CN116401987A - Chip time sequence optimization method, system, equipment and medium - Google Patents
Chip time sequence optimization method, system, equipment and medium Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The invention belongs to the field of computers, and particularly relates to a chip time sequence optimization method, system, equipment and medium. The method comprises the following steps: determining a time sequence path and judging whether the delay time of the time sequence path exceeds a preset time; and adjusting the register positions in the time sequence path according to a predetermined mode based on a netlist equivalence principle in response to the delay time of the time sequence path exceeding a predetermined time. The chip time sequence optimizing method provided by the invention optimizes the circuit time sequence of the chip on the condition that the circuit functional logic of the circuit is not changed after the chip functional design is completed, and when the design time sequence is higher, or in the process of mapping a memory or a digital signal processor, registers which can be absorbed in the circuit are adjusted to the tail end of the circuit as much as possible, so that the influence of the registers on the whole time sequence of the circuit is optimized. Optimizing the design time sequence or reducing the occupied area of the chip.
Description
Technical Field
The invention belongs to the field of computers, and particularly relates to a chip time sequence optimization method, system, equipment and medium.
Background
FPGA (Field Programmable Gate Array), programmable gate array) technology is becoming increasingly popular in recent years for electronic design. The FPGA has the characteristics of hardware logic programmability, large capacity, high speed, embedded storage array and the like, so that the FPGA is particularly suitable for being applied to occasions such as high-speed data acquisition, complex control logic, accurate sequential logic and the like. Timing and area are important indicators in digital application systems.
Further, with the development of modern EDA (Electronic Design Automation ) technology, programmable logic devices have been widely used in digital signal processing, network communication, industrial control, computer related products. Market demands are wide, various demands are induced, and therefore the FPGA is subjected to adaptive design in an iterative mode along with updating of the market demands.
However, in the design of the FPGA, since the functions of the logic loads in the FPGA chip are numerous, after the function is designed, the situation that the chip timing sequence is abnormal or the timing sequence of the local module cannot reach the expected index due to the overlong path of the timing sequence path is easy to occur because of the numerous functional loads of the module. Particularly, when memory mapping or DSP mapping is performed, the lack of a primary register may fail the memory or DSP (Digital Signal Processing, digital signal processor) mapping, and in the integrated stage related to the chip, the integrated result generates more logic resources and wiring resources, which finally results in a larger occupied area of the chip, and affects subsequent layout and wiring.
Therefore, there is a need for an efficient way to solve the above problems.
Disclosure of Invention
In order to solve the above problems, the present invention provides a chip timing optimization method, which includes:
determining a time sequence path and judging whether the delay time of the time sequence path exceeds a preset time;
and adjusting the register positions in the time sequence path according to a predetermined mode based on a netlist equivalence principle in response to the delay time of the time sequence path exceeding a predetermined time.
In some embodiments of the present invention, adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles includes:
an adjustable path is determined and all registers before the output of the adjustable path are adjusted to after the output.
In some embodiments of the present invention, determining the adjustable path and adjusting all registers before the output of the adjustable path to the output includes:
traversing a netlist of sequential paths, judging whether logic devices in the netlist are preset logic devices or not, and taking sequential paths which are continuous to the preset logic devices as paths to be confirmed.
In some embodiments of the invention, the method further comprises:
judging whether the input ends of all logic devices on the path to be confirmed accord with a netlist equivalence principle or not;
and responding to the fact that all logic devices on the path to be confirmed accord with the netlist equivalence principle, and taking the path to be confirmed as an adjustable path.
In some embodiments of the invention, the method further comprises:
and migrating all registers at the input ends of all logic devices in the adjustable path to the output end of the adjustable path, and clearing redundant registers.
In some embodiments of the invention, the method further comprises:
and if any logic device on the path to be confirmed does not accord with the netlist equivalent principle, the path to be confirmed is used as an unadjustable path.
In some embodiments of the invention, the method further comprises:
judging whether a mapping of a preset functional module exists in the time sequence path or not;
in response to the existence of the corresponding function module mapping, judging whether each function module meets the preset mapping requirement;
and in response to the existence of the functional module not meeting the preset mapping requirement, adjusting the position of the register corresponding to the functional module in a preset mode.
In some embodiments of the present invention, determining whether each functional module meets a predetermined timing requirement includes:
judging whether a preset circuit of each functional module is connected with a register;
in response to a predetermined line in the corresponding functional module not being connected to the corresponding register, considering the corresponding functional module as not meeting the predetermined mapping requirement;
and in response to the connection of the corresponding predetermined line in the functional module with the corresponding register, considering the corresponding functional module as meeting the predetermined mapping requirement.
In some embodiments of the present invention, adjusting the location of the register corresponding to the functional module in a predetermined manner includes:
taking a preset line of the functional module as a time sequence path and judging whether the register position in the time sequence path can be adjusted according to a preset mode based on a netlist equivalence principle;
the registers in the predetermined line may be adjusted to the output of the predetermined line in response to the predetermined line by adjusting the register locations in the timing path in a predetermined manner based on netlist equivalence principles.
In some embodiments of the invention, the method further comprises:
in response to a predetermined line being unable to additionally add registers at its output by adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles.
Another aspect of the present invention also proposes a chip timing optimization system, including:
the time sequence judging module is configured to determine a time sequence path and judge whether the delay time of the time sequence path exceeds a preset time;
and the time sequence optimizing module is configured to adjust the positions of the registers in the time sequence path according to a predetermined mode based on a netlist equivalence principle in response to the delay time of the time sequence path exceeding a predetermined time.
Yet another aspect of the present invention is directed to a computer device comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any of the above embodiments.
Yet another aspect of the invention also proposes a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method of any of the above embodiments.
The chip time sequence optimizing method provided by the invention optimizes the circuit time sequence of the chip on the condition that the circuit functional logic of the circuit is not changed after the chip functional design is completed, and when the design time sequence is higher, or in the process of mapping a memory or a digital signal processor, registers which can be absorbed in the circuit are adjusted to the tail end of the circuit as much as possible, so that the influence of the registers on the whole time sequence of the circuit is optimized. Optimizing the design time sequence or reducing the occupied area of the chip.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a chip timing optimization method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a chip timing optimization system according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a computer device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a computer readable storage medium according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of register adjustment of an AND OR gate of a logic device according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of register adjustment of a logic device selector according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a timing optimization process according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
The invention aims to solve the problem of time sequence abnormality caused by each designed functional module of the FPGA in the comprehensive stage of the design of the FPGA chip and optimize the time sequence. Along with iteration of market demands, functions and performance requirements of the FPGA are greatly increased, with the following that design scale of circuit modules in the chip is continuously increased, complex circuits are increased, after functional logic design of the chip is completed due to the increase of the circuits, time sequences of some circuits cannot meet the time sequence requirements at the beginning of the chip design, so that the traditional method adds additional circuits at the comprehensive stage of the chip design to solve the time sequence problem, and the increased circuits finally lead to the increase of occupied area of the chip, influence the overall layout and wiring of the chip and simultaneously cause higher chip power consumption.
As shown in fig. 1, in order to solve the above-mentioned problems, the present invention provides a chip timing optimization method, which includes:
step S1, determining a time sequence path and judging whether the delay time of the time sequence path exceeds a preset time;
and step S2, responding to the time delay time of the time sequence path exceeding a preset time, and adjusting the positions of the registers in the time sequence path according to a preset mode based on a netlist equivalence principle.
In an embodiment of the present invention, the timing path refers to a signal circuit in a chip, i.e., a piece of circuit in which one or more input signals generate one or more output signals according to a designed logic device. The time required from the input to the output of the signal, i.e., the timing, is in clock cycles. Thus, the timing path in this embodiment is broadly referred to as a circuit or signal path that requires a different time to complete an input to an output. Based on the principle of the circuit, the longer the timing path (the longer the computational logic formed by the logic device or other devices in the circuit) the longer the time required to generate the output signal, the longer the timing.
Taking an FPGA chip as an example, a register is an important timing element in FPGA design, and analyzing the timing is essentially the timing analysis between nodes (registers, input and output pins) and if there are no nodes, the timing is not from talking. In an FPGA we can treat a node as a timing analysis from register to register, possibly with some combinational logic filling up between registers. There are four general categories of timing paths: (1) register-to-register type; (2) inputting pins to a register type; (3) register to output pin type; (4) input pin to output pin type. The shift register can adjust the timing of the design. A node may be understood as an input pin, a register, or an output pin. Also, the i.e. timing paths are generally all those satisfying the four types of input-to-output (input includes input from a register, or input from an input pin, and output includes writing data into a register, i.e. output to a register, or output to the outside through a pin of a chip), so that in step S1, all timing paths capable of forming input-to-output in the designed FPGA are extracted from the FPAG design file, and then it is determined whether the consumed time, i.e. clock period, of forming output after passing through a series of logic gates or logic circuits in each timing path satisfies a preset clock period requirement.
In step S2, if the corresponding timing path does not meet the preset timing requirement under the current design, that is, the consumed time (clock period) is longer than the preset value, a netlist (netlist, in the circuit design, for describing the connection relationship between circuit elements) of the timing path is obtained, and it is determined from the netlist whether the registers between the logic devices or the input signals between the logic devices meet the netlist equivalence principle. And if the netlist equivalence principle is met, adjusting the register at the input end of the corresponding logic device to the output end after the corresponding logic device, and further, if the output end of the adjusted logic device is used as the input of the next logic device, namely, is input to the next logic device, and the register also exists at other input ends of the next logic device, namely, the netlist equivalence principle is met, continuing to adjust the register backwards, and so on, adjusting the multi-layer registers in the netlist meeting the netlist equivalence principle to one or more final registers.
In some embodiments of the present invention, adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles includes:
an adjustable path is determined and all registers before the output of the adjustable path are adjusted to after the output.
In some embodiments of the present invention, determining the adjustable path and adjusting all registers before the output of the adjustable path to the output includes:
traversing a netlist of sequential paths, judging whether logic devices in the netlist are preset logic devices or not, and taking sequential paths which are continuous to the preset logic devices as paths to be confirmed.
In some embodiments of the invention, the method further comprises:
judging whether the input ends of all logic devices on the path to be confirmed accord with a netlist equivalence principle or not;
and responding to the fact that all logic devices on the path to be confirmed accord with the netlist equivalence principle, and taking the path to be confirmed as an adjustable path.
In this embodiment, when the corresponding timing path is found not to meet the timing requirement, a netlist of a circuit corresponding to the timing path is obtained, whether each logic device in the netlist is a logic and gate, a logic or gate and a selector MUX is judged according to the input sequence of signals, and a sub-circuit or a sub-netlist which is continuously the three logic devices is used as a path to be confirmed.
Further, on the basis of the path to be confirmed, whether the input ends of all logic devices in the path to be confirmed meet the netlist equivalence principle is judged, if so, all logic devices in the path to be confirmed meet the netlist equivalence principle, namely, the method comprises the following two conditions: 1. registers are present at all (and, or and selector, etc.) inputs of the logic device; 2. no register is present at all inputs of the logic device. The sub-netlist or circuit represented by the path to be verified may be taken as an adjustable path.
In some embodiments of the invention, the method further comprises:
and migrating all registers at the input ends of all logic devices in the adjustable path to the output end of the adjustable path, and clearing redundant registers.
In this embodiment, when the corresponding timing path is found not to meet the timing requirement, a netlist of a circuit corresponding to the timing path is obtained, whether each logic device in the netlist is a logic and gate, a logic or gate and a selector MUX is judged according to the input sequence of signals, and a sub-circuit or a sub-netlist which is continuously the three logic devices is used as a path to be confirmed.
Further, on the basis of the path to be confirmed, whether the input ends of all logic devices in the path to be confirmed meet the netlist equivalence principle is judged, if so, all logic devices in the path to be confirmed meet the netlist equivalence principle, namely, the method comprises the following two conditions: 1. registers are present at all (and, or and selector, etc.) inputs of the logic device; 2. no register is present at all inputs of the logic device. The sub-netlist or circuit represented by the path to be verified may be taken as an adjustable path.
Further, after the adjustable path is determined, registers before and after each logic device in the adjustable path can be moved to the output end of the logic device or adjusted to the final output end of the whole adjustable path, and redundant registers are cleared, so that only the registers on the final output end of the adjustable path are reserved.
Specifically, as for register adjustment of the logic and gate and the logic or gate, as shown in fig. 5, the upper part of the diagram, the signal a and the signal b (the signal a and the signal b can be regarded as other circuit structures or logic devices) are input to the and gate to obtain a result and output to c (the c can be regarded as other circuit structures or logic devices), in the original design, the signal a and the signal b are respectively connected to the register first, then connected to the and gate by the register, in this case, the rule of netlist equivalence is met, the signal a and the signal b can be directly input to the and gate, the corresponding expected result is theoretically given when the signal a and the signal b are both input to the and gate, and meanwhile, the logic of the circuit is not affected by the register is removed. The principle of the same logical or gate adjustment register is the same as that of the logical and gate.
Further, fig. 5 shows a schematic diagram of register adjustment of the selector, i.e. the netlist equivalence principle can only be satisfied when both the input signal and the control signal of the selector have registers, at which time the registers at the input of the selector can be moved to the output.
Further, if the register is adjusted to the output end of the logic device as the input end of the next logic device, and the input end of the next logic device also meets the netlist equivalence principle, the register of the next logic device is continuously adjusted until the register is adjusted to the output end of the whole adjustable path, and the registers of the input ends of all devices in the adjustable path are automatically removed.
Further, in some embodiments of the present invention, the register adjustment process is shown in fig. 7, in which a netlist is traversed (only the and gate and the MUX are traversed, and other elements are encountered to finish the traversal), a sub-netlist (adjustable path) satisfying the timing adjustment is recorded, all input ends of the sub-netlist must have the same registers, that is, initial values and control signals of the registers are the same, then the registers before the shift are deleted in the netlist, all output ends of the sub-netlist are added with one-stage same registers, and finally the sub-netlist is accessed in the netlist.
In some embodiments of the present invention, the length of the adjustable path is dependent on the actual circuit, and the three logic device types and the netlist equivalence principle of each logic device need to be satisfied. It should be noted that in an actual circuit, there may be a plurality of adjustable paths distributed in different sections on a circuit of one function of the chip.
In some embodiments of the invention, the method further comprises:
and if any logic device on the path to be confirmed does not accord with the netlist equivalent principle, the path to be confirmed is used as an unadjustable path.
In this embodiment, when the input end of the corresponding logic device obtained through the netlist meets the netlist equivalence principle, when there is a logic device that does not meet the netlist equivalence principle, the path to be confirmed is regarded as an unadjustable path.
In some embodiments of the invention, the method further comprises:
judging whether a mapping of a preset functional module exists in the time sequence path or not;
in response to the existence of the corresponding function module mapping, judging whether each function module meets the preset mapping requirement;
and in response to the existence of the functional module not meeting the preset mapping requirement, adjusting the position of the register corresponding to the functional module in a preset mode.
In some embodiments of the present invention, determining whether each functional module meets a predetermined timing requirement includes:
judging whether a preset circuit of each functional module is connected with a register;
in response to a predetermined line in the corresponding functional module not being connected to the corresponding register, considering the corresponding functional module as not meeting the predetermined mapping requirement;
and in response to the connection of the corresponding predetermined line in the functional module with the corresponding register, considering the corresponding functional module as meeting the predetermined mapping requirement.
In some embodiments of the present invention, adjusting the location of the register corresponding to the functional module in a predetermined manner includes:
taking a preset line of the functional module as a time sequence path and judging whether the register position in the time sequence path can be adjusted according to a preset mode based on a netlist equivalence principle;
the registers in the predetermined line may be adjusted to the output of the predetermined line in response to the predetermined line by adjusting the register locations in the timing path in a predetermined manner based on netlist equivalence principles.
In some embodiments of the invention, the method further comprises:
in response to a predetermined line being unable to additionally add registers at its output by adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles.
In this embodiment, in the FPGA, when there is a memory map or a digital signal processor map, it is determined whether the memory map or the digital signal processor map is successful, and if the memory map or the digital signal processor map is unsuccessful, the memory map or the digital signal processor map is adjusted by adjusting a register.
Specifically, whether the data bus, the address bus or the control signal of the memory map or the digital signal processor is connected to the register is judged, if the corresponding register is not connected with the register, the memory map or the digital signal processor is not successfully mapped, a register adjusting mode is adopted to adjust the memory map or the digital signal processor, a circuit corresponding to the corresponding data bus, the address bus or the control signal in the memory map or the digital signal processor is used as a time sequence path, a corresponding to-be-confirmed path is determined according to the time sequence path, whether the path to be confirmed is an adjustable path is judged further according to the to-be-confirmed path, and if the path is the adjustable path, the position of the register in the adjustable path is adjusted to the register which is finally used as the output end of the data bus, the address bus or the control signal.
In some embodiments of the invention, when a register cannot be adjusted from a circuit to an output of a signal in a timing path optimized manner for a circuit of a data bus, an address bus, or a control signal, an additional register is added to the output of the data bus, the address bus, or the control signal.
The chip time sequence optimizing method provided by the invention optimizes the circuit time sequence of the chip on the condition that the circuit functional logic of the circuit is not changed after the chip functional design is completed, and when the design time sequence is higher, or in the process of mapping a memory or a digital signal processor, registers which can be absorbed in the circuit are adjusted to the tail end of the circuit as much as possible, so that the influence of the registers on the whole time sequence of the circuit is optimized. Optimizing the design time sequence or reducing the occupied area of the chip.
As shown in fig. 2, another aspect of the present invention further proposes a chip timing optimization system, including:
a timing judgment module 1, wherein the timing judgment module 1 is configured to determine a timing path and judge whether the delay time of the timing path exceeds a predetermined time;
and the time sequence optimizing module 2 is configured to adjust the register positions in the time sequence path according to a netlist equivalence principle in a preset mode in response to the time delay time of the time sequence path exceeding a preset time.
As shown in fig. 3, a further aspect of the present invention further proposes a computer device, including:
at least one processor 21; and
a memory 22, said memory 22 storing computer instructions 23 executable on said processor 21, said instructions 23 when executed by said processor 21 implementing a chip timing optimization method comprising:
determining a time sequence path and judging whether the delay time of the time sequence path exceeds a preset time;
and adjusting the register positions in the time sequence path according to a predetermined mode based on a netlist equivalence principle in response to the delay time of the time sequence path exceeding a predetermined time.
In some embodiments of the present invention, adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles includes:
an adjustable path is determined and all registers before the output of the adjustable path are adjusted to after the output.
In some embodiments of the present invention, determining the adjustable path and adjusting all registers before the output of the adjustable path to the output includes:
traversing a netlist of sequential paths, judging whether logic devices in the netlist are preset logic devices or not, and taking sequential paths which are continuous to the preset logic devices as paths to be confirmed.
In some embodiments of the invention, the method further comprises:
judging whether the input ends of all logic devices on the path to be confirmed accord with a netlist equivalence principle or not;
and responding to the fact that all logic devices on the path to be confirmed accord with the netlist equivalence principle, and taking the path to be confirmed as an adjustable path.
In some embodiments of the invention, the method further comprises:
and migrating all registers at the input ends of all logic devices in the adjustable path to the output end of the adjustable path, and clearing redundant registers.
In some embodiments of the invention, the method further comprises:
and if any logic device on the path to be confirmed does not accord with the netlist equivalent principle, the path to be confirmed is used as an unadjustable path.
In some embodiments of the invention, the method further comprises:
judging whether a mapping of a preset functional module exists in the time sequence path or not;
in response to the existence of the corresponding function module mapping, judging whether each function module meets the preset mapping requirement;
and in response to the existence of the functional module not meeting the preset mapping requirement, adjusting the position of the register corresponding to the functional module in a preset mode.
In some embodiments of the present invention, determining whether each functional module meets a predetermined timing requirement includes:
judging whether a preset circuit of each functional module is connected with a register;
in response to a predetermined line in the corresponding functional module not being connected to the corresponding register, considering the corresponding functional module as not meeting the predetermined mapping requirement;
and in response to the connection of the corresponding predetermined line in the functional module with the corresponding register, considering the corresponding functional module as meeting the predetermined mapping requirement.
In some embodiments of the present invention, adjusting the location of the register corresponding to the functional module in a predetermined manner includes:
taking a preset line of the functional module as a time sequence path and judging whether the register position in the time sequence path can be adjusted according to a preset mode based on a netlist equivalence principle;
the registers in the predetermined line may be adjusted to the output of the predetermined line in response to the predetermined line by adjusting the register locations in the timing path in a predetermined manner based on netlist equivalence principles.
In some embodiments of the invention, the method further comprises:
in response to a predetermined line being unable to additionally add registers at its output by adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles.
As shown in fig. 4, still another aspect of the present invention further proposes a computer readable storage medium 401, the computer readable storage medium 401 storing a computer program 402, the computer program 402 implementing a chip timing optimization method when executed by a processor, comprising:
determining a time sequence path and judging whether the delay time of the time sequence path exceeds a preset time;
and adjusting the register positions in the time sequence path according to a predetermined mode based on a netlist equivalence principle in response to the delay time of the time sequence path exceeding a predetermined time.
In some embodiments of the present invention, adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles includes:
an adjustable path is determined and all registers before the output of the adjustable path are adjusted to after the output.
In some embodiments of the present invention, determining the adjustable path and adjusting all registers before the output of the adjustable path to the output includes:
traversing a netlist of sequential paths, judging whether logic devices in the netlist are preset logic devices or not, and taking sequential paths which are continuous to the preset logic devices as paths to be confirmed.
In some embodiments of the invention, the method further comprises:
judging whether the input ends of all logic devices on the path to be confirmed accord with a netlist equivalence principle or not;
and responding to the fact that all logic devices on the path to be confirmed accord with the netlist equivalence principle, and taking the path to be confirmed as an adjustable path.
In some embodiments of the invention, the method further comprises:
and migrating all registers at the input ends of all logic devices in the adjustable path to the output end of the adjustable path, and clearing redundant registers.
In some embodiments of the invention, the method further comprises:
and if any logic device on the path to be confirmed does not accord with the netlist equivalent principle, the path to be confirmed is used as an unadjustable path.
In some embodiments of the invention, the method further comprises:
judging whether a mapping of a preset functional module exists in the time sequence path or not;
in response to the existence of the corresponding function module mapping, judging whether each function module meets the preset mapping requirement;
and in response to the existence of the functional module not meeting the preset mapping requirement, adjusting the position of the register corresponding to the functional module in a preset mode.
In some embodiments of the present invention, determining whether each functional module meets a predetermined timing requirement includes:
judging whether a preset circuit of each functional module is connected with a register;
in response to a predetermined line in the corresponding functional module not being connected to the corresponding register, considering the corresponding functional module as not meeting the predetermined mapping requirement;
and in response to the connection of the corresponding predetermined line in the functional module with the corresponding register, considering the corresponding functional module as meeting the predetermined mapping requirement.
In some embodiments of the present invention, adjusting the location of the register corresponding to the functional module in a predetermined manner includes:
taking a preset line of the functional module as a time sequence path and judging whether the register position in the time sequence path can be adjusted according to a preset mode based on a netlist equivalence principle;
the registers in the predetermined line may be adjusted to the output of the predetermined line in response to the predetermined line by adjusting the register locations in the timing path in a predetermined manner based on netlist equivalence principles.
In some embodiments of the invention, the method further comprises:
in response to a predetermined line being unable to additionally add registers at its output by adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.
Claims (13)
1. A method for chip timing optimization, comprising:
determining a time sequence path and judging whether the delay time of the time sequence path exceeds a preset time;
and adjusting the register positions in the time sequence path according to a predetermined mode based on a netlist equivalence principle in response to the delay time of the time sequence path exceeding a predetermined time.
2. The method of claim 1, wherein adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles comprises:
an adjustable path is determined and all registers before the output of the adjustable path are adjusted to after the output.
3. The method of claim 2, wherein determining the adjustable path and adjusting all previous registers of the adjustable path output to the output comprises:
traversing a netlist of sequential paths, judging whether logic devices in the netlist are preset logic devices or not, and taking sequential paths which are continuous to the preset logic devices as paths to be confirmed.
4. A method according to claim 3, further comprising:
judging whether the input ends of all logic devices on the path to be confirmed accord with a netlist equivalence principle or not;
and responding to the fact that all logic devices on the path to be confirmed accord with the netlist equivalence principle, and taking the path to be confirmed as an adjustable path.
5. The method as recited in claim 4, further comprising:
and migrating all registers at the input ends of all logic devices in the adjustable path to the output end of the adjustable path, and clearing redundant registers.
6. The method as recited in claim 4, further comprising:
and if any logic device on the path to be confirmed does not accord with the netlist equivalent principle, the path to be confirmed is used as an unadjustable path.
7. The method as recited in claim 1, further comprising:
judging whether a mapping of a preset functional module exists in the time sequence path or not;
in response to the existence of the corresponding function module mapping, judging whether each function module meets the preset mapping requirement;
and in response to the existence of the functional module not meeting the preset mapping requirement, adjusting the position of the register corresponding to the functional module in a preset mode.
8. The method of claim 7, wherein determining whether each functional module meets a predetermined timing requirement comprises:
judging whether a preset circuit of each functional module is connected with a register;
in response to a predetermined line in the corresponding functional module not being connected to the corresponding register, considering the corresponding functional module as not meeting the predetermined mapping requirement;
and in response to the connection of the corresponding predetermined line in the functional module with the corresponding register, considering the corresponding functional module as meeting the predetermined mapping requirement.
9. The method of claim 7, wherein adjusting the location of the register corresponding to the functional module in the predetermined manner comprises:
taking a preset line of the functional module as a time sequence path and judging whether the register position in the time sequence path can be adjusted according to a preset mode based on a netlist equivalence principle;
the registers in the predetermined line may be adjusted to the output of the predetermined line in response to the predetermined line by adjusting the register locations in the timing path in a predetermined manner based on netlist equivalence principles.
10. The method as recited in claim 9, further comprising:
in response to a predetermined line being unable to additionally add registers at its output by adjusting register locations in a timing path in a predetermined manner based on netlist equivalence principles.
11. A chip timing optimization system, comprising:
the time sequence judging module is configured to determine a time sequence path and judge whether the delay time of the time sequence path exceeds a preset time;
and the time sequence optimizing module is configured to adjust the positions of the registers in the time sequence path according to a predetermined mode based on a netlist equivalence principle in response to the delay time of the time sequence path exceeding a predetermined time.
12. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any one of claims 1-10.
13. A computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method of any one of claims 1-10.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117217147A (en) * | 2023-09-21 | 2023-12-12 | 苏州异格技术有限公司 | Logic mapping method, device, equipment and medium for FPGA |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117217147A (en) * | 2023-09-21 | 2023-12-12 | 苏州异格技术有限公司 | Logic mapping method, device, equipment and medium for FPGA |
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