CN105843986B - It is a kind of based on FPGA can automatic extended address control system - Google Patents
It is a kind of based on FPGA can automatic extended address control system Download PDFInfo
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- CN105843986B CN105843986B CN201610143865.2A CN201610143865A CN105843986B CN 105843986 B CN105843986 B CN 105843986B CN 201610143865 A CN201610143865 A CN 201610143865A CN 105843986 B CN105843986 B CN 105843986B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Abstract
The present invention relates to it is a kind of based on FPGA can automatic extended address control system, including an address generating module, multiple address decoder modules and multiple address control modules, the corresponding address decoder module of each column, the corresponding address control module of every a line, address generating module generates an address, address passes to each address decoder module by the first bus, after address decoder module receives address, it is compared according to the address of itself, it decodes out address and opens Word Line, after return to a signal to address control module, address control module judges current line either with or without there is signal, and address generating module is transmitted to by the second bus, address generating module is according to signal to the corresponding portion clearing of address or plus one.The control system is used for the modules assignment configuration data in FPGA, address can spread, be applicable in the FPGA of each scale, high reliablity, flow risk is small.
Description
Technical field
The invention belongs to the technical fields of programmable logic device, are related to a kind of control system, and especially one kind is based on
FPGA can automatic extended address control system.
Background technique
Programmable logic device FPGA, by software tool, exploitation, emulation and test, rapidly by design programming to device
In part, a large amount of non-repeatability engineering cost and circuit R&D cycle are saved, while programmable logic device is matched based on repetition
The memory technology set, it is only necessary to re-download programming, the modification of circuit can be completed.Programmable logic device has the development cycle
Short, at low cost, risk is small, and integrated level is high, and flexibility is big, and the advantages that be convenient for electronic system maintenance and upgrade, therefore receives
The favor of vast end product user, becomes the mainstream of IC chip, and be widely used in various fields as communication,
Control, video, information processing, electronics, internet, automobile and aerospace etc..
Programmable logic device FPGA mainly includes control system, programmable logic cells CLB, Digital Signal Processing
DSP, storage unit BRAM and some high-speed interfaces, clock module and IP kernel etc., and control system is programmable logic device
In most important structure, be the interface of software download programming, be the control system of each module in the entire FPGA of configuration, only control
System accurate can download to the bitstream of Software Create in configuration SRAM, FPGA and could work normally.It realizes
Corresponding bitstream is downloaded in corresponding configuration SRAM, address control system is just had to.Because exploitation is different now
The FPGA of scale, it is necessary to which the FPGA of different scales size cannot be total to by redesigning a set of corresponding address control system
With a set of address control system, since every a set of address control system of design needs human cost and address control newly developed
System can have certain risk.But regardless of different scales size FPGA all share a set of control system if would not exist
The risk of flow.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the existing defects, and providing one kind can automatic extended address based on FPGA
Control system, address can be with arbitrary extension, the flexible convenient FPGA for adapting to each scale.
In order to solve the above-mentioned technical problems, the present invention provides the following technical solutions:
The present invention it is a kind of based on FPGA can automatic extended address control system, an including address generating module is multiple
Address decoder module and multiple address control modules, the corresponding address decoder module of each column, the corresponding address of every a line
Control module, address generating module generate an address, and address passes to each address decoder module, ground by the first bus
After location decoder module receives address, compared according to the address of itself, decode out address open Word Line, after return
A signal is returned to address control module, address control module judge that current line either with or without there is signal, and passes through the second bus
It is transmitted to address generating module, address generating module is according to signal to the corresponding portion clearing of address or plus one.
Further, the address that address generating module generates is divided into 3 parts: RowAddress, ColumnAddress,
Minor Address, and the bit wide of address can be increased.
Further, FPGA includes input/output port, storage unit, programmable logic cells and Digital Signal Processing, and
Module can arbitrarily be increased, increase line number.
Further, each module corresponds to an address decoder module, the MinorAddress of each module in FPGA
Address is different, and the MinorAddress in the corresponding address decoder module of each module for comparing is in different size.
Further, each address decoder module of every a line, for returning to COLUMN_CNT_EN signal.
Further, the last one address decoder module of every a line other than last line, for returning to ROW_
CNT_EN signal.
Further, the last one address decoder module of last line, for returning to ROW_CNT_EN, ROW_END letter
Number.
Further, address control module, for judging current line either with or without there is ROW_CNT_EN, COLUMN_CNT_
EN, ADDR_END signal, and it is transmitted to address generating module.
Further, address generating module is the counter of a generation address.
Beneficial effects of the present invention: the control system is used for the modules assignment configuration data in FPGA, to reach
FPGA meets the function that user wants, and therefore, the control system configurability is strong, address can spread, be applicable to each
In the FPGA of scale, high reliablity, flow risk is small.
Detailed description of the invention
Fig. 1 is the module diagram in FPGA of the present invention；
Fig. 2 be the present invention it is a kind of based on FPGA can automatic extended address control system address structure figure；
Fig. 3 be the present invention it is a kind of based on FPGA can automatic extended address control system architecture diagram.
Specific embodiment
Embodiment cited by the present invention, is merely used to help understand the present invention, should not be construed as protecting model to the present invention
The restriction enclosed for those skilled in the art without departing from the inventive concept of the premise, can also be right
The present invention makes improvements and modifications, these improvement and modification are also fallen into the range of the claims in the present invention protection.
As shown in Figure 1, the module in FPGA includes: input/output port IOB, storage unit BRAM, programmable logic cells
CLB, Digital Signal Processing DSP can arbitrarily increase module according to design requirement, increase line number.
As shown in Fig. 2, being one 32 address structures, it is segmented into 3 parts: RowAddress: which row is represented,
ColumnAddress: which module in current line is represented, MinorAddress: represents the specific address in current block, root
Need to increase the bit wide of address according to design.
The present invention it is a kind of based on FPGA can automatic extended address control system description:
As shown in Figure 1, the module in FPGA includes input/output port IOB, storage unit BRAM, programmable logic cells
CLB, Digital Signal Processing DSP, each module corresponds to an address decoder module Addr_decoder, due to each module
The address MinorAddress it is different, therefore for comparing in each module corresponding address decoder module Addr_decoder
MinorAddress size is also different.
As shown in figure 3, every the last one address decoder module of a line (in addition to last line ROW Last), corresponding A ddr_
Decoder (5), for returning to ROW_CNT_EN signal, namely line feed enable signal.
As shown in figure 3, the last one address decoder module of last line ROW Last, corresponding A ddr_decoder (6),
For returning to ROW_CNT_EN, ROW_END signal namely end of address (EOA) enable signal.
As shown in figure 3, the corresponding address control module Addr_ctrl (3) of every a line, for judge current line either with or without
There is ROW_CNT_EN, COLUMN_CNT_EN, ADDR_END signal, and is transmitted to address generating module by the second bus (2)
Addr_gen(7)。
As shown in figure 3, address generating module Addr_gen (7) is a counter for generating address, MinorAddress
It is adding up always, is only receiving COLUMN_CNT_EN signal, MinorAddress can be reset, and Column_Address just adds one；
When receiving ROW_CNT_EN signal, MinorAddress can be reset, and Column_Address can be reset, and RowAddress adds one；
When receiving ADDR_EN signal, MinorAddress can be reset, and Column_Address can be reset, and RowAddress can be reset, ground
Location generation module Addr_gen (7) terminates.
The present invention it is a kind of based on FPGA can automatic extended address control system principle:
As shown in figure 3, generating an address by address generating module Addr_gen (7), this address includes (as shown in Figure 2)
RowAddress, ColumnAddress, MinorAddress.Address passes to the decoding of each address by the first bus (1)
Modules A ddr_decoder (4,5,6).Address decoder module Addr_decoder (4,5,6) can be according to itself after receiving address
Address compare, decode out address open Word Line.
Address decoder module Addr_decoder (4) terminates that a COLUMN_CNT_EN signal can be returned, and address is told to produce
The address of raw modules A ddr_gen (7) this module is over, and address generating module Addr_gen (7) will be Minor
Address is reset, and ColumnAddress adds one.
Address decoder module Addr_decoder (5) is to correspond in the last one module of a line every (in addition to last line),
To return to ROW_CNT_EN end signal, the address of address generating module Addr_gen (7) this line is told to be over, ground
Location generation module Addr_gen (7) will reset MinorAddress, and ColumnAddress is reset, and RowAddress adds one.
Address decoder module Addr_decoder (6) is the last one module of corresponding last line, to return to ADD_END
End signal tells address generating module Addr_gen (7) all addresses have counted to terminate, address generating module Addr_gen
(7) MinorAddress will be reset, ColumnAddress is reset, and RowAddress is reset.
Module in FPGA can arbitrarily increase module according to design requirement, increase line number, what address generating module generated
Address can increase its bit wide according to the design needs, therefore, address can any spread, it is flexibly convenient to be suitable for each scale
FPGA in, high reliablity, flow risk is small；The control system is used for the modules assignment configuration data in FPGA, with
Reach FPGA and meet the function that user wants, therefore, the control system configurability is strong, regardless of the FPGA of different scales size
A set of control system is all shared, human cost reduces, and development risk is small.
Claims (9)
1. it is a kind of based on FPGA can automatic extended address control system, it is characterised in that: it is more including an address generating module
A address decoder module and multiple address control modules, the corresponding address decoder module of each column, the corresponding ground of every a line
Location control module, address generating module generate an address, and address passes to each address decoder module by the first bus,
It after address decoder module receives address, is compared according to the address of itself, decodes out address and open Word Line, after
A signal is returned to address control module, address control module judge current line either with or without there is signal, and it is total by second
Line is transmitted to address generating module, and address generating module is according to signal to the corresponding portion clearing of address or plus one；
Address decoder module Addr_decoder (4) terminates that a COLUMN_CNT_EN signal can be returned, and address is told to generate mould
The address of block Addr_gen (7) this module is over, and address generating module Addr_gen (7) will be MinorAddress
It resets, ColumnAddress adds one；
Address decoder module Addr_decoder (5) is to correspond in the last one module of a line every (in addition to last line), to
ROW_CNT_EN end signal is returned, the address of address generating module Addr_gen (7) this line is told to be over, is produced from address
Raw modules A ddr_gen (7) will reset MinorAddress, and ColumnAddress is reset, and RowAddress adds one；
Address decoder module Addr_decoder (6) is the last one module of corresponding last line, is terminated to return to ADD_END
Signal tells address generating module Addr_gen (7) all addresses have counted to terminate, address generating module Addr_gen (7)
MinorAddress will be reset, ColumnAddress is reset, and RowAddress is reset.
2. it is according to claim 1 based on FPGA can automatic extended address control system, it is characterised in that: the address
The address that generation module generates is divided into 3 parts: Row Address, Column Address, Minor Address, and can increase
The bit wide of address.
3. it is according to claim 1 based on FPGA can automatic extended address control system, it is characterised in that: the FPGA
It including input/output port, storage unit, programmable logic cells and Digital Signal Processing, and can arbitrarily increase module, increase
Line number.
4. it is according to claim 3 based on FPGA can automatic extended address control system, it is characterised in that: the FPGA
In each module correspond to an address decoder module, the address Minor Address of each module is different, each module pair
Minor Address in the address decoder module answered for comparing is in different size.
5. it is according to claim 1 based on FPGA can automatic extended address control system, it is characterised in that: it is described each
Each capable address decoder module, for returning to COLUMN_CNT_EN signal.
6. it is according to claim 1 based on FPGA can automatic extended address control system, it is characterised in that: in addition to last
The last one address decoder module of every a line outside a line, for returning to ROW_CNT_EN signal.
7. it is according to claim 1 based on FPGA can automatic extended address control system, it is characterised in that: last line
The last one address decoder module, for returning to ROW_CNT_EN, ROW_END signal.
8. it is according to claim 1 based on FPGA can automatic extended address control system, it is characterised in that: the address
Control module, for judging that current line either with or without there is ROW_CNT_EN, COLUMN_CNT_EN, ADDR_END signal, and passes
To address generating module.
9. it is according to claim 1 based on FPGA can automatic extended address control system, it is characterised in that: the address
Generation module is the counter of a generation address.
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| EP1202165A2 (en) * | 2000-10-30 | 2002-05-02 | Hewlett-Packard Company (a Delaware corporation) | Generation of cryptographically strong random numbers using MISR registers |
| CN102789190A (en) * | 2011-05-20 | 2012-11-21 | 中国科学院微电子研究所 | Column address distributor circuit suitable for different types of FPGA (field programmable gate array) circuit programming |
| CN104598405A (en) * | 2015-02-03 | 2015-05-06 | 杭州士兰控股有限公司 | Expansion chip and expandable chip system and control method |
| CN104881373A (en) * | 2014-12-05 | 2015-09-02 | 中国航空工业集团公司第六三一研究所 | Method for expanding access spaces of memories |
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| KR101820505B1 (en) * | 2011-06-28 | 2018-03-02 | 에스케이플래닛 주식회사 | Apparatus and method for generating address book based on user relationship and record medium |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1202165A2 (en) * | 2000-10-30 | 2002-05-02 | Hewlett-Packard Company (a Delaware corporation) | Generation of cryptographically strong random numbers using MISR registers |
| CN102789190A (en) * | 2011-05-20 | 2012-11-21 | 中国科学院微电子研究所 | Column address distributor circuit suitable for different types of FPGA (field programmable gate array) circuit programming |
| CN104881373A (en) * | 2014-12-05 | 2015-09-02 | 中国航空工业集团公司第六三一研究所 | Method for expanding access spaces of memories |
| CN104598405A (en) * | 2015-02-03 | 2015-05-06 | 杭州士兰控股有限公司 | Expansion chip and expandable chip system and control method |
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Effective date of registration: 20201217 Address after: 2 / F, building B1, No. 777, Jianzhu West Road, Binhu District, Wuxi City, Jiangsu Province, 214000 Patentee after: WUXI ZHONGWEI YIXIN Co.,Ltd. Address before: Hui Road Binhu District 214035 Jiangsu city of Wuxi province No. 5 Patentee before: The 58th Research Institute of China Electronics Technology Group Corp. |