CN1088301C

CN1088301C - Trellis coded modulation system for HDTV

Info

Publication number: CN1088301C
Application number: CN95191650A
Authority: CN
Inventors: 理查德·W·西塔; 戴维·A·威尔明
Original assignee: Zenith Electronics LLC
Current assignee: Zenith Electronics LLC
Priority date: 1994-07-08
Filing date: 1995-06-29
Publication date: 2002-07-24
Anticipated expiration: 2015-06-29
Also published as: CA2181539A1; KR100234865B1; JP3354938B2; US5600677A; US5583889A; MX9603333A; CA2181539C; CN1141108A; JPH10502776A; BR9507201A; WO1996002100A1; US5636251A

Abstract

A trellis coded modulation system comprises a source of successive 2-bit data symbols X1, X2 arranged in a frame format wherein each frame comprises a plurality of data segments each including a plurality of groups of interleaved data symbols. Each group of interleaved data symbols is separately coded by a precoder (32a) and convolution encoder (32b) to derive coded output symbols Z0, Z1, Z2, which are mapped to respective 8-level symbols for transmission together with periodically generated frame and segment sync symbols. The received signal may be filtered by a linear filter (42), e.g. a comb filter (42), to reduce co-channel interference and each group of filtered symbols is applied to a respective first Viterbi decoder (44) for estimating data bits X1, X2.

Description

The trellis coded modulation system that is used for high definition TV

The present invention relates to lattice battle array coded modulation (TCM) and send and receiving system, and relate in particular to the use of TCM in high definition TV (HDTV) is used.

Lattice battle array coded modulation is the technology that a kind of known being used for improves the performance of digital transmission and receiving system.Signal to noise ratio under the given power level is improved, perhaps alternatively can be reduced to and reach the required transmitted power of given signal-to-noise performance.In essence, TCM comprises and adopts one every K input data bit transition of data bit list entries become the multimode convolution coder of k+n carry-out bit, and so is referred to as ratio k/ (k+n) convolution coder.Become these carry-out bit maps the discrete symbols sequence of a MCW modulated carrier wave (to have 2 in order to send data then ^(k+n)Individual value).These symbols possibilities for example, comprise 2 ^(k+n)Individual phase value or amplitude.By the input data bit being encoded in a kind of sequence mode relevant with state, can increase the minimum euclid distance that allows to send between the sequence, and cause when in receiver, using maximum likelihood decoder (for example Viterbi decoder), error probability being reduced.

Fig. 1 briefly represents a system of the above-mentioned type.By the sequence convolution coder 10 relevant with state of a k/ (k+n) ratio, every k position of input traffic converts k+n carry-out bit to.Every group of (k+n) individual carry-out bit then becomes 2 by mapper 12 maps ^(k+n)In the individual symbol one.These symbols are sent on a selected channel by transmitter 14.Receiver comprises a tuner 16 that is used for the signal transition that is received on the selected channel is become intermediate-freuqncy signal, and this intermediate-freuqncy signal is demodulated to base-band analog signal by demodulator 18.This analog signal is suitably sampled by A/D converter 20 so that the symbol that recovers to be sent is followed these symbols and is applied to the Viterbi decoder 22 that is used to recover an original k data bit again.

United States Patent (USP) 5,087, disclosing for No. 975 a kind of is residual sideband (VSB) system that form sends TV signal with in succession M level symbol on standard 6MHz television channel.The symbol rate optimal fixation is for being about 684H (about 10.76 million symbol/seconds), and wherein H is the NTSC horizontal frequency.In order to reduce NTSC common-channel interference in the receiver, it is 12 symbol clocks receiver comb filter at interval that this patent also openly adopts a feedforward to postpone.For the operation of convenient receiver comb filter, source data is the mode filter precodings at interval of 12 symbol clocks by a feedback delay.Encoder replaces this comb filter that the signal that is received is handled can adopt a complementary modulus in this obtains receiver in the system of patent after, and the signal-to-noise performance that produces descends so that avoid under the situation that does not have tangible NTSC common-channel interference therefore.

An object of the present invention is to provide a kind of and TCM technology and and the digital transmission and the receiving system of receiver comb filter combination, to reach signal-to-noise performance with improvement that the NTSC common-channel interference reduces.

Another object of the present invention provides a kind of digital transmission and receiving system of the above-mentioned type, and the complexity of receiver obtains simplifying not obviously under the prerequisite that reduces performance in this system.

A further object of the present invention is frame structure and the synchro system that a kind of novelty is provided for digital television signal.

Of the present invention these with and other objects and advantages will along with following become together with the description of the drawings clear.

Technical scheme of the present invention:

According to one embodiment of present invention, a kind of trellis coded modulation system comprises the 2 bit data symbol X in succession that arrange with a kind of form of frame ₁, X ₂, a source forming, wherein each frame comprises a plurality of data segments, each data segment comprises the staggered data symbols of many groups.The staggered data symbol of each group is encoded respectively by a precoder and convolution coder, to derive the output symbol Z of coding ₀, Z ₁, Z ₂, they are sent with frame and section synchronizing symbol with regular generation to corresponding 8 level symbols by map.The signal that receives can carry out filtering by a linear filter (for example comb filter), and reducing common-channel interference, and the symbol of respectively organizing filtering is added to a corresponding Viterbi decoder with data estimator position X ₁, X ₂Each first decoder preferably includes the Viterbi decoder that a complexity reduces, and it is represented in response to a kind of part of the state of linear filter.The symbol of each group of received also can directly be added to corresponding the 2nd a Viterbi decoder with data estimator position X ₁, X ₂Data bit X from the estimation of first or second decoder ₁, X ₂Obtain selecting, to be further processed.

An advantage of the present invention is, the invention provides a kind of numeral and sends and receiving system, and it had both comprised that the TCM technology had also comprised a kind of receiver comb filter, with the S/N performance of realization improvement and reducing of NTSC common-channel interference.

A further advantage of the present invention, the numeral that has provided aforementioned type sends and receiving system, and wherein the complexity of receiver is reduced, and does not reduce performance significantly.

The present invention also provides a kind of frame structure that is used for digital television signal and synchro system of novelty.

Fig. 1 is the system block diagrams of the TCM system of best MLSE (maximum-likelihood sequence estimation) Viterbi of the employing of routine decoder;

Fig. 2 A is according to the TV signal transmitter of the TCM system that adopts Viterbi decoding and the system block diagrams of receiver of comprising of the present invention;

Fig. 2 B is a kind of calcspar of selecting execution mode fully of the receiver of Fig. 2 A;

The symbol interleave that is caused in the transmitter of Fig. 3 presentation graphs 2;

Fig. 4 is the circuit 32 of presentation graphs 2 and the calcspar of circuit 34 in more detail;

Fig. 5 is the chart of mapper 49 operations in the presentation graphs 4;

Fig. 6 is a table, the operation of the convolution coder 32b of presentation graphs 4;

Fig. 7 is the lattice battle array state transition graph according to the table of Fig. 6;

Fig. 8 is the

circuit

42,44,46 of presentation graphs 2 and a calcspar of 48 in more detail;

Fig. 9 is the functional block diagram of the optimum MLSE Viterbi decoder 46A-46L of Fig. 8;

Figure 10 is a circuit diagram, and this circuit can replace the Viterbi decoder 46A-46L of Fig. 8 to be used for recovering position Y ₁And Y ₂Estimation;

Figure 11 is the functional block diagram of the most preferably MLSE Viterbi decoder 44A-44L of Fig. 8;

Figure 12 is a table, represents the operation of TCM encoder of the present invention, the effect of being introduced comprising the comb filter 42 of the receiver of Fig. 2;

Figure 13 represents effect that two subclass of 42 li of comb filter make up and the coset as a result that is produced;

Figure 14 represents seven cosets occurring in the table of Figure 13;

Figure 15 is the lattice battle array state transition graph according to the table of Figure 12;

Figure 16 is the functional block diagram according to the Viterbi decoder of the lattice system of battle formations programming of Figure 15;

Figure 17 is a calcspar, the position X that expression utilizes the Viterbi decoder of Figure 16 to recover to be sent ₁And X ₂Estimation;

The state of the

delay unit

48,54 and 56 of Figure 18 presentation graphs 4 after between a section synchronization zone;

Near the form of the signal that the output of the multiplexer 62 of Figure 19 presentation graphs 4 is produced a segment sync signal;

Figure 20 is the calcspar after the comb filter 42 that is used for deal with data segment signal and frame synchronizing signal among Fig. 8 is modified;

Figure 21 is the calcspar after the back encoder 48A-48L that is used for deal with data segment signal and frame synchronizing signal among Fig. 8 is modified;

Figure 22 is illustrated in the form of the signal that near the output of the multiplexer 62 of the Fig. 4 the frame synchronizing signal produces;

Figure 23 represents one embodiment of the present invention, realizes the raising of position transmission rate in this embodiment by the input data that the form that each symbol has 3 positions is provided;

Figure 24 A and 24B represent the application of the present invention in QAM (quadrature amplitude modulation) system; And

Figure 25 A and 25B represent to be respectively applied for the structure of the back encoder in the receiver in Figure 23 and the embodiments of the present invention shown in Figure 24.

Fig. 2 A briefly represents one and is applied to ' the multistage VSBHDTV of No. 975 disclosed types of patent sends and the TCM system of receiving system.Multistage VSB HDTV uses although wait in expectation in the preferred forms of the present invention, but it is more general to should be appreciated that the present invention comes down to, thereby can be applicable to the transmission and the receiving system of other type, comprise the low-resolution video system and be the data system of base with the non-video.And, can adopt other modulation technique, for example adopt the modulation technique of quadrature amplitude modulation (qam).

Refer again to Fig. 2 A, data source 24 provides a series of data byte, these bytes may, for example, comprise compressed video signals or any other digital data signal of HDTV signal, NTSC (NTSC) definition of compression.Although not necessarily, the byte align that preferably makes data is in frame in succession, and each frame comprises 262 and 263 data segments on a kind of benchmark that replaces, and each data segment is formed by two bit signs that about 10.76 million symbols/second, symbol rate occurred by 684.Be applied to from the data byte of data source 24 and be used for carrying out the Reed-Solomon encoder 26 of forward error correction coding and then being applied to byte interleaver 28, data source 24 also provides a plurality of timing signals simultaneously.In order to reduce the susceptibility of system to burst noise, byte interleaver 28 rearranges the total data byte of a frame.

Be applied to symbol interleaver 30 from data byte behind the interleave of interleaver 28, the latter provides two output bit stream X by character rate in a kind of preferred forms ₁, X ₂, each position is to X ₁, X ₂Corresponding to a data symbol.Especially, owing in receiver, have comb filter (below will go through), need be 2 bit signs of each data segment interleave in 12 son section A-L, each son section comprises 57 symbols as shown in Figure 3.Each son section, for example sub-section A, thus comprising for example A0-A56 of 57 symbols, each height section is each other by separating between 12 sign fields.Symbol interleaver 30 carries out work by four consecutive symbols that 2 bit signs of each data byte that is applied rearranged into corresponding son section.Thereby, for example, four 2 bit signs that impose on first data byte of interleaver 30 are provided as output symbol A0, A1, A2 and the A3 of son section A, and four 2 bit signs of second data byte that is applied become output symbol B0, B1, B2 and the B3 of son section B, and by parity of reasoning.This guarantees that each symbol of each data byte is done the as a whole processing that obtains in encoder and receiver.

2 bit sign streams from interleaver 30 are coupled to a precoder qualifying battle array encoder 32, so that convert 3 carry-out bits that below will be described in more detail to.Because the characteristics of unit 32 are 12 symbol delays, can it be envisioned as be by parallel that constitute and each encoder of 12 encoders by 1/12 symbol clock speed operation, and each height section that imagination interleaver 30 produces is handled by one in these parallel encoders respectively.The 3 bit sign streams that output place of unit 32 generates are applied to the VSB modulator 36 of symbol mapper and synchronous inserter 34 and back, so that send by a plurality of 8 grades of symbols.

Send signal and received by a receiver, this receiver comprises corresponding to the tuner of square among Fig. 1 16,18 and 20, demodulator and A/D converter 40.The output of unit 40 is made up of (for example 8-10 position) 8 grades of symbols streams of multidigit, (execution mode of a kind of example of the circuit of console switch 50 is referring to United States Patent (USP) 5 for

parts

50a, 50b, 50c and the 50d of these symbols by selector switch 50,260, No. 293) be applied to by first handling on the path and that a comb filter 42 and a Viterbi decoder 44 constitute by second handling on the path that the 2nd Viterbi decoder 46 and back encoder 48 constitute.Each is handled path and comprises an equalizer 38 that is connected between switching part 50b and the 50c.Both output of Viterbi decoder 44 and back encoder 48 each by bit stream X ₁, X ₂Reconstruction form.The parts 50d of selector switch 50 the bit stream that is applied to X ₁, X ₂Be coupled to symbol and go on the interleaver 52, the latter rebuilds original data byte.These data bytes go interleaver 54 to remove interleave by byte and by 56 error correction of Reed-Solomon decoder, so that be applied on the other parts of this receiver then.

A kind of execution mode of selecting fully of the receiver of presentation graphs 2A among Fig. 2 B.This execution mode except a Viterbi decoder 45 only is provided substantially with the system class of Fig. 2 A seemingly.More particularly, 45 responses of Viterbi decoder are from the control signal of selector switch 50, when selecting first to handle path, bear first layout of the function that realizes Viterbi decoder 44, and when selecting second to handle path, bear second layout of the function that realizes Viterbi decoder 46.

Referring to Fig. 4, unit 32 comprises that (each symbol is identified as an X from the symbol of interleaver 30 in a reception ₁, X ₂) and produce carry-out bit Y ₁, Y ₂Mould 2 feedback precoder 32a.More particularly, precoder 32a comprises that its first input end is used for connecting an acceptance position X ₂With its second input and generation carry-out bit Y ₂The modulo 2 adder 44 that connects of adder output, this adder output is connected with adder second input with one 12 symbol delay parts 47 by a multiplexer 46.Its input is also got back in the output of delay unit 47 by multiplexer 46 couplings.The carry-out bit Y of adder 44 ₂As position Z ₂Be applied on the input of symbol mapper 49 of more detailed expression in Fig. 5.

Not bits of coded Y from precoder 32a ₁Be applied to 1/2 speed, 4 states, system feedback convolution coder 32b, to convert carry-out bit Z to ₁And Z ₀Convolution coder 32b comprises that one is used for directly position Y ₁Be applied on second input of symbol mapper 49 as a position Z ₁And be applied to the signal path 51 of an input of modulo 2 adder 52.Be applied to the input of 12 symbol delay parts 54 by the output of multiplexer 53 adders 52, the latter's output is applied on the 3rd input of symbol mapper 49 with as a position Z ₀And be applied to the input of the 2 12 symbol delay parts 56 by second multiplexer 55.The output of delay unit 56 imposes on second input of adder 52.By

multiplexer

53 and 55,

delay unit

54 and 56 output also respectively coupling get back to their inputs separately.Each

delay unit

47,54 and 56 is pressed character rate (about 10.76 million symbol/seconds) timing.In order to characterize the operation of these symbol delay parts respectively, preferably handle each height section A-L (see figure 3) individually by precoder 32a and convolution coder 32b.

Can adopt at convolution coder 32b under prerequisite of the present invention and to be different from form shown in Figure 4.For example, the quantity of coder state can be different from the quantity shown in the figure, can adopt feed forward architecture rather than disclosed feedback arrangement, and can adopt nonsystematic coding in feedback or any of feed forward architecture.

Multiplexer

46,53 and 55 allows to be used for synchronous insertion during being arranged in the moment of selecting their B inputs separately.Select the A input of multiplexer constantly in other all.The operation of convolution coder 32b and mapper 49 (hereinafter referred to as lattice battle array encoder (TE) 60) is in this case represented in the operation of this circuit when investigating the A input when each multiplexer of selection and temporarily ignore the effect of precoder 32a, the table among Fig. 6.The delay unit 56 of arbitrary time n convolution coder 32b and four kinds of possibility state Q of 54 are shown in first tabulation of this table ₁Q ₀These states are 00,01,10 and 11.Secondary series is illustrated in each state Q of time n encoder 32b ₁Q ₀The next Y ₂Y ₁Possible values.The 3rd row representative of this table is at time n position Y ₂Y ₁With coder state Q ₁Q ₀Various combinations under carry-out bit Z ₂Z ₁Z ₂Each value.For example, be in state Q as encoder 32b ₁Q ₀=01, position Y ₂Y ₁Made carry-out bit Z at=10 o'clock ₂Z ₁Z ₀=101.Symbol mapper 49 (see figure 5)s response carry-out bit Z is shown in the 4th tabulation that is denoted as this table of R (n) ₂Z ₁Z ₀The amplitude of the symbol that provides.Because there are three carry-out bits, be provided with 8 symbol levels (7 ,-5 ,-3 ,-1 ,+1 ,+3 ,+5 and+7).For example, carry-out bit Z ₂Z ₁Z ₀=101 make call sign mapper 49 produce symbol level+3.At last, the state of encoder 32b at time (n+1) shown in the 5th of this table the tabulation.Should be appreciated that, because the length of each

delay unit

54 and 56 is 12 symbols, for the symbol of each height section A-L state Q at time n and the encoder 32b that (n+1) locates ₁Q ₀Representative coder state conversion in succession.

Can observe out 8 grades of symbols that produce at the output of mapper 49 is symmetrical for zero level.For the signals collecting in the convenient receiver, the most handy specified rate (for example+1 unit) is setovered each symbol so that a directed component to be provided actually.Then symbol and directed component are applied to modulator 36 (see figure 2)s so that selected carrier wave is modulated, send thereby press suppressed carrier modulation format illustrated in No. 975 patent of above mentioned ' through multiplexor 62.The output of mapper 49 also is applied to the input of RAM64, and the output of RAM64 is applied on second input of multiplexer 62.The 3rd input of multiplexer 62 provided by section and frame synchronizing signal source 66.

Referring to the symbol mapper 49 of Fig. 5, can observe out 8 symbol level and be divided into 4 subclass a, b, c and d again, each subclass is only by carry-out bit Z ₁Z ₀A kind of particular state sign.Like this, carry-out bit Z ₁Z ₀-00 selects character subset d, Z ₁Z ₀=01 selects character subset c, Z ₁Z ₀=10 select character subset b, and Z ₁Z ₀=11 select subclass a.In each subclass, the size of the difference between each symbol amplitude is 8 units.Can also observe out in succession symbol level (7 ,-5), (3 ,-1), (+1 ,+3) and (+5 ,+7) is by carry-out bit Z ₂Z ₁Common state select.Thereby, for example, carry-out bit Z ₂Z ₁=00 selects two kinds of symbol amplitude levels-7 and-5, and and the like.Such as will be described in more detail below, above-mentioned these two characteristics of symbol mapper 49 are useful for the complexity of simplified receiver.

Fig. 7 is the state transition graph of the convolution coder 32b that derivation is come out from the table of Fig. 6.The figure shows four kinds of states of this encoder and the various conversions between these states.Especially, each state has two parallel transfers, respectively extends on the identical or different states.These transfers are by the input position Y that causes state exchange ₂Y ₁And the result of mapper 49 exports, and R indicates.As will explaining in more detail below, this state diagram can be used for designing in the receiver one and be used for recovering a position Y ₂And Y ₁Technical known optimum maximum likelihood sequencal estimation (MLSE) the Vilerbi decoder of estimation.

Fig. 8 represents the decoded mode of receiver of the present invention in more detail.The multidigit value of symbol that comes self-tuner, demodulator, A/D converter 40 first is handled that path is applied on first demultplexer 70 and second is handled path and be applied on second demultplexer 72 by what be made of equalizer 38 by what be made of comb filter 42 and equalizer 38.Comb filter 42 is made up of a feedforward filter that comprises

linear adder device

72 and 12 symbol delay parts 76.As more fully mentioned in front ' in No. 975 patents explain, this filter can work in by deduct between 12 sign fields the symbol that is received before this from the symbol of each reception and reduce the NTSC common-channel interference.Because in transmitter, have the symbol interleave, be A for form is provided ₁, A ₀, B ₁-B ₀Treat the output of comb shape in succession of grade, this comb filter is worked on each height section independently.These comb shape outputs corresponding one output among the son section A-L by each correspondence that demultplexer 70 is distributed into 12 units.The son section of each combing is applied to the Viterbi decoder 44A-44L by the speed operation of 1/12 symbol clock speed (fs) of a correspondence respectively by demultplexer 70.It is a pair of by to an input position X that each decoder 44A-44L provides ₁X ₂The output decoded bits that constitutes of estimation, this becomes as shown in Figure 3 interleave bit stream to decoded bits by multiplexer 78 multipath conversion.

Interleave symbol from unit 40 also is distributed into 12 independent son section A-L by demultplexer 72 multichannels, and each height section is applied on the corresponding Viterbi decoder 46A-46L.Thereby as can be seen from each initial data byte of data source 24 as a unit by corresponding among a decoder 46A-46L processing.For example, by symbol A ₃A ₂A ₁A ₀The data byte of representative is handled by decoder 46A, and and the like.This situation also is correct for decoder 44A-44L certainly, but their handled symbols obtain the combing of filter 42 in advance.

Decipher so that recover a position Y in order to carry out optimum MLSE Viterbi according to technical known method ₂And Y ₁Estimation, each decoder 46A-46L can comprise one by the operation of 1/12 speed of symbol clock speed fs and according to the practically identical device of the state diagram programming of Fig. 7.Especially, typically adopt a suitable programming ROM, each decoder 46A-46L is programmed for and produces 4 transfers and measure, each transfer amount kilsyth basalt show two sub-current collections among the symbol level (being the 8-10 place value) that received and each character subset a, b, c, the d flat in poor between the immediate level.Fig. 9 represents a kind of Viterbi decoder that LSI Logic company makes.This decoder can be programmed for the function of carrying out each decoder 46A-46L.This decoder comprises that a transfer measures generator ROM 84, and the symbol that its response is received produces that 4 transfers are measured and transfer measured and imposes on addition, comparison and a selection (ACS) unit 86.ACS unit 86 and path measure that memory 88 is two-way to be connected and memory is recalled in supply.Substantially, the transfer that 86 pairs of generators in ACS unit 84 produce is measured to measure with the former path that is stored in 88 li of memories and is produced new path mutually and measure, and the path that equal state is sent is measured and compared and select to have state that minimum path measures to store.After the transfer that generates some quantity, backtracking memory 90 can work as the position Y that selects a survival path and generation can cause this survival path ₂And Y ₁Estimation.

Should remember to have ignored in the analysis in front the effect of precoder 32a on incoming bit stream.Although will illustrate in greater detail the function of precoder in the back, as long as recognize now because the operation input position X of mould 2 precoders ₂With position Y ₂Different just much of that.The output of each Viterbi decoder 46A-46L includes only a Y among Fig. 8 ₂Estimation, a rather than input position X ₂Correspondingly, in order to recover input position X from each decoder 46A-46L ₁And X ₂Estimation in receiver, adopt complement code mould 2 back encoder 48A-48L.Each back encoder 48A-48L comprises an input position Y ₁With carry-out bit X ₁Between direct path and a feed forward circuit, carry-out bit Y in this feed forward circuit ₂Directly impose on an input of modulo 2 adder 92 and pass through second input that single symbol delay parts 94 are applied to adder 92.The output of adder 92 is by input position X ₂Estimation form.At last, by 96 decoded bits X of multiplexer from back encoder 48A-48L ₁, X ₂Multipath conversion becomes interleave bit stream as shown in Figure 3.

A kind ofly select in the execution mode fully of the present invention, each Viterbi decoder 46A-46L can replace with an amplitude limiter 98 as shown in Figure 10, so that the receiver that provides cost to reduce under the situation of feature of high relatively signal to noise ratio is provided at the signal that is received.Normally this situation of wired transmission.General wired transmission transmits than ground has better signal to noise ratio.Thereby between TCM coding gain, receiver complexity and cost, can trade off.Referring to Figure 10, amplitude limiter 98 is characterised in that three amplitude limit grades (4,0 and+4).Level is decoded as Y for the device 98 that is limited of the receiving symbol under-4 ₂Y ₁=00, level is Y between-4 and 0 ₂Y ₁=01, level 0 and+4 between Y ₂Y ₁=10, level is greater than+4Y ₂Y ₁=11.As before, position Y ₂Y ₁Encoder 48A-48L converts an X to by each back ₂X ₁Estimation.Referring to the mapper 49 of Fig. 5, be by position Z because of symbol level in succession as described above as can be seen again ₂Z ₁Public value represent that amplitude limiter 98 is realized the suitable decoding of institute's receiving symbols.This execution mode of the present invention in fact provides a kind of 4 level to send and receiving system, and it provides the identical bit rate with 8 level TCM systems, but relatively poor because do not carry out TCM coding gain signal-to-noise performance.

Referring to Fig. 8, although comb filter 42 has the required effect that reduces the NTSC common-channel interference, it has also increased to recovering position X again ₁And X ₂And carry out the complexity of optimum MLSE Viterbi decoders for decoding.Especially, best MLSE Viterbi decoder not only must be considered the state of encoder, also must consider the state of the delay unit 76 of comb filter 42.Because exist 4 kinds of coder state and 4 possible modes (that is, having 4 kinds of possibility states of delay unit 76 for each state of encoder 32b) that enter each state, an optimum decoder must be handled a kind of lattice battle array of 16 states.In addition, decoder must consider to enter 4 kinds of transfers of various states, but has only 2 kinds of transfers to enter each coder state.The such decoder of expression in Figure 11, although be complicated in essence, its design is simple and clear relatively.Especially, although the functionality of this decoder similar with the decoder shown in Fig. 9 (thereby adopting identical reference number) comprises that producing the requirement that 15 rather than 4 transfers measure increases its complexity greatly.These transfer amount kilsyth basalts show poor between each 15 possible constellation points (i.e. the linear combination of 8 level symbols provides 15 kinds of possible output levels) of output place of the symbol level that received and comb filter.

The table explanation of Figure 12 a kind of output that is used for reducing from comb filter 42 according to the present invention recovers an X ₁And X ₂Thereby complexity three little its cost techniques of Viterbi decoder 44A-44L.This by the position X of precoding shown in Fig. 4 ₂And become possible simplification is to reach by ignore some state informations from the delay unit 76 of comb filter 42 in the lattice system of battle formations of constructing the basis that forms decoder.Especially, as will being described in more detail below, the of the present invention this viewpoint of a, b, the c that 8 kinds of the delay unit 76 by only considering the identification comb filter may states, the information of d subclass realizes that decoding simplifies.If represent the output of delay unit 26 with reference letter V, then the assembled state of encoder and channel can be expressed as Q ₁(n) Q ₀(n) V ₁V ₀(n), subclass V wherein ₁V ₀(n)=subclass Z ₁Z ₀(n-1).That is to say that the state of delay unit 26 is to represent with the subclass of former symbol.

Now referring to the table among Figure 12, the assembled state Q of encoder and channel when time n is shown in first tabulation ₁Q ₀V ₁V ₀(only utilizing subset information to represent the state of delay unit 76).As shown, exist 8 kinds of possible states 0000,0010,0100,0110,1001,1011,1101 and 1111 (to please note Q under all situations ₁=V ₀).These eight states are to derive to come out the state Q of encoder 32b when the table of Fig. 6 provides random time (n+1) from last two row of the table of Fig. 6 ₁Q ₀Associated subset V with the output V of delay unit 76 ₁V ₀Should note the V of time (n+1) ₁V ₀The carry-out bit Z of subclass and time n ₁Z ₀Identical (seeing the 3rd row in Fig. 6 table).Each assembled state Q of encoder and channel in the table of Figure 12 ₁Q ₀V ₁V ₀Enumerated twice, be input position X ₁Each probable value and enumerate once (the 3rd row of seeing this table).Each encoder/channel status and each input position X when time n is shown in the 4th tabulation of this table ₁The subclass Z of value ₁Z ₀These values are according to concerning Z ₁=X ₁And Z ₀=Q ₀Derivation is come out.In the secondary series of this table and the 5th row, use the V of first row in subclass identifier (a-d) label table of 49 li of mapper of Fig. 5 respectively ₁V ₀Subclass and the Z that forms the 4th row of table ₁Z ₀Subclass.

Again referring to Fig. 8, the output of linear adder device 74 that imposes on the comb filter 42 of each decoder 44A-44L be with the letter U sign and be that the value of using the value of symbol that is received to deduct previous symbol constitutes.This value is pressed Z subclass Z ₁Z ₀With V subclass V ₁V ₀Between difference be illustrated in by subclass identifier (a-d) in the 6th row in the table of Figure 12, thereby for example, the first capable U subclass that should show at time n is (d-d), and fifth line is (c-d), or the like.The probable value of U subclass is derived by deduct each V subclass (a, b, c and d) from each Z subclass (a, b, c and d) in Figure 13.Especially, each possible Z subclass is what to use corresponding to the circle sign of the blacking of the level of each subclass on the top of this figure.For example, subclass a is made up of the level-1 and+7 in 8 level, and subclass b is made up of level-3 and+5, or the like.Similarly, the left margin at this figure identifies each possible V subclass.Internal representation at this figure deducts each V subclass to derive the result of U subclass (U=Z-V) from each Z subclass.For example, seen in the last column in the table of Figure 12 to U subclass (a-a) from a subclass level-1 and+7, deduct a subclass level-1 and+7 and derive, form three level+8,0 ,-8 in the upper left corner that is illustrated in Figure 13 like this.Similarly, the 8th being seen U subclass of row (a-b) deducts b subclass level-3 and+5 and draws in Figure 12 table from a subclass level-1 and+7, and three level+10 shown in providing ,+2 ,-6, and or the like.

Check that 16 U subclass shown in Figure 13 disclose each U subclass and are called in 7 common subset that doubly collect one below belonging to.These 7 cosets are illustrated among Figure 14 and are labeled as coset A (U subclass a-a, b-b, c-c and d-d), B1 (U subclass b-a, c-b and d-c), B2 (U subclass a-d), C1 (U subclass c-a and d-b), C2 (U subclass a-c and b-d), D1 (U subclass d-a) and D2 (U subclass a-b, b-c and c-d).The coset of also having represented each U subclass in the 7th row in the table of Figure 12.Should observe out each coset is made of 3 level in 15 possibility level.

The state Q of the encoder/channel when showing the time (n+1) corresponding to last tabulation in the table of last two Figure 12 that are listed as in the table among Fig. 6 ₁Q ₀V ₁V ₀Can utilize first row of this table and the lattice battle array state transition graph that last row are constructed the combination of the encoder/channel shown in Figure 15 now.Do not consider V in the figure ₀, because it is and Q ₁Redundant.Thereby lattice battle array state transition graph comprises 8 states, and sends two transfers from each state.Each transfer is with input position X ₁And coset A, the B1 relevant with each conversion, B2, C1, C2, D1 and D2 sign.Can utilize the lattice system of battle formations of Figure 15 that the basis of the Viterbi decoder (being used for each decoder 44A-44L) that a kind of complexity obtains simplifying is provided now, this decoder is used for estimating an input position X from the output U of the adder 74 of comb filter 42 ₁A kind of decoder of selecting execution mode fully of the best Viterbi decoder of this formation Figure 11 can be taked the form of the Viterbi decoder shown in Figure 16.Realize that this Viterbi decoder unit can be similar to the parts that adopted in the decoder of Fig. 9 and Figure 11, thereby can comprise that a transfer measures generator 84, ACS unit 86, path and measure memory 88 and one and recall memory 90.Under the situation of the decoder of Figure 16, transfer is measured generator 84 and is programmed for and produces seven transfers and measure, each transfer measure Euclidean distance between the hithermost level of 3 significant levels of each coset among the symbol level of output of the adder 74 of representing

comb filter

42 and 7 coset A, B1, B2, C1, C2, D1 and the D2 square.For example, suppose level U=(6), seven transfers measure should derive as follows: A=2 ²=4; B1=4 ²=16; B2=4 ²=16; C1=2 ²=4; C2=2 ²=4; D1=0 and D2=0.Measure the lattice system of battle formations with Figure 15 according to these transfers, this decoder provides an X ₁Estimation and relevant coset sign, they can obtain from the survival path that this decoder is made is judged.

But, still need to provide input position X ₂Estimation, and this coset information that can provide according to the Viterbi decoder by Figure 16 obtains.By input position X in Fig. 4 ₂Path in this estimation of precoder 32a position X is set ₂Ability become more convenient.Especially, as can be seen as long as precoder 32a is configured to input position X ₂(n)=1, the corresponding carry-out bit Y of this precoder then ₂(n) and previous carry-out bit Y ₂(n-1) difference.That is to say, if Y ₂() ﹠amp n; Y ₂(n-1), X then ₂(n)=1.Equally, if X ₂(n)=0, then corresponding carry-out bit Y ₂(n) will equal the carry-out bit Y of front ₂(n-1).That is to say, if Y ₂(n)=Y ₂(n-1), X then ₂(n)=0.Equally, by the mapper 49 of reference Fig. 5, can observe out and work as Z ₂(be Y ₂)=1 o'clock provides the positive level symbol, and works as Z ₂=Y ₂The negative level symbol was provided in=0 o'clock.

Expression utilizes above-mentioned characteristic estimating position X among Figure 17 ₂The symbol level U of the output of the adder 74 by (delay that is chosen as with the Viterbi decoder 44A-44L is complementary) comb filter 42 that postpones 100 is applied on the input of a plurality of (promptly 7) amplitude limiter 102.The coset id signal of output place of Viterbi decoder 44A-44L is applied on second input of amplitude limiter 102.Whether amplitude limiter 102 is by determining from the U symbol level of comb filter 42 near by the outer level (for example level of coset A+8 or-8) of coset A, B1, B2, C1, C2, D1 or the D2 of each Viterbi decoder 44A-44L sign or whether derive a position X near the intermediate level (for example 0 level of coset A) of the level of the coset that is identified ₂Estimation, near the next X of situation of outside level ₂Be interpreted as 1 and near the next X of situation of intermediate level ₂Be decoded into 0.Above-mentioned situation is based on this fact, promptly only works as the Y in succession of output place of precoder 32a ₂The position is with value Y ₂And Y (n)=1 ₂(n-1)=0 just produce the positive outside level (for example coset A+8) of each coset when the feature, and and if only if Y in succession ₂The position has value Y ₂And Y (n)=0 ₂(n-1)=1 o'clock just produce the negative outer level (for example-8 of coset A) of each coset, and Y that only ought be in succession ₂The position has value Y ₂And Y (n)=1 ₂Or Y (n-1)=1 ₂And Y (n)=0 ₂(n-1)=0 o'clock just produce the intermediate level (for example 0 of coset A) of each coset.X under the first two kind situation ₂(n)=1 (because of Y ₂() ﹠amp n; Y ₂(n-1)) X under and in the end a kind of situation ₂(n)=0 (because of Y ₂(n)=Y ₂(n-1)).

At last, should be appreciated that when adopting optimum MLSE Viterbi decoder to handle the output of comb filter 42 as shown in Figure 11, at input position X ₂Path in comprise that a precoder need estimate a position X ₂Path in introduce encoder after the benefit.Under the situation of the circuit of Figure 17 because the position X that estimates ₂Be directly produce then do not need to mend the back encoder.

As the front is illustrated, following aspect of the present invention has the data segment of varying number and each data segment and has in the structure of symbol of varying number although can be applied to each frame equally, the data that data source 24 provides are preferably arranged by Frame in succession, and every frame is made up of the data segment of a plurality of 684 symbols.Also further require in first data segment of each frame, to introduce the frame synchronizing signal that can comprise one or more pseudo random sequences, and require on preceding four character positions of each data segment, to introduce a data segment sync signal.Again referring to Fig. 4, frame synchronizing signal and segment sync signal are to go in reasonable time is inserted into data flow on the output of multiplexer 62 by frame and data segment sync generator 66.In these interims, select B input and the multiplexer 53 of convolution coder and 55 the B input of the multiplexer 46 of precoder 32a.And last 12 symbols of last data segment of each frame are read into 64 li of memories and at last 12 mark spaces of the output place duplicated frame sync section of multiplexer 62.As will explaining in more detail in the back, above-mentioned measure is for guarantee to be effective handling together from the symbol of identical son section from the symbol of each height section A-L (see figure 3) only in receiver.

More specifically, during the section sync interval, pass through generator 66 and multiplexer 62 4 predetermined synchronizing symbol S ₀, S ₁, S ₂And S ₃Be inserted in the data flow, and temporarily be suspended in the input data of synchronization from data flow 24.And, because the output of

delay unit

48,54 and 56 is fed back to their inputs separately, and then the feature of each delay unit will as shown in figure 18 after between the section synchronization zone, and wherein the state of each delay unit is by from the sign convention of son section E.Expression segment sync signal S in Figure 19 ₀, S ₁, S ₂And S ₃Near mixed signal, this data segment comprises appear at the time synchronously and respectively (n-1) and (n+1) previous section and a back section that appears at time n in Figure 19.Relevant with this figure, should be noted that, although in the data flow of mixing, inserted synchronizing symbol, the integrality of son section be guaranteed (from apart 12 mark spaces of all symbols of identical son section).

Execution mode for a kind of modification of the comb filter 42 of operating Figure 20 presentation graphs 8 according to synchronous inserted mode of the present invention.This modification comprises a multiplexer 110 is set, it have direct this comb filter of reception output the A input and receive the B input of the output of adder 112.An input of adder 112 directly directly is connected with the output of this comb filter, and second output of importing by 12 symbol delay parts 114 and comb filter of adder 112 is connected.During 13-16 between the sign field (promptly postponing between the synchronization zone of 12 symbol clocks), select the B input of multiplexer 110, and selecting the A input At All Other Times.

The output of comb filter 42 during between the synchronization zone comprises when when operation:

S ₀-A(n-1)

S ₁-B(n-1)

S ₂-C(n-1)

S ₃-D(n-1)

On behalf of significant data and decoded device, the information that these A inputs through multiplexer 110 impose on decoder ignore.But, the next symbol (i.e. symbol that comes comfortable son section E) in the data segment that occurs since time n, from the symbol quilt of identical son section suitably combing to together and the A input of process multiplexor 110 offer decoder.Select the B input of multiplexer 110 during preceding 4 symbols of the data segment that occurs in the time (n+1).Comb filter 42 is output as during this:

A(n+1)-S ₀

B(n+1)-S ₁

C(n+1)-S ₂

D(n+1)-S ₃

These values are combined so that 4 output A (n+1)-A (n-1), B (n+1)-B (n-1), C (n+1)-C (n-1) and D (n+1)-D (n-1) in succession to be provided in 4 outputs of comb filter during sync interval that adder 112 neutralizations are stored in 114 li of delays.Can notice each output representative required from the data symbol after the combing of identical son section.Then, reselect the A input and the conventional processing of continuation of multiplexer 110.

Figure 21 represents to be used for the execution mode of a kind of back encoder of the back encoder 48A-48L of for example Fig. 8 in the receiver of the present invention and Figure 10, and this back encoder is modified as according to synchronous inserted mode of the present invention and carries out work.This amended back encoder comprises a mould adder 120 and feedforward delayer 122, it also comprises a multiplexer 124, this multiplexer be used for the output of delayer 122 sync interval coupling get back to this delayer input and other the time input signal of this back encoder is applied to an input of adder 120 through delay 122.As a result, each amended back encoder 48A-48L will finish the symbol of related with it on request son section will be stored into 122 li of its pairing delays after sync interval, and the output of encoder is uncared-for after sync interval.

Carry out frame synchronization insertion and processing according to top at the illustrated mode about the same of data segment sync.More specifically, as shown in Figure 22, in frame synchronization interim, promptly on first data segment of each frame, generator 66 and multiplexer 62 initial manipulation are used for frame synchronization symbols V ₀-V ₆₇₁Be inserted into frame sync segment S ₀Preceding 672 character positions on.Last 12 symbols of frame sync segment are inserted in the data flow by RAM64 and constitute last data segment S of former frame (this frame is former to be written among the RAM64) ₃₁₂Last 12 symbols.Equally, because the B input of frame synchronization

interim selection multiplexer

46,53 and 55, at next data segment S ₁The

end delay unit

48,54 and 56 of section between the synchronization zone will present the situation shown in Figure 18, thereby illustrated data segment also as shown in Figure 22 above will forming.

The circuit of Figure 20 and Figure 21 is by top illustrated such work to guarantee only to obtain processing together with the symbol of identical son section from the symbol of each sub-section A-L.The output of these two circuit during the frame sync segment S0 do not represent significant data and thereby processing in the back in be left in the basket.

As mentioned in front, system of the present invention can adopt different mapping conformations to provide, and for example, the bit rate of raising perhaps can adopt the different modulating modes such as QAM.Figure 23 illustrates the application of the present invention in a kind of system, 3 of each symbologies rather than 2 described above in this system.Provide 3 input data bit X by character rate as shown in FIG. ₁, X ₂And X ₃, position X ₃And X ₂Comprised mould 4 combiners 44 " mould 4 top encoder 32a ' convert a Y to ₂And Y ₂So that as Z ₂And Z ₂Be applied to the symbol mapper 49 of 16 level ' on.Data bit X is down as position Z ₁Be applied to mapper 49 ' the 3rd input and convolution coder 32b on, convolution coder 32b produce be applied to mapper 49 ' four-input terminal on position Z ₀The same in Shuo Ming the execution mode in front, position Z ₁Z ₀Sign subclass a, b, c and d, each subclass is made up of 4 kinds of symbol level.Equally, the difference of each symbol amplitude is 8 amplitude units in each subclass, and symbol level in succession (for example-15 ,-13) is by position Z ₃Z ₂Z ₁Common condition select.Thereby the signal that circuit produced of Figure 23 can utilize technology decoding described above.In this example, the number of states that had of optimum MLSE decoder (promptly do not consider precoder and be used for decoders for decoding is carried out in the output of comb filter) should be 8 times of coder state.Comprise mould 4 precoders and allow this decoder on a kind of lattice battle array, to work, thereby the state of this decoder is two times of encoder and still can be under the situation that does not cause error propagation bits of coded be not deciphered.

Figure 24 A and 24B represent the application of the present invention to the QAM modulator.As shown in Figure 24 A, be provided with 3 input position X ₁, X ₂And X ₂, position X ₃And X ₂" and 32a precoding is to provide carry-out bit Z independently respectively by mould 2 precoder 32a ₃And Z ₂, position X ₁Offer convolution coder 32b to produce carry-out bit Z ₁And Z ₀Carry-out bit Z ₃Z ₂Z ₁Z ₀Be applied to symbol mapper 49 " with generation be applied to QAM modulator 36 ' belong among the subclass a-d 16 quadrature related symbol (seeing Figure 24 B) of one.According to top described, still can observe the Z that puts in place ₁Z ₀Identify each character subset a-d.The optimum decoding that does not have a precoder will require the status number of decoder be encoder status number 2 ³=8 times.By precoder, decoder only has the state of diploidy number amount.

The employed receiver of the system of Figure 23 and Figure 24 can take to summarize among Fig. 8 the form of expression.Under the situation of the system of Figure 23, as shown in Figure 25 A comprising mould 4 combiners 92 ' mould 4 back encoder 48A ' will replace each mould 2 encoder 48A afterwards, and under the situation of the system of Figure 24 A and 24B, " and 48A will replace each mould 2 back encoder 48A to a pair of mould 2 back encoder 48A as shown in Figure 25 B.

Can recognize, be tangible for those skilled in the art under the prerequisite of the spirit and scope of the invention the various execution modes that illustrated of the present invention being carried out many changes.The present invention only is subjected to the qualification of the regulation in claims.

Claims

1. data receiver, it comprises that the device of the data-signal that is used for producing reception, the data-signal of reception comprise a plurality of symbols that separate regularly, each symbol by an encoder that is comprising a multimode convolution coder by to 2 or more a plurality of data bit X ₁, X ₂..., X _nEncode and be expressed as 3 positions or more a plurality of Z ₀, Z ₁, Z ₂..., Z _nMultimode linear filter is used to reduce to become the common-channel interference of feature of the data-signal of described reception; And code translator comprises a Viterbi decoder, and the latter responds the data-signal data estimator position X of mensuration behind the linear filtering of the Maximum likelihood sequence of at least a portion in the state of a kind of combination and described linear filter of state of described convolution coder conversion between representing ₁, X ₂..., X _n

2. the receiver of claim 1, wherein said linear filter comprises that the data-signal of a M state linear filter and described reception comprises the M group interleave symbol of coding respectively, and described receiver comprises M described code translator and comprises and be used for every group code of described M group code is applied to device on of described M code translator of correspondence.

3. claim 1 or 2 receiver comprise one the 2nd Viterbi decoder device, and the mensuration of Maximum likelihood sequence that is used for responding the conversion between the state of described convolution coder is from the data-signal data estimator position X of described reception ₁, X ₂..., X _n

4. the receiver of claim 1, wherein said 3 or more a plurality of position Z ₀, Z ₁, Z ₂..., Z _nComprise and use coded data bit X ₁, X ₂The position Z that produces ₀, Z ₁, Z ₂, and wherein said code translator comprises the data-signal data estimator position X of mensuration behind the linear filtering of the Maximum likelihood sequence of the conversion between the subclass of state of a kind of combination of the state that is used for responding described convolution coder and described linear filter ₁, X ₂Device.

5. the receiver of claim 4, the state of wherein said linear filter is that available 3-place value is represented, and wherein said subclass comprises a position in the position of described 3-place value.

6. claim 4 or 5 receiver, wherein said code translator comprises a Viterbi decoder, is used for data estimator position X ₁And be used for discerning one by a plurality of cosets of the centrifugal pump of the expection output of the predetermined quantity of representing described linear filter.

7. the receiver of claim 6 comprises that signal and the coset of the centrifugal pump of response described identification of response behind the described linear filtering is used for data estimator position X ₂Device.

8. the receiver of claim 7, the output of wherein said linear filter is to be represented by 15 different centrifugal pumps, and each in wherein said a plurality of coset comprises 3 a kind of different combination among described 15 different centrifugal pumps, the described data estimator position X that is used for ₂Device comprise the output that is used for determining described linear filter signal level whether near the median of 3 centrifugal pumps of the coset that identifies or one device in the external value.

9. data receiver, it comprises the device of the data-signal that is used to produce reception, the data-signal of reception comprises a plurality of symbols that separate regularly, the Z that each described symbolic representation is 3 ₀, Z ₁, Z ₂, these three is to utilize a multimode convolution coder the first data bit X ₁Be encoded into a Z ₀, Z ₁With utilize mould 2 precoders the second data bit X ₂Be encoded into Z ₂And form, its meta Z ₀, Z ₁Each subclass (a-d) that indicates described symbol, each described subclass (a-d) comprises two equally spaced values of symbol, and position Z ₁, Z ₂Sign respectively comprises every pair of described symbol of two adjacent-symbol values; A multimode linear filter is used to reduce to define the NTSC common-channel interference of described reception data-signal; First decoder device comprises that a Virterbi decoder responds the data-signal data estimator position X of mensuration behind the described linear filtering of the Maximum likelihood sequence of the conversion between the subclass of a kind of combination of state of described convolution coder and described linear filter ₁, X ₂Second decoder device is used for from described reception data-signal data estimator position X ₁, X ₂And choice device is used to the data bit X that described estimation is provided ₁, X ₂Select described first decoder device or described second decoder device.

10. the receiver of claim 9, wherein said Viterbi decoder comprises that one is used to produce the transfer that a plurality of transfers measure and measures generator, distance in the coset of the output of each transfer amount kilsyth basalt timberline filter and each 3 values between immediate that value, each described coset represent that the straight line between the value of symbol of two described subclass is poor.

11. comprising, the receiver of claim 10, wherein said Viterbi decoder be used for data estimator position X ₁With the device that is used to discern a relevant coset.

12. the receiver of claim 11 comprises that signal and the coset of response described identification of response behind the described linear filtering is used for data estimator position X ₂Device.

13. the receiver of claim 12, the wherein said data estimator position X that is used for ₂Device comprise the output that is used for determining described linear filter signal level whether near the median of 3 values of coset of described identification or one device in the external value.

14. the receiver in the claim 9 to 13 in arbitrary claim, the state of wherein said linear filter is with 3 place value V ₀, V ₁, V ₂Expression and wherein said subclass comprise the position V of described 3 place values ₁

15. the receiver of the arbitrary claim in the claim 9 to 13, wherein said first and second decoder devices comprise that responds the Viterbi decoder that described choice device is born the structure of carrying out the described first code translator function or born the structure of the function of carrying out described second decoder device.

16. one kind is used for Viterbi decoder that the signal that is produced by a polymorphic convolution coder and receive is deciphered on a polymorphic channel, described Viterbi decoder comprises that one is used to respond described received signal and produces the transfer that a plurality of transfers measure and measure generator, and comprises and be used to respond the device that the Maximum likelihood sequence of the conversion between the subclass of state of a kind of combination of the state of measuring described convolution coder and described channel is measured in described transfer.

17. the decoder of claim 16, wherein said transfer is measured generator and is comprised and be used to produce the device that a plurality of transfers are measured, and wherein the distance between the immediate value in the coset of the value of the described received signal of representative and corresponding N value is measured in each described transfer.

18. the decoder of claim 17, wherein said determinator comprise first data component that is used for the described received signal of direct estimation and the device that is used to discern a relevant coset of described coset.

19. the decoder of claim 18 comprises that the coset of described received signal of response and described identification is used to estimate the device of second data component wherein.

20. the decoder of claim 19, wherein each described coset comprises 3 data values, and the wherein said device that is used for estimating described second data component comprises that the level that is used for determining described received signal is whether near the median of 3 values of the coset of described identification or one device in the external value.