KR20000045145A - Vsb demodulator of digital television receiver - Google Patents

Abstract

PURPOSE: A VSB demodulator of a digital television receiver is provided to improve a decoding capacity by varying Viterbi decoding methods according to a channel status. CONSTITUTION: A VSB demodulator of a digital television receiver comprises an equalizer for detecting an error value corresponding to a channel status, a channel status extractor for determining a channel status, and a Viterbi decoder for decoding an output of the equalizer. The channel status extractor comprises a reference value storage portion(302), a subtracter(304), a code determinater(306), a multiplier(308), and a multiplexer(310). The storage portion stores a predetermined reference value. The subtracter subtracts the error value of the equalizer from the reference value. The code determinater determines an output code of the subtracter. The multiplier multiplies the error value of the equalizer by a predetermined weight. The multiplexer outputs an output of the multiplier or a predetermined value according to an output of the code determinater.

Description

A VSB demodulator of a digital television receiver

The present invention relates to a residual side wave method (VSB) demodulator having a Viterbi decoder which improves decoding capability by determining an input bit as an erasure in a digital television receiver or calculating a branch matrix by reflecting an equalizer error value. It is about.

In general, successive information signals are converted into discrete forms by encoding, which is represented by a binary bit stream. The encoded binary bit stream is properly filtered and then modulated by VSB modulation and transmitted over the air. In this case, Reed Solomon encoding and convolutional encoding are used as encoding techniques for correcting errors in data during transmission.

The Viterbi algorithm, which receives and decodes a convolutional coded bit stream, uses trellis diagrams to determine the path lengths for these two paths when two paths with different paths meet at each point in time. Path metrics are compared to select and maintain only one path with a low probability of error. At this time, the selected path is a survival path, and the determination of the survival path is performed at every time point. The Viterbi algorithm is an algorithm that performs maximum-likelihood decoding, which is a kind of dynamic programming, and is widely used in communication fields such as digital transmission, magnetic recording, and voice recognition.

2 is an example of a VSB demodulator in which a conventional Viterbi decoder is used. The VSB demodulator 106 as shown in FIG. 2 is used in a digital television receiver described later, and includes an IF demodulator 202, an equalizer 204, a Viterbi decoder 206, a deinterleaver 208, an RS decoder 210, It consists of a derandomizer 212. 2, the IF demodulator 202 receives an IF signal and outputs a digital bit stream, and the equalizer 204 adaptively adjusts the filter coefficient according to the state of the transmission channel and then filters the channel accordingly. Compensate for traits The Viterbi decoder 206 decodes according to the Viterbi algorithm using the soft decision result of the equalizer 204, and the deinterleaver 208 encodes a process to compensate for burst errors. Rearranges the interleaved in the original bit stream. The RS decoder 210 performs Reed-Solomon decoding to correct errors in units of blocks, and the derandomizer 212 rearranges error-decoded data and reconstructs them into an MPEG transport stream for output.

However, the conventional VSB demodulator decodes the data received by the Viterbi decoder regardless of the state of the channel, and thus, when the state of the channel is poor, the decoding performance is deteriorated. That is, if the state of the channel is very poor, even if the channel characteristics are compensated in the equalizer, there is a channel error, which negatively affects the decoding.

Accordingly, the present invention has been made to solve the above-mentioned problems. Viterbi improves the decoding capability by determining the input bit as an eraser or reflecting the equalizer error value in the digital terrestrial television receiver according to the channel state. The purpose is to provide a decoder.

In order to achieve the above object, the apparatus of the present invention includes an equalizer for receiving a broadcast signal of a predetermined channel and detecting an equalizer error value corresponding to a channel state, and a predetermined equalizer error value input from the equalizer. A channel state extractor for determining a channel state in comparison with a reference value, and processing the data inputted from the equalizer according to a channel state signal input from the channel state extractor with an eraser to decode or equalize the equalizer error value. CLAIMS 1. A VSB demodulator of a digital television receiver comprising a Viterbi decoder that decodes an output of a device, the channel state extractor comprising: a reference value storage unit for storing a predetermined reference value; A subtractor for subtracting the error value input from the equalizer from the reference value; A code determiner for determining an output code of the subtractor; A multiplier that multiplies the equalizer error value by a predetermined weight value; And a multiplexer for outputting a multiplier output or a predetermined value according to the output of the code determiner.

1 is a block diagram showing the configuration of a digital television to which the present invention is applied;

2 is a block diagram showing a conventional VSB demodulator shown in FIG.

3 is a block diagram showing a VSB demodulator according to the present invention;

4 is a detailed configuration diagram of the channel state extractor shown in FIG. 3;

5 is a block diagram showing the configuration of a Viterbi decoder according to the present invention.

* Explanation of symbols for main parts of the drawings

106 ': VSB demodulator 202: IF demodulator

204 ': equalizer 206': Viterbi decoder

208: deinterleaver 210: RS decoder

212: derandomizer 300: channel state extractor

302: reference storage unit 304: subtractor

306: code determiner 308: multiplier

310: multiplexer 502: branch matrix generator

504: addition comparison selection unit 506: survival memory unit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic diagram showing a digital television receiver, showing a terrestrial broadcast reception structure of a VSB system. Referring to FIG. 1, a digital television receiver includes an RF tuner 102, an analog-to-digital converter (ADC) 104, a VSB demodulator 106, an MPEG transport stream demux (MPEG TS DeMUX) 108, and an MPEG2 decoder 110. ), A video memory 112, an AC-3 audio decoder 114, an audio memory 116, a microprocessor 118, and a system memory 120. In FIG. 1, the tuner 102 receives a radio broadcast signal of a channel selected according to a tuning signal, outputs an IF signal, and the ADC 104 converts an analog signal into a digital signal. The VSB demodulator 106 receives digital data and outputs an MPEG transport stream, and the MPEG TS Demux 108 decomposes the transport stream in units of 188 bytes and divides the system data, video data, and audio data into outputs. do. At this time, the system data includes program specific information (PSI) for the currently received programs in four tables (PAT, PMT, NIT, CAT). The MPEG decoder 110 processes MPEG decoding to reproduce a video signal YCrCb, and the AC-3 audio decoder 114 receives an audio packet to reproduce a PWM audio signal. In this case, the video memory 112 and the audio memory 116 store corresponding data in each decoding process.

The overall operation of the receiver is controlled by the microprocessor 118, and the microprocessor 118 executes a program included in the system memory 120 and stores various data in the system memory 120. Although not shown in detail in the drawing, video data is converted into an RGB signal by the video processor and displayed on the CRT, and audio data is amplified by the audio processor and output through a speaker, and the microprocessor 118 is connected to a microcom serial communication channel. Can be transferred to the user control.

3 is a block diagram illustrating a VSB demodulator according to the present invention. The VSB demodulator 106 'used in the digital television receiver configured as shown in FIG. 2 includes an IF demodulator 202, an equalizer 204', a Viterbi decoder 206 ', a deinterleaver 208, and an RS decoder 210. , A derandomizer 212 and a channel state extractor 300.

The IF demodulator 202 demodulates the IF signal to output a baseband bit stream, and the equalizer 204 'detects an equalizer error value corresponding to the state of the channel through which the broadcast signal is transmitted, according to a predetermined algorithm. Compensate for traits

Here, the equalizer 204 'is configured to obtain a transfer function of the transfer channel and to configure the circuit to have the inverse function of the transfer function. The channel characteristics are not always constant, but change frequently depending on time and place. Accordingly the tap coefficient is adaptively changed. As described above, the equalizer calculates an error value in order to detect a state of a channel. The criteria for calculating the error value are classified into mean squared error (MSE) and least squares (LS). The filter structure is divided into a transverse line filter and a lattice structure filter, and is divided into an equalizer using a training signal and a blind equalizer according to whether the training signal is used. Equalizers that use the Mean Squared Error (MSE) criterion include a Least Mean Square (LMS) equalizer, a decision feedback LMS (DF-LMS) equalizer, and a GAL (GAL) that applies the LMS algorithm to a lattice filter. Gradient Adaptive Lattice).

As shown in FIG. 4, the channel state extractor 300 includes a reference value storage unit 302, a subtractor 304, a code determination unit 306, a multiplier 308, and a multiplexer 310. The equalizer error value e inputted from 204 'is compared with a predetermined reference value to determine the channel state. For example, if the equalizer error value e outputted by the equalizer 204 'changes from 0 to 1 (0≤e≤1) according to the state of the channel, and empirically the error value e is 0.7 or more Assume that the received bits are then processed by erasure. Then, the reference value 0.7 is stored in the reference value storage unit 302, and the subtractor 304 subtracts the error value input from the equalizer 204 'from the reference value. The code determiner 306 determines the output of the subtractor 304 and outputs 1 if it is positive and 0 if it is negative. The multiplier 308 multiplies the equalizer error value by a predetermined weight and outputs the result to the multiplexer 310. The multiplexer 310 outputs the multiplier 308 according to the output of the code determiner 306, or " Select 0 "to print. That is, if the equalizer error value is greater than the reference value and the sign is negative, the multiplexer 310 selects and outputs "0", and if the equalizer error value is less than or equal to the reference value, the multiplexer 310 determines the multiplier. Select output We and output it as a channel status signal.

As shown in FIG. 5, the Viterbi decoder 206 ′ is composed of a branch matrix generator 502, an add comparison selector 504, and a survival memory unit 506, which are input from the channel state extractor 300. The data input from the equalizer 204 'is decoded according to the Viterbi algorithm in consideration of the channel state signal. In an embodiment of the present invention, the Viterbi decoder includes a trellis decoder.

Referring to FIG. 5, the branch matrix generation unit 502 (BMU: Branch Metric Unit) receives a received encoded data string, compares all possible codewords, and calculates and outputs a branch metric. The add compare selection unit (ACSU) adds a branch matrix from the branch matrix generation unit 502 and updates the branch matrix by adding the branch matrix to the previous path metric. Comparing two path matrices, a path matrix having a high probability is selected, and a decision vector is output. The survivor memory unit 506 (SMU: Survivor Memory Unit) stores the decision vector output from the addition comparison selector 504 in the memory, and finds the original information sequence using the decision vector. That is, the branch matrix generator 502 receives the received digital signal, calculates a branch matrix, and outputs the branch matrix to the add comparison selector 504. The add comparison selector 504 outputs the branch matrix for each decoding cycle. The path matrix is updated to output an N-bit decision vector to the surviving memory unit 506. The surviving memory unit 506 stores the determination vector input from the addition comparison selecting unit 504 in the memory, and restores the original vector sequence using the determination vector stored in the memory.

At this time, the addition comparison selector 504 receives the channel state information from the channel state extractor 300 and selects a path according to the channel state as shown in Table 1 below.

Equalizer error value Reference value Code judge Channel status signal Viterbi input 0.3 0.7 One We Equalizer output 0.7 One We Equalizer output 0.8 0 0 Eraser 0.9 0 0 Eraser

When the reference value is 0.7 as shown in Table 1, if the equalizer error value is 0.7 or less and the channel state is relatively good, the code determiner 306 outputs "1" and thus the multiplexer 310 outputs the channel state. As a signal, a value We obtained by multiplying an error value by a weight is output. At this time, the Viterbi decoder 206 'calculates a branch matrix as shown in Equation 1 to select a path with less error.

BM _{n =} (BM) _n-1 + PM * We

Referring to Equation 1, the Viterbi decoder 206 'adds a value obtained by multiplying the path matrix PM by the channel state signal We to the previous branch matrix (BM) _n-1 to add a new matrix BM _n. ) Is calculated. As such, the channel state signal We is reflected in the calculation of the branch matrix and thus influences the path selection. Therefore, an optimal path can be obtained in consideration of the channel state.

On the other hand, if the equalizer error value exceeds 0.7, the code determiner 306 outputs "0" and thus the multiplexer 310 provides "0" as the channel status signal. Accordingly, the Viterbi decoder 206 'determines the corresponding bits input from the equalizer 204' by erasing the eraser. As described above, the Viterbi decoder 206 'processes the received bit as an eraser when the channel state is poor according to the channel state signal input from the channel state extractor 300, and weights the error value when the channel state is good. Decoding performance can be improved by selecting the path by applying the channel state signal multiplied by to the new branch calculation.

As described above, according to the present invention, after determining the state of the channel by using the error value of the equalizer, if the state of the channel is poor, then the bits inputted by the Viterbi decoder are processed by an erasure, and the channel is decoded. If the condition is good, the decoding performance can be improved by decoding the channel state by multiplying the error value by the weight and multiplying the path matrix to obtain a new branch matrix.

Claims (2)

An equalizer 204 'that receives a broadcast signal of a predetermined channel and detects an equalizer error value corresponding to the channel state, and compares the equalizer error value input from the equalizer with a predetermined reference value to determine a channel state The channel state extractor 300 and the channel state signal inputted from the channel state extractor process the data inputted from the equalizer with an eraser to decode or decode the output of the equalizer by reflecting the equalizer error value. In a VSB demodulator of a digital television receiver comprising a Viterbi decoder 206 ', The channel state extractor, A reference value storage unit 302 for storing a predetermined reference value; A subtractor 304 for subtracting an error value input from the equalizer from the reference value; A code determiner (306) for determining an output code of the subtractor; A multiplier (308) that multiplies the equalizer error value by a predetermined weight (W); And And a multiplexer (310) for outputting an output of a multiplier or a predetermined value in accordance with the output of the code determiner. The VSB demodulator of claim 1, wherein the multiplexer selects and outputs "0" when the error value is larger than a reference value according to the output of the code determiner.