CN1294743C

CN1294743C - Receiver of 8MHz channel digital television system

Info

Publication number: CN1294743C
Application number: CNB200410043405XA
Authority: CN
Inventors: M·菲莫夫; R·W·奇塔; W·E·布雷特尔
Original assignee: Zenith Electronics LLC
Current assignee: Zenith Electronics LLC
Priority date: 1999-05-27
Filing date: 2000-05-22
Publication date: 2007-01-10
Anticipated expiration: 2020-05-22
Also published as: HK1044440A1; CN1351797A; CN1538742A; WO2000074375A1; HK1044440B; CN1199440C

Abstract

A transmitter transmits, and a receiver receives, a data frame is transmitted into an 8 MHZ channel. The data frame contains a plurality of data segments, where each of the data segments contain DS symbols. The DS symbols include data symbols, priming symbols, and segment synchronization symbols. The transmitter trellis encodes the data symbols, priming symbols, and segment synchronization symbols. The receiver trellis decodes the data symbols, priming symbols, and segment synchronization symbols. The data frame also contains a mode control ID which the receiver uses in trellis decoding the data symbols, priming symbols, and segment synchronization symbols.

Description

The receiver of 8MHz channel digital television system

The application is that the application number submitted on May 22nd, 2000 is dividing an application of 00808028.3 patent application.

Related application

Following common unexamined patent application has disclosed the theme of asking for protection at this: (1) denomination of invention is the US6 of " Digital Television lattice structure (Trellis) code modulation system with convolution mode coded data and sync symbols ", 687,310; (2) denomination of invention is the US6 of " on the occasion of Viterbi (Viterbi) decoder of the digital television signal of comb shape filtering ", 529,558; (3) denomination of invention is the US6 of " making the mode of the digital signal that multidata structure picture experience is disturbed discern ", 493,402; (4) denomination of invention is the US6 of " digital television system that reduces co-channel interference in the 8MHz channel ", 246,431; And denomination of invention is the US6 of " 8MHz channel data frame ", 608,870.

The present invention and prior art background

The present invention relates to digital sending/receiving system on the whole, specifically, relating to a kind of data frame structure and circuit arrangement are chosen to be is convenient to such as conversion between code element and byte, interweaves and the system for digital data transmission/reception of deinterleaving and this class running of forward error correction.This system also is convenient to utilize and signal noise ratio (S/N ratio) the relevant data rate of enhanced system capacity with transmission environment.

The invention still further relates to the utilization of the modulation of plaid matching structured coding in the sending/receiving system (TCM), specifically, relate to high definition TV (HDTV) use in to the utilization of TCM.

United States Patent (USP) U.S.Pat.No.5,087,975 and U.S.Pat.No.5,600,677 have disclosed a kind of vestigial sideband (VSB) system that sends TV signal on a standard 6MHz television channel by continuous N level symbol form.This TV signal for example can comprise one or two compression sideband HDTV signal or several low-resolution signal through overcompression.The progression M that characterizes code element can be with environmental change, but chip rate is preferably fixing, for example is 10.76 million code element/seconds.The used code element progression in any specific occasion is the function that characterizes the S/N ratio of transmission medium substantially.For instance, the occasion that S/N is lower can be utilized less code element progression.It is believed that the ability of utilizing lattice structure coding (8VSBT), 4 and 2 to adapt to 16,8,8 symbol level can provide enough flexibilities to satisfy the situation of most systems.Will be understood that lower M value can compare performance for cost provides improved S/N by the transmission bit rate that reduces.For instance, consider the chip rate of 10.76 million code element/seconds, 2 grades of VSB signals (1 of each code element) provide the transmission bit rate of 10.76 megabit per seconds, 4 grades of VSB signals (2 of each code elements) provide the transmission bit rate of 21.52 megabit per seconds, the rest may be inferred, and 16 grades of VSB signals provide the transmission bit rate of about 43.04 megabit per seconds.

Usually know that the S/N of cable television appliances reduces than the raising of performance with signal (channel) frequency.The above-mentioned attribute of M level VSB transmitting system promptly reduces with M and improved S/N ratio, is used in a certain respect in the upper frequency channel of CATV (cable TV) discharge device S/N being compensated than degradation in the present invention.That is to say,, in a CATV system, carry out VSB and send, wherein adopt bigger M value to send the lower frequency channel according to this one side of the present invention.Though the bit rate of upper frequency channel reduces thus, the received signal that its S/N ratio of regenerating can be comparable with the lower frequency channel.

Usually know also that the S/N of aerial digital signal broadcasting can be improved by TCM (lattice structure coded modulation) than performance.United States Patent (USP) U.S.Pat.No.5,600,677 and U.S.Pat.No.5,583,889 have illustrated a kind of VSB signal of 8 grades of TCM coding.Viterbi in the receiver (Viterbi) decoder is using in the middle of (U.S.Pat.No.5 discloses in 087,975) comb filter close collaboration with one.This comb filter has suppressed the co-channel interference that existing NTSC signal is caused.

And, according to other aspects of the present invention, system effectiveness, especially with such as the relevant system effectiveness of this class of conversion between data interlacing and deinterleaving, code element and byte, forward error correction and Veterbi decoding running, can obtain bigger reinforcement by the data frame structure that above-mentioned running is convenient in selection in the variable M level VSB symbol of signal transmitted and TCM code parameters constraints.United States Patent (USP) U.S.Pat.No.5,677,911 have disclosed a kind of data frame structure of 6MHz channel.

The application described above and other common unexamined applications adapt to the VSB system of previous announcement and can send on (adopting as China and Europe) standard 8MHz television channel, and have the existing PAL (phase-aoternation line system) of the inhibition this ability of interference that signal caused.In the native system, chip rate is 14.14 million code element/seconds preferably, so that all bit rate improves with being directly proportional.

The lattice structure coded modulation is the well-known technology that improves digital sending/receiving system performance.For instance, can realize the raising of signal noise (S/N) in given power stage than performance; As an alternative, can reduce the transmitted power that realizes that given S/N is more required than performance.In fact, TCM comprises and utilizes the multimode convolution coder that every k input data bit of the data bit sequence imported is transformed to k+n carry-out bit, thereby is called the convolution coder of ratio k/(k+n).The discrete code element that the carry-out bit of this convolution coder then is mapped as through the data transmission carrier wave of ovennodulation (has numerical value 2 ^(k+n)).This code element for example can comprise 2 ^(k+n)Individual phase value or range value.Can encode to the data bit of being imported by sequential system by dependent status, between admissible sending order, realize the minimum Euclidean space distance of raising, cause error probability to reduce when in receiver, adopting PRML decoder (for example Viterbi decoder).

Fig. 1 illustrates top described this system usually.Every k of input traffic position is transformed to (k+n) individual carry-out bit by the convolution coder 10 of the dependent status order of ratio k/(k+n).Then be mapped as one by mapper 12 has 2 to the individual carry-out bit of each group (k+n) ^(k+n)Wherein corresponding one code element of individual level.This code element is sent on a selected channel by transmitter 14.Receiver comprises that the signal transformation that a tuner 16 is used for receiving on the selected channel is an intermediate-freuqncy signal, is separated by a demodulator 18 and transfers to provide a base-band analog signal.This analog signal is taken a sample by suitable method by A-D converter (A/D) 20 and is reduced the code element that is sent, and then delivers to a Viterbi decoder 22 and comes an also original initial k data bit.

United States Patent (USP) U.S.Pat.No.5,087,975 has also disclosed and utilizes the feedforward that has a receiver comb filter of subtraction element and 12 code element clock gaps are carried out to postpone to reduce the co-channel interference of NTSC in the receiver.For the ease of the running of this receiver comb filter, this source data is encoded in advance by the mode filter of feedback delay with 12 code element clock gaps.(in the absence of the co-channel interference of obvious NTSC, this its receiver of system that grants patent comprises the rearmounted encoder of a complementary mold, be used for substituting comb filter is handled received signal in case the S/N that is attributable to it than performance degradation) the ATSC digital television standard and the United States Patent (USP) U.S.Pat.No.5 that publish September 16 nineteen ninety-five, 600,677 and U.S.Pat.No.5, disclosed system in 583,889 with TCM and above-mentioned comb filter.

Adopt in the middle of the system of TCM and comb filter, each offers precoder and lattice structure encoder to the input data bit.Precoder is delivered in one of them position of each contraposition, and each contraposition is wherein delivered to the lattice structure encoder in another position.Precoder and lattice structure encoder be integrated one or more 12 digit delay elements respectively.Like this, precoder and lattice structure encoder can be envisioned as have below (i) and (ii) 12 identical precoders and lattice structure encoder: (i) be used to make 2 input group to be linked in sequence to the input adapter (being coupler) of 12 identical precoders and lattice structure encoder; And (ii) be used to make output group and the output adapter (being multiplexer) that symbol mapper is linked in sequence of 3.

12 precoders and lattice structure encoder interweave to paired position, so that each one-tenth contraposition of first byte is by first precoder and lattice structure coder processes in the data, and each of second byte becomes contraposition by second precoder and lattice structure coder processes in the data,, each one-tenth contraposition of the 12 byte is by the 12 precoder and lattice structure coder processes in the data.Same 12 bytes handling each subsequent group.Symbol mapper maps to one with 3 carry-out bits of each group and has 8 code elements that signal level is wherein corresponding of 8 grades of structure pictures.The code element that is generated is delivered to a multiplexer, and sync symbols is formed data and this structure of sync symbols in the Calais mutually frame by frame with data symbols.

The 6MHz channel frame forms one and has 313 segmented structure.Frame first segmentation (frame synchronization segmentation) comprising: (i) comprise the segment sync part of 4 segment sync code elements and the field sync part of the field sync code element that (ii) comprises 828 pseudorandoms generations.Each comprises other 312 segmentations (data sementation): the segment sync part and the data division that (ii) comprises 828 data code elements that (i) comprise 4 segment sync code elements.

Send each code element in the above-mentioned frame structure then, and receive by receiver.This receiver comprises comb filter and lattice structure decoder.This comb filter that is provided is used for the interference that filtering may be caused by the NTSC channel that near platform is broadcasted.This lattice structure decoder (for example Viterbi decoder) that is provided is used for each symbol decoding in the middle of institute's received frame is its corresponding original one-tenth contraposition.The lattice structure decoder is similar with dative structured coding device aspect the code element of identical bytes processing together at the lattice structure decoder.Like this, these code elements must be imported the lattice structure decoder in the correct order.

Above mentioned the application and other common unexamined applications relate to the modification to above-mentioned 6MHz VSB system, so that can operate and have the co-channel interference capability of reduction PAL on standard 8MHz television channel.In the middle of the system of the present invention, chip rate preferably is fixed on about 14.14MHz (but not 10.76MHz).And adopt the lattice structure coding method of one 9 tunnel (but not 12 tunnel), Frame to comprise 289 segmentations (but not 313 segmentations).The VSB system that the VSB system that prior art discloses and the application disclose, both all utilize lower part I and United States Patent (USP) U.S.Pat.No.5, illustrated multimode in 677,911.

The receiver of first aspect present invention, it is characterized in that, be used for the digital VSB signal that comprises start bit, segment sync code element and data symbols is received the decode, wherein said start bit, segment sync code element and data symbols are the multistage code elements through a lattice structure encoder encodes, wherein the corresponding segment sync symbols in the middle of each described start bit and the described segment sync code element is combined to generate an output segment sync code element with a predetermined value in described lattice structure encoder, and wherein said receiver comprises:

One tuner, be tuned to a selected channel; And

One lattice structure decoder is decoded to the described start bit that receives in this tuning selected channel, described segment sync code element and described data symbols.

Brief Description Of Drawings

The features and advantages of the present invention will become clear after reading the explanation of doing below in conjunction with accompanying drawing, wherein:

Fig. 1 adopts a system block diagram of optimizing the existing TCM system of PRML estimation of the order (MLSE) Viterbi decoder;

Fig. 2 A illustrates the novel data frame structure of the present invention;

Fig. 2 B illustrates frame synchronization (FS) segmental structure of Frame among Fig. 2 A;

Fig. 2 C illustrates the data sementation structure of Frame among Fig. 2 A;

Fig. 3 A is the chart of expression data structure picture size of the present invention and other parametric relationships;

Fig. 3 B is the chart of expression TCM code parameters of the present invention and other parametric relationships;

Fig. 4 A is the simplified block diagram of transmitter of the present invention;

Fig. 4 B bytes that are bytes that transmitter among Fig. 4 A is shown to symbol transformations device and the mapper 36 are to the chart of symbol transformations device part embodiment;

Byte when Fig. 5 represents to be in the 8VSBT mode among Fig. 4 A is to the running of symbol transformations device and mapper;

The running of data symbols interleaver 42 in Fig. 6 presentation graphs 5;

The running of convolution coder 44 in Fig. 7 presentation graphs 5;

Fig. 8 illustrates and can dispose with the comb filter that the present invention uses;

Fig. 9 is the simplified block diagram by the receiver of the present invention's structure;

Figure 10 is the more detailed expression of the data processor 68 of receiver among Fig. 9;

Figure 11 be received signal when being in the 8VSBT mode among Figure 10 code element to the more detailed expression of byte converter 84 runnings;

Figure 12 is the more detailed expression of 9 road Viterbi decoders 90 among Figure 11;

Figure 13 is the more detailed expression of symbol de-interleaver 94 among Figure 11;

Figure 14 represents the generation of non-TCM mode start bit;

Figure 15 a is the more detailed block diagram of the transmitter that operates under the 8VSBT mode according to the present invention;

Figure 15 b is the more detailed block diagram of the receiver that operates under the 8VSBT mode according to the present invention;

Figure 16 further is shown specifically 9 road convolution coders 120 among Figure 15 a;

Figure 17 further is shown specifically representative among a Figure 16 convolution coder unit;

Figure 18 illustrates the convolution coder as the replacement scheme of 9 road convolution coders shown in Figure 17;

Figure 19 illustrates the mapping function of symbol mapper 122 among Figure 15 a;

Figure 20 is the status transition chart of convolution coder among Figure 17;

Figure 21 illustrates the status change with output lattice structure encoded segment sync symbols of encoder generation among Figure 17;

Figure 22 further is shown specifically 9 * 4 data symbols interleavers 116 among Figure 15 a;

Figure 23 is the form that its code element of 9 road convolution coders takies situation among expression Figure 16;

Figure 24 is the form that further is shown specifically convolution coder running among Figure 17;

Figure 25 is based on the lattice structure status transition chart of form among Figure 24;

Figure 26 illustrates the combination that operates on comb filter 132 and 9 road Viterbi decoders 138 among Figure 15 b that supports the comb filter mode;

Figure 27 is the useful equivalent electric circuit that disposes among Figure 26;

Figure 28 illustrates 9 road Viterbi decoders 138 that operate among Figure 15 b that avoids the comb filter mode;

Figure 29 is the further functional block diagram of the optimization MLSE Viterbi decoder 166A-166I of expression in detail among Figure 28;

Figure 30 is that expression can be used for substituting and optimizes the MLSE Viterbi decoder among Figure 29 and reduce every Y ₁And Y ₂The schematic diagram of the circuit of estimating;

Figure 31 is the further functional block diagram of the optimization MLSE Viterbi decoder 166A-166I of expression in detail among Figure 27;

Figure 32 illustrates the form that TCM encoder of the present invention operates the effect of comb filter 132 introducings that comprise receiver among Figure 15 b;

Figure 33 represents the coset as a result that comb filter 132 makes up two subclass resulting effect and taken place;

Figure 34 represents central 7 cosets that take place of form among Figure 33;

Figure 35 is based on the lattice structure status transition chart of form among Figure 32;

Figure 36 is the functional block diagram according to the Viterbi decoder of lattice structure schematic diagram programming among Figure 35;

Figure 37 illustrates to utilize Viterbi decoder among Figure 36 to reduce block diagram to the estimation of send position X1 and X2;

Figure 38 be expression have the coupler/multiplexer of frame synchronization synchronous, to another diagrams of 9 road Viterbi decoders 45 among Figure 15 b; And

Symbol de-interleaver 142 among the further detailed presentation graphs 15b of Figure 39.

The explanation of preferred embodiment

Following explanation comprises 2 major parts, i.e. part I and part II.Part I discusses novel data frame structure.Only with reference to the TCM sign indicating number transmitter of whole VSB modes (non-TCM coding and TCM encode) and the running of receiver have been discussed by the level of detail that also is enough to illustrate the data frame structure needs.Part II goes through novel TCM coded system and the transmitter that is associated and the running of receiver.

Part I

New data frame structure of the present invention shown in Fig. 2 A.This Frame with label 24 marks, comprises 289 segmentations usually.All segmentation comprises 836 code elements.

Shown in Fig. 2 A and Fig. 2 B, first segmentation of Frame 24 is labeled as FS (frame synchronization), and since one 4 code element segment sync symbol 26, each 4 code element is 2 grades of code elements.This symbol can be United States Patent (USP) U.S.Pat.No.5, the form that discloses in 416,524.Ensuing 823 code elements of this frame synchronization segmentation also are 2 grades of code elements, comprising: 700 code elements that form a pseudorandom sequence frames synchronous code; 24 used code elements of VSB mode identifier to the data of 288 segmentations of Frame 24 remainders and start bit (in part II, defining after a while) identification progression M (for example 16,8,8T, 4 or 2); And the retaining space of 99 code elements.ATSC digital television standard and United States Patent (USP) U.S.Pat.No.5 have disclosed this pseudorandom sequence frames synchronous code in 619,269.(what it should be noted that this patent discloses is utilization to 3 pseudorandoms orders in the field sync signal and one 24 code element VSB mode identification signals.) the VSB mode discerns following disclosure.As illustrated among the part II after a while, last 9 code elements of FS segmentation are the repetitions to last 9 code elements of the last segmentation of former frame.

288 remaining in the middle of the Frame 24 segmentations are the data sementations that are labeled as DS0-DS287.Shown in Fig. 2 C, Frame with the FS segmentation in used 2 grade of 4 identical code element segment sync symbol 26 be beginning.This segment sync symbol back then comprises 832 code elements of 828 data code elements and 4 start bits.These 4 start bits are taked the form discussed after a while in part II.

Shown in form among Fig. 3 A, each data symbols is represented 4 (M=16), 3 (M=8), 2 (M=4 or 8T) or 1 (M=2) among the data sementation DS0-DS287.Because every frame has the data symbols (288 * 828=238,464) of fixed number, so the data byte number of each frame will change as shown in the figure.That is to say that each Frame 24 comprises 119,232 data bytes concerning VSB mode M=16; Concerning VSB mode M=8, comprise 89,424 data bytes; Concerning VSB mode M=4 or 8T, comprise 59,616 data bytes; Concerning VSB mode M=2, then comprise 29,808 data bytes.Though each frame data byte number changes with VSB mode M, can notice that concerning any one specific M value (16,8,8T, 4 or 2), each Frame 24 all provides integral words to save.In fact the architectural characteristic of this Frame 24 simplifies the design to receiver.As below will further describing, receiver forward error correction circuit, receiver code element to byte converter and receiver byte deinterleaver better keep frame synchronization with the whole VSB mode signals that sent, and receiver Viterbi decoder and data symbols deinterleaver preferably keep frame synchronization to the 8VSBT mode.Frame synchronizing signal can be directly used in these purposes, as long as each each Frame of VSB mode is had integral words joint, forward error correction piece and byte-interleaved group, as long as the Frame of each 8VSBT mode has an integer TCM code set (TCG) that defines below and the data symbols that defines below equally interweaves group (DSIG).

Adopt Read-Solomon (RS) forward error correction in the receiver of the present invention.The standard that MPEG (Motion Picture Experts Group) committee has established 188 bytes transmits the grouping scale.This grouping can be reduced to 187 bytes by removing the MPEG sync byte because of the appearance of segment sync symbol 26.Transmission grouping to each this 187 byte increases the RS block size that 20 parity bytes obtain 207 bytes, allows each RS piece is carried out the error correction of 10 bytes.As shown in Figure 3A, the RS block size of 207 bytes usefully causes each frame integer RS piece to all selected VSB mode, therefore allows the RS decoder of receiver to keep synchronously by frame synchronizing signal.

Convolution byte-interleaved group scale (B) is defined as by the present invention and comprises B=54 data byte (other numerical value of available B), and this defines as shown in Figure 3A, no matter how selected VSB mode causes each frame integral words to save the group that interweaves equally.This convolution byte-interleaved group scale also allows frame synchronizing signal to be used to make the deinterleaver periodic synchronous of receiver, therefore makes the receiver design simplification.

For 8VSBT mode and Fig. 3 B, described in lower part II, 9 code elements in a certain moment by 9 independently convolution coder with the parallel mode convolutional encoding.Above-mentioned 9 code elements can be called TCM code set (TCG).Whole 836 code elements (segment sync, data and start bit) in each 288 data segmentation are all encoded through TCM.So, can an integer TCG be arranged as can be known in the Frame 24 by following equation:

This integer TCG allows frame synchronizing signal to be used for making the Veterbi decoding processing hold period of receiver synchronous.

And for the 8VSBT mode, as described in part II after a while, beneficially, the data symbols that identical bytes is associated is by same processing the in 9 TCM encoders.Can interweave and organize 9 * 4 data symbols interleavers that operate on 36 data code elements of DSIG by adopting being defined as data symbols, most code elements are realized this processing.Noting, only is that data symbols interweaves in this way.Start bit and segment sync code element are not included in this symbol interleave process.Thereby each data sementation has an integer DSIG (828/36=23).So every frame has an integer DSIG:

(828/36 DSIG of each data sementation) * (288 data segmentations of every frame)=6624 DSIG of every frame

This integer DSIG allows frame synchronizing signal to be used for making the symbol de-interleaver hold period of receiver synchronous.

Fig. 4 A is the simplified block diagram by the transmitter of the present invention's structure.The data source 30 of TV signal is connected with a Reed Solomon Coding device 32 delivers to a convolved data byte interleaver device 34, and then will deliver to a byte to symbol transformations device and mapper 36 through the data byte that interweaves.Will be understood that, this data source can provide through the HDTV of overcompression signal (or according to the VSB mode be 2 through the HDTV of overcompression signal) or several standard-definition signals through overcompression.Byte to the code element of symbol transformations device and mapper 36 output deliver to one by VSB mode control signal with byte to symbol transformations device and mapper 36 controlled frame formatter 38.Meet previous configuration through formative frame, deliver to a VSB modulator 40 and be used on the 8MHa television channel, transmitting in conjunction with Fig. 2 and Fig. 3 explanation.This transmission medium can comprise a cable television appliances or terrestrial broadcasting environment.No matter any situation needs a kind of like this transmitter concerning the 8MHz channel that each sent.

Byte to symbol transformations device and mapper 36 has two kinds of working methods: a kind ofly be used for non-TCM mode, another kind is used for 8VSBT.A mode chart shown in Fig. 4 B.For non-TCM mode, this chart comprises 4 row, and each VSB mode M=16, M=8, M=4 and M=2 are 1 row.Byte to symbol transformations device and mapper 36 responds the VSB mode control signal that is added, with the respective column according to chart among Fig. 4 B the data byte of being imported is transformed to data symbols output.For instance, to VSB mode M=16, the data byte of being imported 11010101 will be transformed to 2 continuous data symbols with corresponding+88 and-40 relative amplitudes.To VSB mode M=8, the data byte of this input will be transformed to 3 continuous have corresponding+80 ,+48 and-16 (first that supposes next data byte is 1) or+80 ,+code element of the relative amplitude of 48 and-48 (first that supposes next data byte is 0).To VSB mode M=4, this data byte will be transformed to 4 continuous code elements with corresponding+96 ,-32 ,-32 and-32 relative amplitudes.To VSB mode M=2, will be given+64 ,+64 ,-64 ,+64 ,-64 ,+64 ,-64 with 8 output symbols of+64 relative amplitudes.To VSB mode M=8T, this data byte will be transformed to 48 grades of continuous code elements by the complex way that only describes in detail among the part II after a while now in conjunction with Fig. 5 and Fig. 6 brief description.

When Fig. 5 represents to be in the 8VSBT mode among Fig. 4 A byte to the running of symbol transformations device and mapper 36.Import a data symbols interleaver 42 through the data byte that interweaves, this data byte is decomposed into the data symbols of 2 un-encoded, carry out one 9 tunnel symbol interleave.Then, according to the state of each convolution coder (in part II, illustrating after a while) in 9 road convolution coders 44, starting (P) code element of un-encoded and segment sync (S) code element of un-encoded are inserted in the data flow in the relevant position by symbol inserter 46.The combination of start bit, segment sync code element and the data symbols of 288 data segmentations of 44 pairs of Frames 24 of 9 road convolution coders is encoded.That is to say that 9 road convolution coders 44 are encoded to 3 positions through convolutional encoding with per 2 input positions.The output of 9 road convolution coders 44 is connected with a mapper 48, each is mapped as one through 3 of convolutional encoding has one of them code element of 8 output stages (with reference to Fig. 4 B the 2nd row).Then, to each the 289th segmentation, insert a frame synchronization segmentation FS by frame formatter 38.

As shown in Figure 6, be input to data symbols interleaver 42 (being preferably 9 * 4 symbol interleaver) through the data byte that interweaves.1 position of input adapter 50 each byte stepping.Each data byte comprises 4 and is appointed as [X ₀X ₁X ₂X ₃] 2 bit symbols.Data sementation comprises 207 data bytes (828 data code elements).The data byte segmentation that inputs to data symbols interleaver 42 comprises 42 bit symbols respectively, can be appointed as:

[0 ₀0 ₁0 ₂0 ₃][1 ₀1 ₁1 ₂1 ₃][2 ₀2 ₁2 ₂2 ₃]…[206 ₀206 ₁206 ₂206 ₃]

Data symbols interleaver 42 is as 1 position output symbol of output adapter 52 each code element stepping.A circular in definition of data symbols interleaver 42 is 9 steps of input adapter 50 (each step input one byte) to scan 4 the 9 step scannings that output adapter 52 (each step output one code element) followed in the back.Each circulation interweaves 36 code elements (9 complete bytes) like this.Each data sementation has 828/36=23 circulation (each Frame has 288 * 23=6624 circulation).Each data sementation of initial sum of each Frame 24 initial all will be imported adapter 50 and output adapter 52, and the two is set at first circulation that its apical position begins this data sementation.The data symbols of 52 pairs one data sementations of the output adapter of data symbols interleaver 42 (not comprising start bit and segment sync code element that symbol inserter 46 is increased) ordering is output as:

…0 ₀1 ₀2 ₀3 ₀4 ₀5 ₀6 ₀7 ₀8 ₀0 ₁1 ₁2 ₁3 ₁…789 ₀10 ₀…17 ₀9 ₁10 ₁

…206 ₂198 ₃3199 ₃200 ₃201 ₃202 ₃203 ₃204 ₃205 ₃206 ₃…

After this symbol interleave, then in position be inserted in the data flow by the start bit and the segment sync code element of symbol inserter 46 with un-encoded.The data sementation of each 828 data code element is by the sync symbols guiding of 4 un-encoded.And the start bit of 4 un-encoded just in time is inserted into the front of last 5 the data code elements of this segmentation.This configuration cause 9 symbol intervals between start bit and corresponding segment sync code element so that they can import the same convolutional encoder 44A-44I of 9 road convolution coders 44 that more are shown specifically among Fig. 7.The numerical value of start bit and sync symbols as among the part II after a while further as described in, by them the current state of the convolution coder 44A-44I of input (in the middle of 9 one) is determined.The output of symbol inserter 46 to the code element of partial data segmentation ordering is:

…S ₀S ₁S ₂S ₃0 ₀1 ₀2 ₀3 ₀4 ₀5 ₀6 ₀7 ₀8 ₀0 ₁1 ₁2 ₁3 ₁…

206 ₂198 ₃199 ₃200 ₃201 ₃P ₀P ₁P ₂P ₃202 ₃203 ₃204 ₃205 ₃206 ₃…

As shown in Figure 7, the input adapter 54 of 9 road convolution coders 44 and output adapter 56 switch together to each code element.One circulation may be defined as 9 steps of input and output adapter 54 and 56.If input and output adapter 54 and 56 all is in the position, top of the Frame first data sementation original position, input and output adapter 54 just is in the position, top that it conforms to the segmentation original position in 9 segmentations (836 circulations) afterwards once more with 56.Because every frame has 288 data segmentations, and 288/9=32 is an integer, so input and output adapter 54 and 56 will be in the position, top of its each subsequent data frame 24 original positions.This running can make transmitter and receiver hardware be convenient to design.The code element that ordering entered and shifted out 9 road lattice structure encoders 44 does not change.

Previously described symbol interleaver 42 its purposes are, data symbols are placed an ordering so that pass through identical convolution coder (and identical Viterbi decoder of receiver) with those data symbols of given syllable dependent connection.It is comparatively favourable that this " byte encapsulation " has been found in certain damage aspect of inhibition.If given Viterbi decoder have can't error correction mistake, just trend towards error propagation to subsequent symbol.If the code element in the middle of the identical bytes is packaged into identical lattice structure decoder, just little on average byte is subjected to the influence of error propagation.In part II, " byte encapsulation " provided more specifically details below.

The output of each convolution coder 44A-44I maps to each symbol level by mapper 48 (Fig. 5) according to secondary series among Fig. 4 B.In the middle of 9 convolution coder module 44A-44I (comprising convolution coder and mapper) each more specifically details in part II, disclose after a while.

Byte to symbol transformations device and mapper 36 provides signal to frame formatter 38.To whole VSB modes, frame formatter 38 is inserted into the frame synchronization segmentation FS of 836 code elements in the middle of the code element stream.The generation of this insertion is prior to 288 data segmentations of each group.The frame synchronization segmental structure provides as follows among Fig. 2 B:

[S ₀S ₁S ₂S ₃] [ATSC PN sequence] [VSB mode] [not stipulating code element] [P ₀P ₁P ₂P ₃Ddddd]

Code element [S ₀S ₁S ₂S ₃] (4 sync symbols are arranged) be 2 grades of code elements to keeping code element (have 99 keep code elements).Code element [S ₀S ₁S ₂S ₃] expression segment sync waveform.Comprise identical that the PN sequence of 700 code elements can be with disclosed in the ATSC digital television standard of ATSC 6MHz system.Similar in VSB mode ID sign indicating number (24 mode code elements are arranged) and the ATSC 6MHz system, and explanation below.To non-TCM mode, last 9 code elements of frame synchronization segmentation are unspecified 2 grades of code elements.To 8VSBT, last 9 code element [P of frame synchronization segmentation ₀P ₁P ₂P ₃Ddddd] be one 8 grades of code elements, be last 9 repetitions in the middle of the last data frame through the TCM symbols encoded.There are not TCM or RS sign indicating number for the frame synchronization code element.Note, in the middle of the 8VSBT mode, encode through TCM during last 9 frame synchronization code elements (repetition symbols) segmentation formerly.

In the middle of the non-TCM mode, insert 42 grades of segmentation sync symbols in each data sementation original position by frame formatter 38.4 start bits that in the end will be comprised multistage pseudo-random data by frame formatter 38 before 5 data code elements are inserted into each data sementation.Frame formatter 38 is increased to data flow under non-TCM mode situation start bit is generated by PN shown in Figure 14 (pseudo random number) sequence generator 104 and PN mapper 106.This PN sequence generator 104 exports the pseudo-random binary data flow to PN mapper 106.Offer the VSB mode (2,4,8 or 16) that also has signal to be encoded of this PN mapper 106.PN mapper 106 is according to Fig. 4 B running, and its output is used to generate the start bit of non-TCM mode.This start bit is received device and gives up.

In the 8VSBT mode, segment sync code element and start bit are added to data flow by symbol inserter 46, so above-mentioned code element no longer is added to any data sementation by frame formatter 38.

The VSB mode is represented by 3 bytes that are connected on PN sequence back in the frame synchronization segmentation (24 2 grades of code elements).These 3 bytes are 0000111P, ABC PABC1 and PABC PABC, wherein variety of way are provided A, B, C and P value by following table.In fact represent mode for the 3rd of above-mentioned byte.Preceding 2 bytes then form and can read under the situation that comb filter (with reference to Fig. 8) is allowed to or gets around in 9 branches.The A of each mode, B, C and P value are shown in following table.

Table 1

P	A	B	C	Mode
P	A	B	C	Mode		0	0	0	0	2VSB
1	0	0	1	4VSB		0	0	0	0	2VSB
1	0	0	1	4VSB	1	0	1	0	8VSB
0	0	1	1	Keep	1	0	1	0	8VSB
0	0	1	1	Keep	1	1	0	0	16VSB
0	1	0	1	8VSBT	1	1	0	0	16VSB
0	1	0	1	8VSBT	0	1	1	0	Keep
1	1	1	1	Keep	0	1	1	0	Keep

Disclosed the VSB receiver that utilizes comb filter to be used to suppress co-channel interference in above-cited ' 975 patent and the U.S. Patent No. 6,246,431.United States Patent (USP) U.S.Pat.No.5 discloses the utilization to 2 paths in the receiver in 260,793, and a path adopts comb filter, and another path then gets around this comb filter, is determined the selection of path by the appearance of interference signal.

Among the present invention, (as U.S. Patent No. 6,246, described in 431) receiver uses one 9 branches feedforward comb filter 58 as shown in Figure 8 with a

summator

60 and 9 symbol delay devices 61.If this comb filter 58 is got around in receiver, the VSB mode just can be determined according to top table 1 at an easy rate.If this comb filter 58 is not got around, this code element just will be changed by the summator in the comb filter 58 60.As mentioned above, each code element of the 3rd mode byte is by one of them code element guiding of identical value 9 code elements of morning.Even if this code element arrangement also allows this mode is easy to judge under the situation of this comb filter support.For instance, if supposition VSB mode is the 8VSBT mode, the symbol level of 3 byte mode fields that sent just can be expressed as follows:

-5-5-5- 5+5+5+5-5 +5-5+5+5 -5+5-5+5 -5+5-5+5 +5-5+5-5

Above-mentioned corresponding to binary digit

0,000 1,110 1,011 0,101 0,101 1010 last 8 code elements (position) represent that this mode is the 8VSBT mode.If this comb filter got around, used above-mentioned at different levels of these last 8 code elements are easy to be interpreted as 0 or 1, thereby can determine the VSB mode

If this comb filter is supported, last 8 code element outputs through filtering will be expressed as follows:

-10+10-10+10 +10-10+10-10

These also are easy to be interpreted as 0 or 1, produce and are got around the identical result of situation with comb filter.Should be understood that this method can work to any VSB mode.

With noted earlier relevant, will be noted that the relative level of each VSB mode code element has even interval, be in the central position between each relative level of the selected code element of whole higher VSB modes.For instance, relative level+112 of VSB mode M=8 be in its relative level of VSB mode M=16+120 and+central position between 104, relative level+96 of VSB mode M=4 be in its relative level of VSB mode M=8+112 and+central position between 80 and its relative level of VSB mode M=16+104 and+central position between 88, relative level+64 of VSB mode M=2 be in its relative level of VSB mode M=4+96 and+32 central position, its relative level of VSB mode M=8+80 and+48 central position and its relative level of VSB mode M=16+72 and+central position between 56, the rest may be inferred.Preferably symbol level staggered with the numerical value shown in the scheduled volume (for example+20) before transmission, was used for making the carrier wave of receiver to obtain easily little pilot tone.To notice that also the data rate that characterizes each VSB mode increases by 1 with respect to each code element of data rate of instant lower VSB mode, its S/N reduces half than performance simultaneously.

Fig. 9 is the simplified block diagram by the receiver of the present invention's structure.The RF TV signal that transmitter receives from Fig. 4 A comprises that one has the M level VSB signal of frame format among Fig. 2 A, Fig. 2 B and Fig. 2 C.The signal that is received is transformed to an IF frequency (intermediate frequency) by a tuner 62, and the signal that is in IF that is received is delivered to a VSB demodulator 64.This VSB demodulator 64 generates an Analog Baseband output signal that comprises the M level code element of about 14.14 million code elements/second speed.This analog signal is by being binary form with symbol transformations and it being delivered to modulus (A/D) converter 65 sampling of data processor 68.Data processor 68 provides a feedback signal that is used to control A-D converter 66 to guarantee that this analog baseband signal is with suitable symbol time sampling (as United States Patent (USP) U.S.Pat.No.5, disclosed in 416,524).Data processor 68 will this treated binary data by delivering to a coupler 70 with the corresponding data byte form of the output in the TV data source 30 shown in Fig. 4 A, with this data allocations that receives to a video processor 72 that comprises corresponding decompression circuit respectively and an audio process 74.

Data processor 68 illustrates in Figure 10 in more detail.The binary element of A-D converter 66 outputs is delivered to a data acquisition 76, generates the feedback signal that is used to control A-D converter 66.This data acquisition 76 also generates the following column signal that can be used for whole each frame among Figure 10: the code element clock signal; Frame synchronization (FSYNC) signal; Segment sync; One 8 times of code element clock signals; Byte clock signal and RS grouping initial signal.This code element clock signal has about 14.14MHz frequency to whole VSB modes.FSYNC signal used in the preferred embodiment is close to 53.7Hz.The frame swynchronization code of frame synchronization segmentation FS allows to derive in time the FSYNC signal that conforms to first data symbols of the data sementation DS0 of each Frame 24.

The binary element of A-D converter 66 outputs (amplitude of the analog signal of the process sampling of expression VSB demodulator 64) is delivered to a comb filter 78 by data acquisition 76 as shown in top Fig. 8.Explanation after a while is used for this comb filter 78 of 8MHz channel.United States Patent (USP) U.S.Pat.No.5 describes a comb filter that is used for the 6MHz channel in 087,975 in detail.(different with the addition combiner with 9 symbol delay among Fig. 8, the comb filter that discloses in this patent has 12 code elements, and adopts a subtractive combination device.) output of comb filter 78 delivers to a multistage amplitude limiter 80, by the chart among Fig. 4 B the symbol transformations that is received returned digit order number.Multistage amplitude limiter 80 is delivered to a VSB mode decoder with the amplitude limit value of VSB mode ID among the frame synchronization segmentation FS of each Frame 24 (24 2 grades of code elements), detects 24 VSB mode ID and progressively manifests one 3 VSB modes and select signal.This VSB mode selects signal that the VSB mode (M=16,8,8T, 4 or 2) of institute's receiving symbol is discerned, in the remaining period of each Frame 24 control data acquisition cuicuit 76, comb filter 78, multistage amplitude limiter 80 and code element to byte converter 84.

Multistage amplitude limiter 80 these VSB modes of response comprising 9 output buss are selected signal, are used for the binary signal of expression symbol magnitude is transformed to the numerical value of its corresponding position.Like this, in the M=2 VSB mode, each binary element amplitude signal 9 output buss wherein up conversion be 1 corresponding signal; In the M=4 VSB mode, each binary element amplitude signal output bus wherein two up conversions be 2 corresponding signals; In the M=8VSB mode, each binary element amplitude signal output bus wherein three up conversions be 3 corresponding signals; And in the M=16 VSB mode, each binary element amplitude signal output bus wherein four up conversions be 4 corresponding signals.All in the middle of the VSB mode, multistage amplitude limiter 80 is not exported the code element from the frame synchronization segmentation.In the 8 VSBT modes, the segmentation of output total data comprises data sementation sync symbols and start bit.In the

mode

2,4,8 and 16, dateout code element only.9 outputs of multistage amplitude limiter 80 select the timing signal of signal and data acquisition 76 to deliver to code element to byte converter 84 with 3 VSB modes of VSB mode decoder 82.

For non-TCM mode, code element to byte converter 84 as United States Patent (USP) U.S.Pat.No.5,631,645 described such runnings.For 8 VSBT modes, code element to byte converter 84 as below and after a while described in the part II as one Viterbi decoder/symbol de-interleaver running.A byte deinterleaver 86 is given in code element to the output of byte converter 84, and then gives a RS decoder 88.Code element to byte converter 84 will be represented a series of 8 bit data bytes of the input bit map of institute's receiving symbol for each VSB mode.The data byte that the process convolution mode that 86 pairs of code elements of byte deinterleaver are provided to byte converter 84 interweaves carries out deinterleaving, and 88 pairs of data bytes through deinterleaving of RS decoder carry out error correction.

For 8 VSBT modes, illustrate in more detail that below in conjunction with Figure 11-Figure 13 and in part II code element is to the running of byte converter 84 in the receiver.Figure 11 illustrates the general view of this code element to byte converter 84 interior Veterbi decoding systems.Start bit, segment sync code element and data symbols through the TCM coding are decoded in one 9 road Viterbi decoder 90.Viterbi decoder is known to the method for decoding through the TCM encoded signals.The start bit of un-encoded and segment sync code element are eliminated in the middle of the code element stream through decoding by a starting and segment sync code element stripper 92.Become again to byte with of the data symbols formation of one 9 * 4 symbol de-interleaver 94 un-encoded.Make whole runnings synchronous by code element clock, frame synchronization and segment sync.

9 road Viterbi decoders 90 shown in Figure 12.Each can utilize known Veterbi decoding method single Viterbi decoder 90A-90I.Input and

output adapter

96 and 98 is under the control of the switch controller 99 that responds the running of code element clock and frame synchronization, and each code element clock all switches together.Decoder cycle is defined as input and

output adapter

96 and 98 both 9 step scannings.By frame synchronizing signal force input and

output adapter

96 and 98 both to its apical position.After 9 data segmentations (836 cycles), input and output adapter 96 will be in the apical position that it conforms to the segmentation original position again with 98.Because each Frame has 288 data segmentations, and 288/9=32 is an integer, so input and

output adapter

96 and 98 will be in its apical position in each subsequent data frame 24 original position.

Start bit, segment sync code element and the data symbols of 9 road Viterbi decoders, 90 output un-encoded.The code element ordering that passes in and out this 9 road Viterbi decoder 90 does not change, and is represented by following code element:

The output of 9 road Viterbi decoders 90, start bit and segment sync code element are easy to be eliminated in the middle of data flow by the segment sync timing signal that is reduced in the part morning with reference to receiver by starting and segment sync code element stripper 92 among Figure 11.At this moment only un-encoded but through the data symbols that interweaves still by shown in the following code element:

…0 ₀1 ₀2 ₀3 ₀4 ₀5 ₀6 ₀7 ₀8 ₀0 ₁1 ₁2 ₁3 ₁…7 ₃8 ₃9 ₀10 ₀…17 ₀9 ₁10 ₁

…206 ₂198 ₃199 ₃200 ₃201 ₃202 ₃203 ₃204 ₃205 ₃206 ₃…

By among Figure 13 more 9 * 4 symbol de-interleaver 94 of detailed icon realize that code elements are to the byte conversion.The data symbols of un-encoded inputs to 9 * 4 symbol de-interleaver 94.Input adapter 100 is to position of each data symbols stepping.Output adapter 102 is to position of each data byte stepping, and wherein each byte comprises 42 bit symbols.

The period definition of 9 * 4 symbol de-interleaver 94 is 49 step scannings of (each step input one 2 bit data code element) input adapter 100, and then one the 9 step scanning of (each step output one byte) output adapter 102.Like this, each cycle makes 36 code elements (9 complete bytes) deinterleaving.Each data sementation has 828/36=23 cycle, and each Frame has 288 * 23=6624 cycle.The original position of each Frame 24 forces input and output adapter 100 and 102 to begin period 1 of data sementation to its apical position.Because in fact each Frame has 6624 cycles, this adapter will be in its apical position in each subsequent data frame original position.So the segmentation of the data byte output of 9 * 4 symbol de-interleaver, 94 outputs is just as follows:

As explained above, byte deinterleaver 86 is delivered in code element to the output of byte converter 84.As after this will further describing, byte deinterleaver 86 utilizes MIN memory that the data byte that the process convolution mode that receives from code element to byte converter 84 interweaves is carried out deinterleaving.

As everyone knows, finish byte-interleaved (convolved data byte interleaver device 34 in reference to Fig. 4 A) here at transmitter continuous data byte is disperseed each other, help to make the data that send to exempt from the short pulse The noise.In the receiver, must be to carrying out deinterleaving through the byte that interweaves so that before forward error correction, rebuild its primitive relation.Like this, the short pulse noise of some given duration will make in the RS of deinterleaved data piece only limited number byte make mistakes.Above-mentioned byte of makeing mistakes can be by RS decoder 88 error correction in the receiver (Figure 10).

In the expectation process to greatest expected short pulse noise duration of maximum byte clock rate (promptly corresponding), select the used algorithm that interweaves to guarantee that RS decoder 88 can carry out error correction to the data byte through deinterleaving of makeing mistakes with VSB mode M=16.Like this, along with the increase of noise duration of greatest expected short pulse, this algorithm that interweaves must make the continuous data byte further separate.As an alternative, can adopt RS sign indicating number with better function, but its shortcoming of this method is to use more expense, promptly needing more, multibyte is used for error correction.And; by making system with reference to highest byte clock rate (corresponding) with 16VSB; the short pulse error protection of raising will be provided with the decline of VSB mode and corresponding byte-rate, and this is because how to make interlace mode obtain carrying out in given number bytes range regardless of the VSB mode.

The convolutional interleave algorithm is generally used for making the data that send to exempt from the short pulse noise effect.This algorithm postpones the single byte of successive byte group by different quantity, is sometimes referred to as interleave depth, and this byte effectively is scattered in the part or all of Frame 24.Carry out deinterleaving by making received byte postpone opposite quantity.Implement a kind of like this system, below 3 parameters acquire a special sense: but the number of the byte errors T of greatest expected short pulse length BL, 88 error correction of RS decoder and RS grouping scale.

As previously described, being preferably in has an integer RS grouping in the Frame 24, so that RS decoder 88 can be synchronous by frame synchronizing signal FSYNC.By selecting one (preferably each frame has integer number) interleaved packet scale to make it to equal B parameter=BL/T, and be equal to or greater than RS grouping scale by the integral multiple with parameter N and select different delays, RS decoder 88 can carry out error correction until the greatest expected duration of BL byte clock to the data through deinterleaving with regard to the short pulse noise.

Consider that wherein greatest expected short pulse length is 4 data byte clocks, RS decoder 88 can carry out the system of error correction to a data byte errors in the RS grouping (being BL=4, T=1, N=8) of each 8 data byte simplification example.Utilize these parameters, this group scale B=BL/T=4/1=4 that interweaves.Carry out convolutional interleave with above-mentioned parameter, so that to each group B=4 data byte, first data byte faces 0 to postpone, second data byte faces the delay of 1N=8 data byte clock, the 3rd data byte faces the delay of 2N=16 data byte clock, and the 4th data byte faces the delay of 3N=24 data byte clock.Postpone to carry out deinterleaving by being inverted, so that the data byte that each group process that B=4 received is interweaved, first data byte postpones 3N=24 data byte clock, second data byte postpones 2N=16 data byte clock, the 3rd data byte postpones 1N=8 data byte clock, and the 4th data byte then postpones 0.

The convolution de-interleaver of the above-mentioned algorithm of existing enforcement comprises that one has the memory of (B-1) N/2 memory location.For the reality value of B and N, these values are usually many greatly than numerical value used in the simplification example that provides above, because a large amount of shift register of needs, existing deinterleaver has a labyrinth very.An adoptable alternative structure is utilized a kind of normal linearity memory array, so must keep a large amount of FIFO head and the tail pointers in the hardware.This is a very complicated task, thereby very undesirable.

The problems referred to above are at United States Patent (USP) U.S.Pat.No.5, and 572, thus received data is carried out correct deinterleaving solve by a linear storage array is used with an address generator that is used to generate the read/write address repetitive sequence in 532.Memory array has less relatively scale, only utilizes a memory location that surpasses required number, so that each group corresponding data byte is added different the delay.Here in Shuo Ming the system, B=54, N=216, and M=4.As United States Patent (USP) U.S.Pat.No.5, described in 572,532, need the data byte number of every Frame in fact can divide equally so that the deinterleaver address generator can utilize frame synchronization to be used for synchronously by B.Fig. 3 A diagram is this situation concerning whole VSB modes.

Part II

Figure 15 a that is obtained by Fig. 4 a and Fig. 5 combination among the part I totally illustrates a new TCM transmitter.Be contemplated to multistage VSB digital application in the preferred embodiment of the present invention, but will be understood that, the present invention is comparatively basic in itself, thereby can be applicable to the sending/receiving system of other types, comprises the video system of low resolution and based on the data system of non-video.And, can also adopt other modulation techniques, such as using for example those modulation techniques of quadrature amplitude modulation (QAM).

Shown in Figure 15 a, a data source 110 provides continuous data byte, and it for example can comprise: through the HDTV of overcompression signal, and TV signal or any other digital data signal through overcompression of single-definition.As described below, though data byte there is no need, will preferably dispose by the successive frame form described in the part I, wherein each frame comprises 1 frame synchronization segmentation and 288 data segmentations.Each data sementation comprises 836 2 bit symbols by about 14.14 million code elements/second, chip rate took place.

The data source 110 that a plurality of timing signals also are provided is delivered to a Reed Solomon Coding device 112 with its data byte and is used for the forward error correction coding, delivers to a data byte interleaver 114 more thus.114 pairs of data bytes of this data byte interleaver are resequenced and are reduced the susceptibility of system for the short pulse noise as mentioned above.

The data byte that the process of data byte interleaver 114 outputs interweaves is delivered to a data symbols interleaver 116, provides 2 output bit stream X with chip rate in preferred embodiment ₁, X ₂, each becomes contraposition X ₁, X ₂Corresponding with a data symbols.Specifically, this data symbols interleaver 116 is interleavers (following can the detailed description in detail) of one 9 * 4=36 grouping, and 828 2 bit data code elements of each data sementation are interweaved.

2 bit data code element stream of the un-encoded of data symbols interleaver 116 outputs are delivered to starting (P) code element and segment sync (S) symbol inserter 118 (following can the detailed description in detail), insert the start bit and the segment sync code element of un-encoded on each data sementation relevant position.The start bit of un-encoded, segment sync code element and data symbols are delivered to one 9 road convolution coder 120, are used to be transformed to 3 carry-out bits of every code element as following will further describing.From 9 road convolution coders 120 to start bit and the feedback network of segment sync symbol inserter 118 feedback signal of each convolution coder state this 9 road convolution coder 120 of expression is provided, as will illustrating, the start bit and the segment sync code element of the un-encoded inserted impacted.Because this 9 road convolution coder 120 is characterized in that one 9 symbol delay devices, be to comprise 9 parallel encoders that operate by 1/9 code element clock rate respectively so it is taken as.

The 3 bit code flow filaments that the process convolution mode that the output of 9 road convolution coders 120 manifests is encoded are delivered to a symbol mapper 122, and each 3 bit symbols is mapped to wherein corresponding one of M amplitude or phase level (M=8 in this example).Start bit, segment sync code element and the data symbols through the TCM coding of symbol mapper 122 outputs are delivered to a frame formatter 124, and deliver to a VSB modulator 126 thus, are used for as a plurality of 8 grades of code elements transmission.Can increase by a pilot tone to signal transmitted, so that make the amplitude of each code element scheduled volume of setovering.

Figure 15 b represents 8VSBT (TCM encoder) receiver that Fig. 9 among the part I-Figure 11 combination obtains.The signal that is sent by one comprise with Fig. 1 in the receiver of tuner 16, demodulator 18 and A/D 20 corresponding tuners, demodulator and A/D 128 received.The output of tuner, demodulator and A/D 128 comprises 8 grades of code element stream of a multidigit (8 to 10 of for example every code elements).One data obtain unit 130 and obtain various clock signals and synchronizing signal in the middle of the code element stream that is received.These clock signals and synchronizing signal comprise code element clock, byte clock, segment sync and frame synchronizing signal.The output that data obtain unit 130 deliver to a selector diverter switch 134a/134b (for one make the diverter switch running with comprise a comb filter 132 first handle that path is connected and second handled circuit example embodiment that path connects referring to United States Patent (USP) U.S.Pat.No.5 with this comb filter 132 gets around, 260,793).The output of selector diverter switch 134a/134b is delivered to a frame synchronization code element and is given up circuit 136, is allowing whole other code elements of Frame start bit, segment sync code element and the data symbols of TCM coding (promptly through) will comprise that 836 code elements of the frame synchronization segmentation of each received data frame give up by to one 9 road Viterbi decoder 138 time.VSB decoder 82 is not shown in Figure 15 b for simplicity.But should be understood that this VSB mode ID, also can be called VSB mode sign indicating number here, is detected in the middle of the frame synchronization segmentation before the frame synchronization segmentation is given up unit 136 this frame synchronization segmentation is given up.

The output of 9 road Viterbi decoders 138 comprises start bit, segment sync code element and the data symbols of un-encoded.Thereby the output of 9 road Viterbi decoders 138 comprises contraposition stream X ₁And X ₂Reorganization.Bit stream X ₁And X ₂Deliver to a starting code element and a segment sync code element stripper 140, start bit and segment sync code element are given up, only allow the data symbols of un-encoded be sent to symbol de-interleaver 142.The data byte that 142 pairs of original processes of symbol de-interleaver interweave is recombinated.These are followed by byte deinterleaver 144 deinterleavings through the data byte that interweaves, and the data byte of this process deinterleaving is by Read-Solomon decoder 146 error correction, so that be applied to this receiver remaining part.

This TCM encoding process relates to data symbols interleaver 116, start bit and segment

sync symbol inserter

118,9 road convolution coders 120 and the symbol mapper 122 among Figure 15 a.The particular content of explanation 9 road convolution coders 120 and symbol mapper 122 is useful earlier.This 9 road convolution coder 120 of the functional diagram of Figure 16 (similar to Fig. 7) so for simplicity in this repetition.Input adapter 148 (being coupler) and output adapter 150 (being multiplexer) switch respectively each code element, so that by wherein identical some each code elements that is separated by 9 code element gaps in the multiplexed stream of handling of 9 road convolution coder 120A-120I.

Figure 17 illustrates the detail of same 9 road one of them representative encoder of convolution coder 120A-120I.The convolution coder of Figure 17 comprises a precoder 152 and a lattice structure encoder 154.This precoder 152 comprises a summer and a single symbol delay device Q ₂, with an input position X ₂Precoding is a middle carry-out bit Y ₂And input position X ₁Directly transmit as an interposition Y ₁ Lattice structure encoder 154 comprises a summer and two single symbol delay device Q ₀And Q ₁, with interposition Y ₁And Y ₂Carry out the lattice structure coding and form 3 convolutional encoding code elements.These 3 convolutional encoding code elements are delivered to symbol mapper 122 by output adapter 564, and then output has the code element of corresponding stage in the middle of-7 to+7 respectively.Thereby each 9 road convolution coder 120A-120I receives the input symbols [X of 2 un-encoded ₂X ₁], and export 3 code elements through convolutional encoding.

Should be understood that 9 road convolution coders and each 9 individual encoders shown in Figure 17 among Figure 16 together can be equivalently represented by single encoded device among Figure 18, wherein delay cell Q ₂, Q ₁And Q ₀Each represents one 9 symbol delay devices.Method among Figure 16 and Figure 17 is for system advantage, and especially the explanation for the interactive effect (discussing after a while) of comb filter in the receiver and Viterbi decoder is more useful.But the method for Figure 18 is better concerning making up actual hardware.Two kinds of in fact equivalences of method.For Figure 18, notice that the state that feeds back to start bit and segment sync symbol inserter 118 comprises each 9 symbol delay unit Q ₂, Q ₁And Q ₀Single position in the middle of (3 altogether), these are that maximum duration is in the position in each corresponding 9 symbol delay unit.

The symbol mapped function of being implemented by symbol mapper 122 is shown specifically in Figure 19.This symbol mapped function is identical with the mapping shown in the secondary series among Fig. 4 B basically, and this output stage numerical value is divided equally by 16 only for simplicity.This symbol mapped function make each possible 3 through the code element of convolutional encoding and its respective stages-7 to+7 relevant.

Figure 20 is the combined status transition chart of symbol mapped function among representative convolution coder among Figure 17 and Figure 19.State shown in each circle is to binary condition [Q ₂Q ₁Q ₀] decimal representation.Each branch's mark has the input symbols [X of un-encoded ₁X ₂] with the output symbol level (7 to+7) through the TCM coding of relevant symbol mapper 122 outputs.For instance, the branch of input symbols [00] with un-encoded and relevant output symbol level-7 through the TCM coding is from decimal system state 2, and transition are decimal system state 1.

Start bit and segment sync symbol inserter 118 receive the data symbols of un-encoded from data symbols interleaver 116, and in the relevant position segment sync code element and start bit are inserted in the data flow.Its numerical value of the code element of these insertions depends on the state of that specific convolution coder that code element will import (120A-120I one of them) as will illustrating.As illustrated among the part I, each data sementation comprises 4 segment sync code elements, then is 823 data code elements, then is 4 start bits, then is 5 above data symbols.Segment sync sign indicating number figure must take place to per 836 code elements of the input of frame formatter 124, this yard figure comprises 4 through TCM symbols encoded [+5-5-5+5] at the output of symbol mapper 122.

These segment sync code elements each come between when appropriate with combined 9 road convolution coder 120A-120I of symbol mapper 122 in the different coding device.For make with combined 9 road convolution coder 120A-120I of symbol mapper 122 in encoder export when needed+5 or-5, encoder must be in a particular state.Start bit offers wherein that encoder of 9 road convolution coder 120A-120I, so that be in a state, with this symbol mapper 122, responds the input symbols output+5 or-5 of next un-encoded.As shown in Figure 20, only when this specific convolution coder be in

state

0,2,4 and 6 one of them the time encoder and symbol mapper 122 exportable+5 among 9 road convolution coder 120A-120I, only when this convolution coder be in

state

1,3,5 and 7 one of them the time just exportable-5.For each coder state, Figure 21 illustrates the input start bit and the relevant output start bit through the TCM coding of a un-encoded, then is the input segment sync code element of follow-up un-encoded and the relevant output segment sync code element (± 5) of passing through the TCM coding.

Know that the segment sync code element (± 5) of encoding through TCM is always guided by the start bit in mutually same among 9 road convolution coder 120A-120I.This configuration causes 4 segment sync code element [S through the TCM coding ₀S ₁S ₂S ₃] in each in the middle of the output stream of multiple connection by 4 start bit [P through TCM coding ₀P ₁P ₂P ₃] in a guiding, thereby each start bit such as following sign indicating number figure are depicted as 9 code elements that separate before its corresponding segment sync code element:

…xxxP ₀P ₁P ₂P ₃xxxxxS ₀S ₁S ₂S ₃xxx……

Thereby, in order to generate segment sync waveform through the TCM coding, this start bit and segment sync symbol inserter 118 must be observed wherein corresponding one state of 9 road convolution coder 120A-120I, and insert the segment sync code element of the start bit and the process correct coding of process correct coding shown in Figure 21 according to observed state.For instance, if being in

decimal system state

2,9 road convolution coder 120C need just insert the then start bit 01 of the un-encoded of the segment sync code element 11 of un-encoded to particular fragments sync symbols output+5 to convolution coder 120C.This receiver will utilize the segment sync oscillogram through TCM coding (this oscillogram is shown in United States Patent (USP) U.S.Pat.No.5,416,524 in) of synchronous usefulness, will then give up this start bit and segment sync code element after the TCM decoding.

Should note, in order to export a segment sync code element S=+5 through coding, each in the middle of 8 possible initial TCM coder state will cause before coded segment sync code element S=+5 different in the middle of 8 possible start bits (P) through coding of output one.Make its probability of whole coder state equate, then whole 8 its probability of start bit through coding also equate.So, through the start bit P of coding ₀P ₁P ₂P ₃To be at random.The start bit that kindred circumstances is encoded through the process of the segment sync code element S=-5 of coding for guiding one is genuine.

The data symbols interleaver 116 that comprises input adapter 154 and an output adapter 156 as shown in figure 22, and is identical with data symbols interleaver 42 shown in Figure 6.The running of data symbols interleaver 116 and part I are in conjunction with illustrated identical of Fig. 6.Such as previously described, data byte comprises many 2 bit symbols, in the following order input data bitstream unit interleaver 116:

[0 ₀0 ₁0 ₂0 ₃][1 ₀1 ₁1 ₂1 ₃][2 ₀2 ₁2 ₂2 ₃]……[206 ₀206 ₁206 ₂206 ₃]

Data symbols interleaver 116 is the dateout code element in the following order:

…0 ₀1 ₀2 ₀3 ₀4 ₀5 ₀6 ₀7 ₀8 ₀0 ₁1 ₁2 ₁3 ₁…7 ₃8 ₃9 ₀10 ₀…17 ₀9 ₁10 ₁…

206 ₂198 ₃199 ₃200 ₃201 ₃202 ₃203 ₃204 ₃205 ₃206 ₃…

The running profile of 9 road convolution coders 120 of Figure 16 was discussed with reference to Fig. 7 in part I.As illustrated in conjunction with Fig. 7, the input adapter 54 and the output adapter 56 of 9 road convolution coders 44 switch each code element together.One circulation may be defined as 9 steps of input and output adapter 54 and 56.If input and output adapter 54 and 56 both be in the initial apical position of Frame first data sementation, then input and output adapter 54 will be in itself and the initial apical position that conforms to of segmentation in 9 segmentations (836 circulations) afterwards once more with 56.Because every frame has 288 data segmentations, and 288/9=32 is integer, so input and output adapter 54 and 56 will be in the initial apical position of its each subsequent data frame 24.This running can help the hardware designs of transmitter and receiver.The code element ordering that passes in and out 9 road lattice structure encoders does not change.The running of Figure 16 configuration is practically identical.No matter any situation, the code element ordering does not change because of 9 road convolution coders 120.Thereby the code element that comes from the output adapter 150 of 9 road convolution coders 120 sorts as follows:

Data symbols interleaver 116 its purposes are, by a sequence arrangement data symbols so that with those data symbols of a given syllable dependent connection by one identical (with Viterbi decoder identical in the receiver) in the middle of 9 road convolution coder 120A-120I.This " byte packet " finds that its advantage is to suppress some damage.If given Viterbi decoder have can't error correction mistake, just be tending towards making this mistake to expand to subsequent symbol.Advance identical Viterbi decoder if the code element of identical bytes is packaged, just have the influence that byte still less is subjected to the mistake expansion on average.

It should be noted that and to stop original " byte packet " of last 5 the data code elements of each data sementation in the middle of 4 start bits insertion code element stream.Lack should byte packet do not have statistical conspicuousness, and for performance, the influence that can survey should not arranged.Expressing and the corresponding code element of specified byte input 9 road convolution coder 120A-120I on one 9 segmentations (836 circulations) span how among Figure 23.Which code element each 9 code elements row then illustrates is imported this 9 road convolution coder 120A-120I in a circulation.

Symbol mapper 122 will be exported to frame formatter 124 through start bit, segment sync code element and the data symbols of TCM coding, insert a frame synchronization segmentation in each 288 data segmentation front of group as hereinafter described.

Symbol mapper 122 has two attributes paying special attention to.At first, shown in mapping function among Figure 19,8 symbol level are divided into 4 subclass a, b, c and d, and wherein each subclass is by carry-out bit Z ₁Z ₀Particular state identify.Like this, Z ₁Z ₀=00 selects symbol subset d, Z ₁Z ₀=01 selects symbol subset c, Z ₁Z ₀=10 select symbol subset b, and Z ₁Z ₀=11 select symbol subset a.In each subclass, corresponding symbol amplitude is with the amplitude difference of 8 unit.Secondly, continuous symbol level to (7 ,-5), (3 ,-1), (+1 ,+3) and (+5 ,+7) by carry-out bit Z ₂Z ₁Common state select.Like this, for instance, carry-out bit Z ₂Z ₁=00 selects two symbol amplitude levels-7 and-5 etc.The above-mentioned attribute of symbol mapper 122 will be as below will more describing in detail, and both are useful making aspect the reduction of receiver complexity.

Thereby, it should be noted that and can adopt carry-out bit Z ₁Z ₀Select a symbol subset, adopt carry-out bit Z ₂Select a code element of this selection subsets.It is relevant with a 8VSB system that this configuration has illustrated, 3 Z in this system ₂Z ₁Z ₀Be used for selecting a subclass and this selection subsets one code element.A kind of like this configuration can be summarized, the position Z of any number can be adopted _NSelect the code element of a subclass and this selection subsets.In this case, can adopt carry-out bit Z ₁Z ₀Select a symbol subset, adopt carry-out bit Z ₂-Z _NSelect a code element of this selection subsets.

Figure 25 is the status transition chart of lattice structure encoder 154 among Figure 17 that the status change table obtains from Figure 24.The status transition chart of Figure 25 and the status change of Figure 24 are expressed 4 states and the various transition therebetween of lattice structure encoder.Specifically, each state has two parallel branches, and each branch extends to equal state or another state.Mark has input position Y ₂Y ₁Branch cause symbol mapper 122 status changes, therefore and export R.As below will further specifying, this state diagram is used in design one optimization PRML sequencal estimation (MLSE) Viterbi decoder in the receiver, as known in the art, is used to restore contraposition Y ₂And Y ₁Estimation.

Figure 26, Figure 27 and Figure 28 specifically with reference to comb filter 132 and 9 road Viterbi decoders 138, illustrate decoding of the present invention in more detail.Shown in Figure 15 b, come 8 grades of process TCM symbols encoded values of self-tuner, demodulator and A/D 128 to deliver to data acquisition unit 130, as required various synchronizing signals and clock are offered other parts of receiver.Data obtain the output of unit 130 and deliver to selector diverter switch 134a/134b, or are fed to comb filter 132, or comb filter is got around.As United States Patent (USP) U.S.Pat.No.5,260,793 disclosed like that, exist (by the comb filter control signal among Figure 15 b) that comb filter 132 can respond interference signal is switched this signal path of turnover.

Comb filter 132 is one to comprise the filter of linear summer 158 and 9 symbol delay unit 160 as shown in figure 26.This comb filter 132 is 15 grades of code elements with 8 grades of symbol transformations.This comb filter 132 can by 9 code element gaps will more early take place institute's receiving symbol and each institute's receiving symbol reduce the co-channel interference of PAL operationally and (comb filter more fully illustrated referring to United States Patent (USP) U.S.Pat.No.5 in the Calais mutually, 087,975).

The output of selector diverter switch 134a/134b (having omitted the selector diverter switch 134a/134b among Figure 15 b for convenience's sake in the middle of Figure 26, Figure 27 and Figure 28) is delivered to the frame synchronization code element and is given up unit 136, intercepts and gives up 836 code elements in each frame synchronization segmentation.Remaining start bit, segment sync code element and data symbols through the TCM coding are all delivered to 9 road Viterbi decoders 138.

United States Patent (USP) U.S.Pat.No.5,600,677 disclose, and a N road can be as 9 road Viterbi decoders 138 in Figure 15 b receiver by a N road Viterbi decoder decoding through TCM symbols encoded stream.N road Viterbi decoder shown in Figure 26, Figure 27 and Figure 28, wherein N=9.This patent further discloses, Viterbi decoder in the receiver can have 2 kinds of function modes that the comb filter control signal is controlled, a kind of is to have first of comb filter 132 to handle the used mode (Figure 26 and Figure 27) of path, and a kind of is the mode (Figure 28) that comb filter 132 is got around.

The combination of comb filter 132 and 9 road Viterbi decoders 138 can be shown by 2 equivalent electric circuits of Figure 26 and Figure 27.Because this 9 symbol delay device 160, comb filter 132 its effects in input adapter 162 shown in Figure 26 (being coupler) upstream are equivalent to and are in input adapter 162 downstreams and 9 comb filter 164A-164I shown in Figure 27, and wherein each comb filter 164A-164I has a summer 168 and a single symbol delay device 170.Each comb filter 164A-164I presents among 9 Viterbi decoder 166A-166I corresponding one.From the equivalence of Figure 26 and circuit shown in Figure 27 as can be known of the following fact: for two kinds of situations, those code elements that separate 9 code element gaps in the code element stream are by linear summer (the 158 or 168) combination in the comb filter (42 or 164A-164I).Should be understood that Figure 26 represents a more possible hardware embodiment, the equivalent electric circuit among Figure 27 then more is clearly shown that the effect of comb filter aspect Veterbi decoding.

As shown in figure 28, if comb filter 132 is got around, each the Viterbi decoder 166A-166I in 9 road Viterbi decoders 138 can be that one 4 corresponding one the state optimization MLSE decoders to back encoder 174A-174I (being discussed later) are presented in its output.As shown in figure 27, if comb filter 132 is access in, each Viterbi decoder 166A-166I in 9 road Viterbi decoders 138 can be that one 16 corresponding one the state optimization MLSE decoders to back encoder 174A-174I (the clear back encoder 174A-174I that shows in Figure 27 for convenience's sake) are presented in its output, or does not have one 8 state suboptimization decoders of back encoder.Each Viterbi decoder, state are increased to 8 or 16 from 4, are the effects of comb filter 132 as will be illustrated.

The frame synchronization code element is given up 836 frame synchronization code elements that intercept in the unit 136 and give up and is not delivered to 9 road Viterbi decoders 138.Remaining start bit, segment sync code element and data symbols are delivered to wherein corresponding one of Viterbi decoder 166A-166I respectively.Will know, most of initial data byte of data source 100 by Viterbi decoder 166A-166I wherein corresponding one as a cell processing.For instance, by code element [0 ₀0 ₁0 ₂0 ₃] data byte of expression handles by Viterbi decoder 166E (referring to Figure 23)." byte packet " in the receiver will meet the byte packet of transmitter shown in Figure 23.

Consider the situation that comb filter 132 is got around as shown in figure 28 earlier.Each is optimized MLSE Viterbi decoder 166A-166I and can comprise by speed fs/9 (wherein fs is the code element clock) running and according to the practically identical device of the state diagram programming of Figure 24 among Figure 28, so that as known in the art, the MLSE Veterbi decoding that is optimized reduces contraposition Y ₂And Y ₁Estimation.Specifically, each is optimized MLSE Viterbi decoder 166A-166I and adopts the ROM through suitable programmed to be programmed for to generate 4 branch metrics usually, and each represents poor between two subclass of institute's receiving symbol level (for example digital value of a 8-10 position) and each symbol subset a, b, c and d closest value in worthwhile.

Under this situation, Figure 29 illustrates the Viterbi decoder that a LSI logical circuit company makes, and this decoder can be programmed for the function of carrying out each optimization MLSE Viterbi decoder 166A-166I among Figure 28.Decoder shown in Figure 29 comprises a branch metric maker ROM180, and response institute receiving symbol generates 4 branch metrics and delivers to an addition and relatively select (ACS) unit 182.These ACS unit 182 two-way flux of delivering to are measured memory storing 184, also offer a traceback memory 186.In a word, ACS unit 182 is measured the last path of being stored in the memory storing 184 with branch metric maker ROM180 and path and is measured addition and generate new path and measure.ACS unit 182 then compares the path of equal state emission to be measured, and selects those minimum paths to measure and is used for storage.Traceback memory 186 is used to select an existence path operationally after having manifested some branches, and generates producing the position Y of this existence path ₂And Y ₁Estimation.

Will wander back to, ignore 152 pairs of incoming bit stream roles of precoder in the middle of the above-mentioned analysis.After this will further describe the function of precoder 152 in detail, but just be enough to now recognize, input position X ₂Running and position Y because of the precoder 152 of carrying out Modulo-two operation ₂Different.Shown in Figure 28 each is optimized its output of MLSE Viterbi decoder 166A-166I and is only comprised contraposition Y ₂Estimation, do not comprise an input position X ₂Estimation.Therefore, adopt complementary mould 2 back encoder 174A-174I to reduce respectively in the receiver to optimizing the input position X that MLSE Viterbi decoder 166A-166I comes ₁And X ₂Estimation.

Each back encoder 174A-174I comprises an input position Y ₁With carry-out bit X ₁Between direct path, and carry-out bit Y ₂Directly deliver to an input of a modulo 2 adder 176 and deliver to the feed forward circuit of these modulo 2 adder 176 second inputs by a single symbol delay unit 178.The output of modulo 2 adder 176 comprises input position X ₂Estimation.At last, the next position X of back encoder 174A-174I through decoding ₁, X ₂Become the bit stream that interweaves once crossing by output adapter 172 multiple connections as shown in figure 28.

In the present invention's one alternate embodiment, each optimization MLSE Viterbi decoder 166A-166I can be substituted by the amplitude limiter shown in Figure 30 188 among Figure 28, so that provide the receiver that reduce cost by higher relatively S/N than the occasion that characterizes at received signal.Higher relatively S/N ratio is the situation of wire transmission normally, at this moment demonstrates the S/N ratio better than terrestrial transmission usually.So traded off aspect TCM coding gain and receiver complexity and the cost.As shown in figure 30, amplitude limiter 188 is characterized in that, has 3 limiting stages (4,0 and+4).Its progression of the code element that is received is also more negative than-4, will be by amplitude limiter 188 as position Y ₂Y ₁=00 decodes, and the level between-4 and 0 is as position Y ₂Y ₁=01 decodes, 0 and+level between 4 is as a position Y ₂Y ₁=10 decode, than+4 also positive level conduct position Y ₂Y ₁=11 decode.

As discussed previously, position Y ₂Y ₁Be transformed to contraposition X by wherein corresponding one of back encoder 174A-174I ₂X ₁Estimation.Shown in the mapping function as shown in figure 19, know because as previously mentioned continuously symbol level by every Z ₂Z ₁Common value is represented, so 188 pairs of code elements that received of amplitude limiter are carried out suitable decoding.So this embodiment of the invention has been implemented one 4 grades of sending/receiving systems with regard to effect, the equivalent bit rate as 8 grades of TCM systems is provided, but has relatively poor S/N performance because of the TCM coding gain of being unrealized.

To discuss now carry out the situation of Veterbi decoding by the code element of comb filter 132.Though comb filter 132 has the ideal effect that reduces the co-channel interference of NTSC, utilizing optimization MLSE Veterbi decoding to come also original position X ₁And X ₂Occasion also increased the complexity (for example referring to Figure 27) of optimizing MLSE Viterbi decoder 166A-166I.Specifically, optimize the MLSE Viterbi decoder and must not only consider coder state, and consider the state of the single symbol delay device of connected specific comb filter 164A-164I.Because have 4 coder state and 4 kinds of possible methods to import each state (4 kinds of possibility states that promptly each state of lattice structure encoder 154 among Figure 17 had single symbol delay device 170), so optimal decoder must be handled the lattice structure of one 16 states.In addition, in view of only there being 2 branches to import each decoder states under the situation that does not have comb filter 132, this decoder must be responsible for importing 4 branches of each state.

A kind of like this 16 state decoders are shown among Figure 31, and complicated in essence but its design is direct relatively leading.Specifically, the function of decoder and similar (thereby adopting identical with reference to label) shown in Figure 29 are because must generate 15 branch metrics but not just now 4, so its complexity increases greatly.This branch metric is represented each of institute's receiving symbol level and comb filter 132 outputs poor (i.e. the linear combination of 8 grades of code elements provides 15 possible output levels) between may 15 structure image positions.

Express one according to technology of the present invention among Figure 32, be used to reduce being used for from the output of comb filter 164A-164I original position X also ₁And X ₂Its complexity of Viterbi decoder 166A-166I, thereby reduce its cost.By (with precoder 152) contraposition X as shown in figure 17 ₂Carry out this simplification of precoding, realize by in the lattice structure figure formation process that forms the decoder basis, ignoring some state information of delivering to Viterbi decoder from the single symbol delay device 170 of specific comb filter 164A-164I.Specifically, as below will further specifying, by this aspect of the present invention, the simplification of decoding be by only consider to 8 of the single symbol delay device 170 of specific comb filter 164A-164I may states wherein the information that identifies of subclass a, b, c and d (referring to the mapping function among Figure 19) realize.If the output of single symbol delay device 170 is by representing that with reference to alphabetical V the assembled state of this encoder and comb filter can be expressed as Q ₁(n) Q ₀(n) V ₁V ₀(n), V wherein ₁V ₀(n) equal subclass Z ₁Z ₀(n-1).That is to say that the state of single symbol delay device 170 is represented by the subclass of last code element.

Shown in table among Figure 32, the encoder of this combination and state (only utilizing subset information to represent the state of the single symbol delay device 170) Q of comb filter when time n is shown in first tabulation ₁Q ₀V ₁V ₀As shown in the figure, following 8 possible states are arranged: 0000,0010,0100,0110,1001,1011,1101 and 1111.In each above-mentioned state, Q ₁=V ₀Above-mentioned 8 states come from the state Q that provides in Figure 24 table in the lattice structure encoder 154 ₁Q ₀Last 2 row and one of them the V that is associated of single symbol delay device 170 output V of random time (n+1) comb filter 164A-164I (Figure 27) ₁V ₀Subclass.Will note the V of time (n+1) ₁V ₀The carry-out bit Z of subclass and time n ₁Z ₀Identical (referring to the 3rd row in Figure 24 table).Its each state Q of the encoder of this combination and comb filter ₁Q ₀V ₁V ₀In Figure 32 table, list input position X 2 times ₁Each probable value is listed once (referring to the 3rd row in Figure 32 table).The 4th row are to each encoder/channel state and input position X in Figure 32 table ₁Each is worth the subclass Z of equal express time n ₁Z ₀According to Z ₁=X ₁And Z ₀=Q ₀These relations obtain above-mentioned value.The V of the 1st row in the table ₁V ₀The Z of the 4th row in subclass and the table ₁Z ₀Subclass by mapping function among Figure 19 and the subclass identifier (a-d) shown in the 2nd row and the 5th are listed as in Figure 32 table respectively identify.

Wherein corresponding one of Viterbi decoder 166A-166I is delivered among Figure 27 in the output of each comb filter 164A-164I neutral line summer 168.This output is identified by letter U in Figure 32, and comprises that institute's receiving symbol value adds last symbol value.This U value by subclass identifier (a-d) in Figure 32 table the 6th row as Z subclass Z ₁Z ₀With V subclass V ₁V ₀And the expression.Thereby U subclass and the collection of the 1st line time n is (d+d) in the table for instance, and the 2nd row is (b+d), and the rest may be inferred.

Among Figure 33, the probable value of U subclass and collection is by each V subclass (a, b, c and d) and each Z subclass (a, b, c and d) addition are obtained.Specifically, each possible Z subclass is identified by the corresponding blacking circle of level with respective subset along the top of Figure 33.For instance, subclass a comprises in the middle of 8 grades-1 grade and+7 grades, and subclass b comprises-3 grades and+5 grades, and the rest may be inferred.Equally, each possible V subclass then identifies along the left frame of Figure 33.Figure 33 inside illustrates the result who each V subclass and each Z subclass is obtained mutually U subclass and collection (U=Z+V).For example, by-1 of-1 and+7 a subclass level of Z subclass and V subclass obtained U subclass and collection (a+a) (referring to last column in Figure 32 table) with+7 a subclass level addition, shown in the upper left corner, Figure 33 inside, provide+14 ,+6 and-2 these 3 grades.Equally, obtain U subclass and collection (a+b) (referring to eighth row in Figure 32 table and the 12nd capable) by-1 and+7 a subclass level addition with-3 and+5 b subclass level of Z subclass and V subclass, provide as shown in the figure+12 ,+4 and-4 these 3 grades, the rest may be inferred.If signal transmitted adds a pilot tone, the amplitude level in the set shown in Figure 33 (and coset shown in Figure 34 of discussing below) is that the center presents symmetry with 0 grade no longer, and this is because pilot tone makes the amplitude of each code element specified quantity of having setovered.

To the close examination of 16 U subclass shown in Figure 33 and collection, show each all belong to 7 common subclass that after this are called coset and collection one of them.Above-mentioned 7 cosets shown in Figure 34 are listed as coset A (U subclass and collection b+c and a+d), B1 (U subclass and collection c+c and b+d), B2 (U subclass and collection a+a), C1 (U subclass and collection c+d), C2 (U subclass and collection a+b), D1 (U subclass and collection b+d) and D2 (U subclass and collection b+d and a+c).This coset of each U subclass and collection and in Figure 32 table the 7th row shown in.Will be noted that, but each coset comprises wherein 3 of 15 energy levels.

Show the state Q of encoder/comb filter of time (n+1) with the last tabulation in the corresponding Figure 32 table of last 2 row in Figure 25 table ₁Q ₀V ₁V ₀This table the 1 and terminal column can be used for constituting the lattice structure status transition chart of one combined encoder/comb filter.This lattice structure status change is illustrated in Figure 35, is obtained by Figure 32.Among Figure 35, no matter V ₀Because it and Q ₁It is repetition.Lattice structure status transition chart thereby comprise 8 states of time n, 2 branches are from each state.Each branch's mark has input position X ₁And the U coset A, B1, B2, C1, C2, D1 and the D2 that are associated with corresponding transition.Now can adopt lattice structure (to each Viterbi decoder 166A-166I) among Figure 35 that a basis that reduces the Viterbi decoder of complexity is provided, so that estimate an input position X according to the output U of the linear summer 168 of this single symbol delay device equivalence comb filter 164A-164I ₁

Comprise among Figure 31 that this decoder of optimizing Viterbi decoder one alternate embodiment can take the form of Viterbi decoder shown in Figure 36.Be used for implementing this Viterbi decoder device can to used similar of the decoder of Figure 29 and Figure 31, thereby comprise that branch metric maker ROM180, ACS unit 182, path measure memory storing 184 and traceback memory 186.

Among Figure 36 under the situation of decoder, this branch metric maker ROM180 is programmed for and generates 7 branch metrics, each branch metric represent between nearest in central each 3 level of significations of one of them symbol level U and 7 coset A, B1, B2, C1, C2, D1 and the D2 of linear summer 168 outputs of comb filter 164A-164I one Euclidean distance square.For instance, suppose U level=(6), resulting 7 branch metrics are just as follows: A=2 ²=4; B1=4 ²=16; B2=4 ²=16; C1=2 ²=4; C2=2 ²=4; D1=0; And D2=0.According to the lattice structure figure among above-mentioned branch metric and Figure 35, the contraposition X that decoder provides the existence path that carries out from decoder to learn in the middle of judging ₁Estimation and the identification of relevant coset (COSET).

But also need input position X ₂Estimation is provided.This estimation can respond the coset that Viterbi decoder provided among Figure 36 (COSET) information and make.By in the path of input position X2, providing precoder 152 to help contraposition X as shown in figure 17 ₂Carry out the ability of this estimation.Specifically, will know this precoder 152 is configured to need only whenever an input position X ₂(n)=1, the corresponding carry-out bit Y of precoder ₂(n) be different from last carry-out bit Y ₂(n-1).That is to say, if Y ₂(n)  Y ₂(n-1), X then ₂(n)=1.And, if X ₂(n)=0, then corresponding carry-out bit Y ₂(n) will equal last carry-out bit Y ₂(n-1).That is to say, if Y ₂(n)=Y ₂(n-1), X then ₂(n)=0.In addition, will be noted that, work as Z with reference to mapping function among Figure 19 ₂(be Y ₂)=1 o'clock provides positive level code element, and works as Z ₂=Y ₂Then provided negative level code element at=0 o'clock.

Above-mentioned characteristic is used for estimating as shown in figure 37 an X ₂The symbol level U of linear summer 168 outputs of comb filter 164A-164I is added on a plurality of (promptly 7) amplitude limiter 194 one of them input by a delayer 192 (being chosen for the delay of coupling Viterbi decoder 166A-166I).This COSET identification signal of Viterbi decoder 166A-166I output is added to amplitude limiter 194 wherein on the 2nd input.Contraposition X ₂Estimation be by X on the throne by amplitude limiter 194 ₂Be decoded as U symbol level one of them peripheral grade (for example coset A+8 or-8 grades) of coset A, the B1, B2, C1, C2, D1 and the D2 that are discerned of the COSET identification signal of more approaching corresponding Viterbi decoder 166A-166I output whether of judging comb filter 164A-164I under 1 the situation, or X on the throne ₂Whether the more approaching intergrade (for example 0 of coset A grade) of discerning coset manifests to be decoded as the U symbol level of judging comb filter 164A-164I under 0 the situation.Above-mentioned explanation is promptly only worked as the continuous Y of precoder 152 outputs based on a kind of like this fact ₂The position is by numerical value Y ₂And Y (n)=1 ₂When (n-1)=0 characterizing the result be each coset on the occasion of peripheral level (for example coset A+8), only work as continuous Y ₂The position has numerical value Y ₂Or Y (n)=0 ₂(n-1)=1 o'clock result is the peripheral level of negative value (for example-8 of coset A) of each coset, only as continuous Y ₂The position is by having numerical value Y ₂And Y (n)=1 ₂Or numerical value Y (n-1)=1 ₂And Y (n)=0 ₂(n-1)=0 o'clock result is the intergrade (for example 0 of coset A) of each coset.Two kinds of situations after above-mentioned the leaning on, X ₂(n)=0 (because of Y ₂(n)=Y ₂(n-1)).

Will be understood that at last, when the output of comb filter 132 being handled, import position X with Viterbi decoder ₂Path in comprise that precoder 152 (Figure 17) need be at estimated position X ₂Path in conjunction with the back encoder 190 (Figure 31) of a complementation.Because estimated position X ₂Be directly to produce, so do not need complementary back encoder among Figure 37 under this circuit situation.

Referring again to 9 road Viterbi decoders 138 (similar) shown at present among Figure 15 b and Figure 38, decoded through start bit, segment sync code element and the data symbols of TCM coding here with Figure 12.The output of 9 road Viterbi decoders 138 comprises start bit, segment sync code element and the data symbols of the un-encoded of delivering to start bit and segment sync code element stripper 140.Start bit and segment sync code element stripper 140 are given up the start bit and the segment sync code element of un-encoded, only allow the data symbols of un-encoded send symbol de-interleaver 142 to.This symbol de-interleaver 142 is one 9 * 4 grouping deinterleavers, is used for byte is got back in the data symbols formation of un-encoded.All running comes synchronously by frame synchronization and segment sync.

With reference to Figure 12 timing to 9 road Viterbi decoders 138 was discussed among Figure 38 among the part I.The code element ordering that passes in and out this decoder 138 does not change.Thereby decoder 138 is exported the code element of un-encoded by following ordering:

…S ₀S ₁S ₂S ₃0 ₀1 ₀2 ₀3 ₀4 ₀5 ₀6 ₀7 ₀8 ₀0 ₁1 ₁2 ₁3 ₁……

After by start bit and segment sync code element stripper 140 (start bit and segment sync code element stripper 92 with reference to Figure 11 in part I were discussed) the segment sync code element of the start bit of un-encoded and un-encoded being eliminated, just provide following ordering:

206 ₂198 ₃199 ₃200 ₃201 ₃202 ₃203 ₃204 ₃205 ₃206 ₃…

Symbol de-interleaver 142 shown in Figure 39 comprises input adapter 200 and output adapter 202.The running of symbol de-interleaver 142 in part I with reference to Figure 13 in symbol de-interleaver 94 obtain discussing.The code element ordering of coming from symbol de-interleaver 142 is as follows:

So far only illustrated that the frame synchronization segmentation is inserted into code element stream by the frame formatter 124 in Figure 15 a transmitter, and illustrated that the frame synchronization segmentation gives up unit 136 by the frame synchronization code element in Figure 15 b receiver and give up.Processing to the frame synchronization segmentation will be described in transmitter and the receiver now.Here frame synchronization segmental structure of Jie Shiing and ATSC digital television standard and United States Patent (USP) U.S.Pat.No.5, that is discussed in 619,269 is very similar.Receiver utilize frame synchronization segmentation specified data frame start position and VSB transmission means (referring to United States Patent (USP) U.S.Pat.No.5,745,528 and upper part I in discussion).The frame synchronization segmentation is included in 836 code elements that 288 data segmentations of each group are inserted in the code element stream by frame formatter 34 before.As shown above, this frame synchronization segmental structure is:

[S ₀S ₁S ₂S ₃] be to comprise+4 2 grades of code elements of 5-5-5+5 segment sync waveform.The PN sequence then be comprise with the ATSC digital television standard in 700 2 grades of code elements of identical PN sequence.The VSB mode is encoded and is comprised 24 2 grades of code elements, and illustrates in part I.Ensuing 99 code elements are 2 grades of not regulation code elements.Last 9 code elements of frame synchronization segmentation are 8 grades of code element [P ₀P ₁P ₂P ₃Ddddd], be its last 9 repetitions of data symbols of guiding frame synchronization segmentation through the TCM symbols encoded.The TCM to the frame synchronization code element does not encode or Reed Solomon Coding.Should be understood that last 9 frame synchronization code elements (repetition symbols) during last segmentation through TCM coding.

As shown in figure 26, comb filter 132 receives whole code elements as input.The output of comb filter 132 is given up unit 136 by the frame synchronization code element and is given up during the frame synchronization segmentation of 836 code elements, input adapter 162 and output adapter 172 do not switch.Because the last repetition symbols of frame synchronization segmentation, initial 9 code elements of first data sementation after this frame synchronization segmentation by comb filter 132 effectively with last 9 grouping of bits of former frame final data segmentation together.According to said method, comb filter 132 does not exist like that with regard to the picture frame synchronous segmenting and works, thereby filter 132 is only to through the running of TCM symbols encoded.It is required that this running is played due effect for above-mentioned comb shape/Viterbi combination decoding.

Describe the present invention with regard to the VSB digital television system above.But it will be appreciated that the present invention can be used for such as QAM and this class other system of QPSK system.Thereby will be understood that the present invention is only limited to the qualification of claim.

Claims

1. receiver, it is characterized in that, be used for the digital VSB signal that comprises start bit, segment sync code element and data symbols is received the decode, wherein said start bit, segment sync code element and data symbols are the multistage code elements through a lattice structure encoder encodes, wherein the corresponding segment sync symbols in the middle of each described start bit and the described segment sync code element is combined to generate an output segment sync code element with a predetermined value in described lattice structure encoder, and wherein said receiver comprises:

One tuner, be tuned to a selected channel; And

2. receiver as claimed in claim 1 is characterized in that, described lattice structure decoder is one 9 road lattice structure decoder.

3. receiver as claimed in claim 1 is characterized in that, described lattice structure decoder generates each branch metric, and determines the every of each start bit that receives, segment sync code element and data symbols according to described each branch metric.

4. receiver as claimed in claim 3, it is characterized in that, described lattice structure decoder generates 4 branch metrics, and wherein said lattice structure decoder is determined corresponding with each start bit that is received, segment sync code element and data symbols every according to described 4 branch metrics.

5. receiver as claimed in claim 4 is characterized in that, described everybody be estimated position Y ₁And Y ₂, wherein said lattice structure decoder comprises that one is configured to according to described estimated position Y ₁And Y ₂Generate every X ₁And X ₂Back encoder.

6. receiver as claimed in claim 3, it is characterized in that, described lattice structure decoder generates 15 branch metrics, and wherein said lattice structure decoder is determined corresponding with each start bit that is received, segment sync code element and data symbols every according to described 15 branch metrics.

7. receiver as claimed in claim 6 is characterized in that, described everybody be estimated position Y ₁And Y ₂, wherein said lattice structure decoder comprises that one is configured to according to described estimated position Y ₁And Y ₂Generate every X ₁And X ₂Back encoder.

8. receiver as claimed in claim 1 is characterized in that, the described start bit of described lattice structure decoder processes, segment sync code element and data symbols are to generate a coset identification signal.

9. receiver as claimed in claim 8, it is characterized in that, described each start bit that is received of lattice structure decoder decode, the segment sync code element, and first of data symbols, and wherein said lattice structure decoder is by selecting a central limiting stage set of a plurality of limiting stage set to respond described coset identification signal, and by described selected limiting stage set is imposed on the start bit that each receives, the segment sync code element, and data symbols, the start bit that each received of decoding, the segment sync code element, and second of data symbols.

10. receiver as claimed in claim 9, it is characterized in that, the characteristics of described lattice structure decoder are a decoding delay device, wherein, described receiver also comprises a delay element of an input end of described a plurality of limiting stage set, and wherein said delay element is with an input end that postpones to be added to the described a plurality of limiting stage set that are complementary with the described decoding delay device that with described lattice structure decoder is characteristics.

11. receiver as claimed in claim 1, it is characterized in that, but each described start bit, described segment sync code element and described data symbols have one with one of them corresponding level of a plurality of energy levels, wherein said lattice structure decoder is decoded to described start bit, described segment sync code element and described data symbols according to each coset, but wherein each coset comprise one with the corresponding different sets at different levels of described energy level of described start bit, described segment sync code element and described data symbols.

12. receiver as claimed in claim 11 is characterized in that, only has 7 cosets to be used for described start bit, described segment sync code element and described data symbols are decoded by described lattice structure decoder.

13. receiver as claimed in claim 11 is characterized in that, described lattice structure decoder comprises one on the occasion of comb filter.

14. receiver as claimed in claim 11 is characterized in that, each coset in the described coset only comprises 3 uniformly-spaced levels.