CN107910271A - Power semiconductor and its manufacture method - Google Patents
Power semiconductor and its manufacture method Download PDFInfo
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- CN107910271A CN107910271A CN201711148755.6A CN201711148755A CN107910271A CN 107910271 A CN107910271 A CN 107910271A CN 201711148755 A CN201711148755 A CN 201711148755A CN 107910271 A CN107910271 A CN 107910271A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
This application discloses power semiconductor and its manufacture method.This method includes：Multiple grooves are formed in the semiconductor substrate, and the multiple groove includes the first groove of first size and the second groove of the second size, and the first size is more than second size；Splitting bar structure is formed in the first groove；Grid wiring is formed in the second groove, the grid wiring is connected with grid conductor；In the Semiconductor substrate Zhong Ti areas；Source region is formed in the body area；And formation source electrode and gate electrode, the source electrode are electrically connected with the source region and the shielded conductor, the gate electrode is electrically connected with the grid wiring.This method utilizes the filling effect of different dimensioned trenches, while forms grid conductor and grid wiring, so as to simplify technique, reduces manufacture cost.
Description
Technical field
The present invention relates to technical field of electronic devices, more particularly, to power semiconductor and its manufacture method.
Background technology
Power semiconductor is also known as power electronic devices, including power diode, thyristor, VDMOS (vertical double expansions
Dispersed metallic oxide semiconductor) field-effect transistor, LDMOS (lateral diffusion metal oxide semiconductor) field-effect transistors with
And IGBT (insulated gate bipolar transistor) etc..VDMOS field-effect transistors are included in the upper shape of apparent surface of Semiconductor substrate
Into source region and drain region, in the on-state, longitudinal flow of the electric current mainly along Semiconductor substrate.
In the high frequency of power semiconductor uses, lower conduction loss and switching loss are evaluation device performances
Important indicator.On the basis of VDMOS field-effect transistors, further develop groove type MOS field-effect transistor, wherein,
Grid conductor is formed in the trench, and gate-dielectric is formed on trenched side-wall to separate grid conductor and semiconductor layer, so that
Raceway groove is formed in the semiconductor layer along the direction of trenched side-wall.Groove (Trench) technique from level by raceway groove due to becoming vertical
Directly, the influence of planar structure parasitism JFET resistance is eliminated, is substantially reduced cellular size.It is close to increase primitive unit cell on this basis
Degree, improves the overall width of unit area chip interior raceway groove, it is possible to so that channel width-over-length ratio increase of the device on unit silicon chip
So that electric current increase, conducting resistance decline and relevant parameter is optimized, realize smaller size of tube core and possess bigger
Power and high performance target, therefore trench process is more and more applies in novel power semiconductor.
However, with the raising of cell density, electrode resistance can increase, and switching loss accordingly increases, and gate leakage capacitance Cgd is straight
Connect the switching characteristic for being related to device.In order to reduce gate leakage capacitance Cgd, division gate groove (Split Gate are further developed
Trench, is abbreviated as SGT) type power semiconductor, wherein, grid conductor extends to drift region, while grid conductor and leakage
Separated between pole using thick-oxide, so as to reduce gate leakage capacitance Cgd, improve switching speed, reduce switching loss.With
This shielded conductor below grid conductor and is connected with source electrode at the same time, and common ground connection, puts down so as to introduce electric charge
Weigh effect, has reduction surface field (Reduced Surface Field, abbreviation in the vertical direction of power semiconductor
For RESURF) effect, further reduces conducting resistance Rdson, so as to reduce conduction loss.
Cutting for the manufacture method key step of SGT power semiconductors according to prior art is shown respectively in Fig. 1 a and 1b
Face figure.As shown in Figure 1a, groove 102 is formed in Semiconductor substrate 101.The first insulating layer is formed in the lower part of groove 102
103, shielded conductor 104 fills groove 102.On the top of groove 102, two openings separated by shielded conductor 104 are formed.Into
One step, as shown in Figure 1 b, gate-dielectric is formed in the upper portion side wall of groove 102 and the expose portion of shielded conductor 104
105, then conductive material is filled in two openings that shielded conductor 104 separates to form two grid conductors 106.
In the SGT power semiconductors, shielded conductor 104 is connected with the source electrode of power semiconductor,
For producing RESURF effects.Two grid conductors 106 are located at the both sides of shielded conductor 104.Shielded conductor 104 is partly led with power
Separated by the first insulating layer 103 between the drain region of body device, separated between gate electrode 106 by gate-dielectric 105.Grid
Separated between well region in conductor 106 and Semiconductor substrate 101 by gate-dielectric 105, so as to form raceway groove in well region.Such as
Shown in figure, the thickness of the first insulating layer 103 is less than the thickness of gate-dielectric 105.
It is theoretical according to SGT, no matter which kind of SGT structure, the material of shielded conductor 104 is required for and the isolation of the second conductive material
And the material for isolating needs to meet certain capacitance parameter, otherwise easily there is the short circuit of grid source, gate leakage capacitance Cgd exceptions etc.
Failure.How optimised devices structure and to meet the parameter and reliability requirement of product, while wiring method accomplished most efficient, low
Cost is the content to be studied of those skilled in the art.
The content of the invention
In view of the above problems, it is an object of the invention to provide a kind of power semiconductor and its manufacture method, wherein
Using the filling effect of different dimensioned trenches, while grid conductor and grid wiring are formed, so as to simplify technique.
According to an aspect of the present invention, there is provided a kind of manufacture method of power semiconductor, including：Class is adulterated first
Form multiple grooves in the Semiconductor substrate of type, the multiple groove include first size first groove and the second size the
Two grooves, the first size are more than second size；Splitting bar structure, the splitting bar are formed in the first groove
Structure includes shielded conductor, grid conductor and is clipped in the second insulating layer therebetween；Grid is formed in the second groove
Wiring, the grid wiring are connected with the grid conductor；Is formed in the region of the Semiconductor substrate adjacent trench
The body area of two doping types, second doping type are opposite with first doping type；Described in being formed in the body area
The source region of first doping type；And source electrode and gate electrode are formed, the source electrode and the source region and the screen
Conductor electrical connection is covered, the gate electrode is electrically connected with the grid wiring.
Preferably, the step of forming splitting bar structure includes：Insulation is formed on the side wall of the first groove and bottom
Lamination, the insulating laminate include the first insulating layer and the second insulating layer, and first insulating layer surrounds second insulating layer；
The shielded conductor is filled in the first groove；Formed on the top of the first groove and be located at the shielded conductor both sides
The first opening, the side wall on the first opening exposure first groove top；On the side wall on the first groove top
Form gate-dielectric；And form the grid conductor to fill first opening, wherein, the grid conductor with it is described
It is isolated from each other between shielded conductor by least one layer in the insulating laminate, by institute between the grid conductor and the body area
State gate-dielectric to be isolated from each other, be isolated from each other between the shielded conductor and the Semiconductor substrate by the insulating laminate.
Preferably, the step of forming grid wiring includes：First insulating layer is filled in the second groove；Institute
Second opening, the side wall on the second opening exposure second groove top are formed at the top for stating second groove；Described
The gate-dielectric is formed on the side wall on two groove tops；And the grid wiring is formed to fill second opening；
Wherein, it is isolated from each other between the grid wiring and the body area by the gate-dielectric.
Preferably, the first insulating layer in the first groove and the second groove is respectively conforma layer and filled layer,
While formed.
Preferably, between fill shielded conductor the step of and the step of forming the first opening, planarization steps are further included.
Preferably, before planarization steps, the shielded conductor, first insulating layer and second insulating layer point
The Part I in the first groove and second extended laterally on the semiconductor substrate surface Bao Kuo be located at
Point, in planarization steps, using the Semiconductor substrate as stop-layer, remove the shielded conductor, second insulating layer
With the respective Part II of first insulating layer so that, the shielded conductor, second insulating layer and first insulation
The respective Part I top of layer is flushed with the surface of first insulating layer.
Preferably, in the step of forming the first opening, the Part I of first insulating layer is removed positioned at described the
The part on one groove top, the shielded conductor extend downwardly predetermined depth so as to be formed from the semiconductor substrate surface
First opening of desired depth is extended downwardly from the semiconductor substrate surface.
Preferably, the step of forming grid conductor includes：Depositing first conductive layer is open with filling described first.
Preferably, first insulating layer is made of silica, and second insulating layer is by selected from silicon nitride, nitrogen oxides
Or at least one of polysilicon composition.
Preferably, the depth of the first groove and the second groove is in the range of 0.1 to 50 micron.
Preferably, 1.5 times of the width of the first groove more than or equal to the width of the second groove.
Preferably, the width of the first groove is in the range of 0.2 to 10 micron.
Preferably, the width of the second groove is in the range of 0.1 to 5 micron.
Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type
In another kind.
Preferably, the sidewall slope of the first groove so that the top width of the first groove is more than described first
The bottom width of groove.
Preferably, the step of the step of filling the shielded conductor and the formation grid conductor, is included at least once respectively
Deposition.
According to another aspect of the present invention, there is provided a kind of power semiconductor, including：It is more in Semiconductor substrate
A groove, the Semiconductor substrate are the first doping type, and the multiple groove includes the first groove and second of first size
The second groove of size, the first size are more than second size；Splitting bar structure in the first groove, institute
Stating splitting bar structure includes shielded conductor, grid conductor and is clipped in the second insulating layer therebetween；Positioned at the second groove
In grid wiring, the grid wiring is connected with the grid conductor；It is described positioned at the Semiconductor substrate Zhong Ti areas
Body area is the second doping type, second doping type and first doping type adjacent to the first groove top
Conversely；Source region in the body area, the source region are first doping type；With the source region and the shielded conductor
The source electrode of electrical connection；And the gate electrode being electrically connected with the grid wiring.
Preferably, the splitting bar structure includes：Insulating laminate positioned at the first groove lower sides and bottom, institute
Stating insulating laminate includes the first insulating layer and second insulating layer, and first insulating layer surrounds second insulating layer；Extremely
A few part is located at the shielded conductor in the first groove, and the shielded conductor extends to its bottom above the first groove
Portion, and be isolated from each other between the Semiconductor substrate by the insulating laminate；It is located at institute in the first groove top
State the grid conductor of shielded conductor both sides；Wherein, by the insulating laminate between the grid conductor and the shielded conductor
At least one layer be isolated from each other, be isolated from each other between the grid conductor and the body area by the gate-dielectric, the screen
Cover and be isolated from each other between conductor and the Semiconductor substrate by the insulating laminate.
Preferably, first insulating layer fills the lower part of the second groove, the grid wiring filling described second
The top of groove, is isolated from each other between the grid wiring and the body area by the gate-dielectric.
Preferably, the shielded conductor extends downwardly predetermined depth from the semiconductor substrate surface.
Preferably, first insulating layer is made of silica, and second insulating layer is by selected from silicon nitride, nitrogen oxides
Or at least one of polysilicon composition.
Preferably, the depth of the first groove and the second groove is in the range of 0.1 to 50 micron.
Preferably, 1.5 times of the width of the first groove more than or equal to the width of the second groove.
Preferably, the width of the first groove is in the range of 0.2 to 10 micron.
Preferably, the width of the second groove is in the range of 0.1 to 5 micron.
Preferably, first doping type is one kind in N-type and p-type, and second doping type is N-type and p-type
In another kind.
Preferably, the sidewall slope of the first groove so that the top width of the first groove is more than described first
The bottom width of groove.
Preferably, the power semiconductor is selected from cmos device, BCD devices, mosfet transistor, IGBT and Xiao
One kind in special based diode.
According to the method for the embodiment of the present invention, SGT structures are formed in power semiconductor, wherein, shielding
Insulating laminate is formed between conductor and Semiconductor substrate, so as to reduce gate leakage capacitance Cgd.
This method utilizes the filling effect of different dimensioned trenches, while forms grid conductor and grid wiring, so as to
Simplify technique.SGT structures are realized by better simply processing step, complex process in common process is solved, grid source easily occurs
While short circuit, the problems such as gate leakage capacitance Cgd is abnormal are so as to meet the parameter and reliability requirement of product, walked with reference to concrete technology
Suddenly wiring method is accomplished into most efficient, low cost.Compared with prior art, based on 0.25~0.35um techniques, this method can be with
The photoresist mask used in currently manufactured technique is reduced into by 3~4 photoresist masks.
A kind of separate gate power semiconductor device structure for reduction source drain capacitance that the embodiment of the present invention uses and its formation
Method, can also apply in the products such as CMOS, BCD, power MOSFET, high power transistor, IGBT and Schottky.
Brief description of the drawings
By the description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings：
The section of the manufacture method key step of power semiconductor according to prior art is shown respectively in Fig. 1 a and 1b
Figure.
Fig. 2 shows the flow chart of the manufacture method of power semiconductor according to embodiments of the present invention.
Fig. 3 a to 3i show the sectional view of method, semi-conductor device manufacturing method different phase according to embodiments of the present invention.
Embodiment
Hereinafter reference will be made to the drawings is more fully described the present invention.In various figures, identical element is using similar attached
Icon is remembered to represent.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to it is not shown some
Known part.For brevity, the semiconductor structure that can be obtained described in a width figure after several steps.
It should be appreciated that in the structure of outlines device, it is known as when by a floor, a region positioned at another floor, another area
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
Face " or the form of presentation of " A is on B and abuts therewith ".In this application, " A is in B " represents that A is located in B, and
And A and B is abutted, rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to whole half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.
It describe hereinafter many specific details of the present invention, such as the structure of device, material, size, processing work
Skill and technology, to be more clearly understood that the present invention.But just as the skilled person will understand, it can not press
The present invention is realized according to these specific details.
Unless hereinafter particularly pointing out, the various pieces of semiconductor devices can be by well known to those skilled in the art
Material is formed.Semi-conducting material is for example including Group III-V semiconductor, such as GaAs, InP, GaN, SiC, and IV races semiconductor, such as
Si、Ge。
Fig. 2 shows the flow chart of the manufacture method of SGT power semiconductors according to embodiments of the present invention, Fig. 3 a to 3i
The sectional view in different step is shown respectively.Manufacturer according to embodiments of the present invention is described below in conjunction with Fig. 2 and 3a to 3i
The step of method.
This method starts from Semiconductor substrate 101.Semiconductor substrate is, for example, to be doping to the silicon substrate of N-type, the silicon substrate
Longitudinal uniform doping, resistivity is for example between the scope of 1~15 Ω cm.Semiconductor substrate has opposite first surface
And second surface.Preferably, in the first surface of Semiconductor substrate, the works such as photoetching, etching, ion implanting, impurity activation are passed through
Skill forms the partial pressure ring structure of power semiconductor, and the partial pressure ring structure belongs to the known knot of one kind of this area device architecture
Structure part, this will not be detailed here.Preferably, the Semiconductor substrate 101 used in the present embodiment could be formed with MOS field-effects crystalline substance
The semiconductor devices such as body pipe, IGBT isolated-gate field effect transistor (IGFET)s, Schottky diode.
In step S101, first is formed respectively in the first area 201 of Semiconductor substrate 101 and second area 202
Groove 1021 and second groove 1022, as shown in Figure 3a.
Technique for forming first groove 1021 and second groove 1022 includes forming resist by photoetching and etching
Mask, the expose portion of Semiconductor substrate 101 is removed via the opening etching of Etching mask.
In this embodiment, first area 201 refers to the wiring area of source region and shielded conductor in SGT structures, second
Region 202 refers to the wiring area of grid conductor in SGT structures.
First groove 1021 and second groove 1022 are extended downwardly from the surface of Semiconductor substrate 101, and described in arrival
Predetermined depth in Semiconductor substrate 101.Scope of the depth of first groove 1021 and second groove 1022 at 0.1 to 50 micron
It is interior.The width of first groove 1021 is more than or equal to 1.5 times of the width of second groove 1022.In this embodiment, first groove
1021 width is in the range of 0.2 to 10 micron.The width of second groove 1022 is in the range of 0.1 to 5 micron.SGT is tied
The width of the groove of structure is wider much than the groove of the convention trench power semiconductor of identical conducting level of efficiency, and its ditch
The depth of groove is also deeply more many than the groove of convention trench power semiconductor.
Preferably, the sidewall slope of first groove 1021 and second groove 1022, such as the top relative to vertical trench
Into the angle of 85 to 89 degree so that the bottom width of groove is less than top width.The angle of groove is more oblique, beneficial to follow-up each medium
The problems such as the defects of layer, filling of conductive material, reduction blind causes.
In step s 102, insulating laminate is sequentially formed on the surface of Semiconductor substrate 101, which is included altogether
The first insulating layer 122 and the second insulating layer 123 of shape, as shown in Figure 3b.
In first groove 1021, the first insulating layer 122 surrounds the second insulating layer 123.In second groove 1022, first
Insulating layer 122 fills the inner space of groove, and the second insulating layer 123 is covered in the top of the first insulating layer 122 in this region.
The size of first groove 1021 is more than the size of second groove 1022, and therefore, deposition forms first in same technique
Insulating layer 122, can obtain the insulating layer of different filling effects.The first insulating layer 122 in first groove 1021 is conforma layer,
The first insulating layer 122 in second groove 1022 is filled layer.It is, for example, the first insulating layer 122 in the width of second groove 1022
Thickness it is 2 times or more large when, the first insulating layer 122 can be fully filled with second groove 1022.
First insulating layer 122 and the second insulating layer 123 are made of different insulating materials.In this embodiment, first is exhausted
Edge layer 122 is for example made of silica.Second insulating layer 123 for example by silicon nitride, nitrogen oxides or polysilicon extremely
A kind of few composition.Preferably, the second insulating layer 123 is made of silicon nitride.The thickness of first insulating layer 122 be, for example, 500 to
50000 angstroms, the thickness of the second insulating layer 123 is, for example, 50 to 5000 angstroms.The thickness of first insulating layer 122 is bigger, then grid leak electricity
It is smaller to hold Cgd.
Technique for forming the first insulating layer 122 is included by thermal oxide, chemical vapor deposition (CVD) or high density etc.
Ion body chemical vapor phase growing, oxide layer is formed in the inner wall of first groove 1021.The oxide layer conformally covers the first ditch
The side wall of groove 1021 and bottom, so as to still retain a part of inner space of first groove 1021.
Technique for forming the second insulating layer 123 includes passing through chemical vapor deposition (CVD) or high-density plasma
Chemical vapor deposition, nitride layer is formed on 122 surface of the first insulating layer.The nitride layer conformally covers the first insulating layer
122 surface, so as to still retain a part of inner space of first groove 1021.
In step s 103, shielded conductor 104 is formed in first groove 1021, as shown in Figure 3c.
The shielded conductor 104 is for example made of the non-crystalline silicon or polysilicon that adulterate.For the technique for forming shielded conductor 104
Such as including using process deposits polysilicons such as sputterings so that polysilicon fills the remainder of first groove 1021, and adopts
The polysilicon outside first groove 1021 is removed with chemical-mechanical planarization (CMP) so that filling first groove 1021
Polysilicon forms shielded conductor 104.
The deposition velocity of the polysilicon is, for example, 1 to 100 angstrom per minute, and depositing temperature is, for example, 510 to 650 degrees Celsius,
Thickness is, for example, 1000 to 100000 angstroms.By controlling the doping concentration of shielded conductor 104, its resistance can be adjusted.In the reality
Apply in example, the square resistance Rs of shielded conductor 104 is, for example, less than 20 ohm.Further, the square resistance Rs of shielded conductor 104
Smaller, the oxidated layer thickness formed during subsequent oxidation layer is bigger compared with silicon.Further, shielded conductor 104
Material selection amorphous, it is easier to form lower square resistance Rs.
In above-mentioned deposition step, one or many materials for depositing and forming shielded conductor 104 can be used.Multiple
During deposition, the speed of subsequent deposition process is less than previous deposition step, so that sedimentation rate is gradually reduced.In trench fill process
In, the slower filling effect of sedimentation rate is better, the difficult filling of channel bottom packing ratio the top of the groove, therefore in multiple filling, it is preceding
The speed of face deposition needs the speed of small primary depositing any later.
In above-mentioned chemical-mechanical planarization step, stop-layer is used as using Semiconductor substrate 101.In first groove
At 1021, which not only removes the part that polysilicon is located at outside first groove 1021, further also removes the second insulation
123 and first insulating layer 122 of layer is located at the part outside first groove 1021.Therefore, in first groove 1021, shielded conductor
104th, the top of the second insulating layer 123 and the first insulating layer 122 is flushed with the surface of Semiconductor substrate 101.In second groove
At 1022, which not only removes the part that the first insulating layer 122 is located at outside second groove 1022, further also removes
The second insulating layer 123 and polysilicon of the top of one insulating layer 122.Therefore, the top of the first insulating layer 122 and Semiconductor substrate
101 surface flushes.
In step S104, etching removes a part for the first insulating layer 122, so as to be formed on the top of first groove 1021
The first opening 1241 positioned at 104 both sides of shielded conductor, forms the second opening 1022 on the top of second groove 1022, such as Fig. 3 d
It is shown.First opening, 1241 and second opening 1022 exposes the upper portion side wall of first groove 1021 again.
The etch process is, for example, wet etching.Due to the selectivity of etchant, relative to Semiconductor substrate 101, second
Insulating layer 123 and shielded conductor 104 remove the expose portion of the first insulating layer 122.First insulating layer of etching etch-back 122
Part inside first groove 1021 and second groove 1022, so that the surface of exposing semiconductor substrate 101.Second insulating layer
123 and the height that is upwardly extended from the surface of Semiconductor substrate 101 of a part of shielded conductor 104 correspond to the first insulating layer
122 thickness, is, for example, 500 to 50000 angstroms.The height of the extension is beneficial to subsequent touch hole hole opening technology.First insulating layer 122
The depth extended downwardly from the surface of Semiconductor substrate 101 is, for example, 0.5 to 5 micron.After the etching, the first insulating layer 122
Retain positioned at the lower sides of first groove 1021 and a part for bottom so that the lower part of shielded conductor 104 is served as a contrast with semiconductor
Still it is isolated from each other between bottom 101 by insulating laminate.First insulating layer 122 is located at the part guarantor of the lower part of second groove 1022
Stay.As noted previously, as the first insulating layer 122 is filled layer in second groove 1022, therefore wherein without formation shielded conductor.
In step S105, form grid electricity in the upper portion side wall of first groove 1021 and the top of shielded conductor 104 and be situated between
Matter 105, and gate-dielectric 105 is formed in the upper portion side wall of second groove 1022, as shown in Figure 3 e.
Technique for forming gate-dielectric 105 can use thermal oxide.The temperature of the thermal oxide be, for example, 950 to
1200 degrees Celsius.The exposure silicon materials of Semiconductor substrate 101 and shielded conductor 104 form silica in thermal oxidation process.
In step of thermal oxidation, the surface of Semiconductor substrate 101 is also exposed in atmosphere.Gate-dielectric 105 is not placed only in the first ditch
In the upper portion side wall of groove 1021 and second groove 1022, and it is covered on the surface of Semiconductor substrate 101.
Compared with fine and close Semiconductor substrate 101, shielded conductor 104 is the amorphous or polycrystalline material of heavy doping, its structure
More loose, doping concentration is higher.As a result, gate-dielectric 105 is located at the thickness ratio of the Part II on 104 surface of shielded conductor
On 101 surface of Semiconductor substrate and the thickness of first groove 1021 and the Part I in second groove 1022 is big.Grid
The thickness of the Part I of pole dielectric 105 is, for example, 50 to 5000 angstroms, and the thickness of Part II is, for example, 60 to 10000 angstroms.
In step s 106, grid conductor 106 is formed in the first opening 1241, grid is formed in the second opening 1242
Wiring 131, and body area 107 and source region 108 are formed in the region adjacent with first groove 1021 of Semiconductor substrate 101, such as
Shown in Fig. 3 f.
The grid conductor 106 and grid wiring 131 are for example made of the non-crystalline silicon or polysilicon that adulterate.For forming grid
The technique of conductor 106 and grid wiring 131 process deposits polysilicon such as including using sputtering so that polysilicon filling first
The remainder of groove 1021 and second groove 1022, and removed using chemical-mechanical planarization (CMP) positioned at the first opening
1241 and the polysilicon of 1242 outside of the second opening so that polysilicon fills the opening of shielded conductor 104 both sides, so as to be formed in
Grid conductor 106 is formed in first opening 1241, grid wiring 131 is formed in the second opening 1242.
The deposition velocity of the polysilicon is, for example, 1 to 100 angstrom per minute, and depositing temperature is, for example, 510 to 650 degrees Celsius,
Thickness is, for example, 1000 to 100000 angstroms.By the doping concentration of control gate conductor 106, its resistance can be adjusted.In the reality
Apply in example, the square resistance Rs of grid conductor 106 is, for example, less than 20 ohm.Further, the square resistance Rs of grid conductor 106
Smaller, the oxidated layer thickness formed during subsequent oxidation layer is bigger compared with silicon.Further, grid conductor 106
Material selection amorphous, it is easier to form lower square resistance Rs.
In above-mentioned deposition step, one or many materials for depositing and forming grid conductor 106 can be used.Multiple
During deposition, the speed of subsequent deposition process is less than previous deposition step, so that sedimentation rate is gradually reduced.In trench fill process
In, the slower filling effect of sedimentation rate is better, the difficult filling of channel bottom packing ratio the top of the groove, therefore in multiple filling, it is preceding
The speed of face deposition needs the speed of small primary depositing any later.
Then, PXing Ti areas 107 are formed in Semiconductor substrate 101, and the source region of N-type is formed in body area 107.
Technique for forming body area 107 and source region 108 is, for example, multiple ion implanting.By selecting suitable dopant to form difference
The doped region of type, then carries out thermal annealing with activator impurity.In ion implanting, using shielded conductor 104 and grid conductor
106 are used as hard mask, body area 107 and the lateral position of source region 108 can be limited, so as to save photoresist mask.
The angle of the ion implanting is, for example, zero degree, i.e., relative to the surface vertical injection of Semiconductor substrate 101.By controlling ion
The energy of injection, can limit the injection depth of body area 107 and source region 108, so as to limit upright position.
When forming body area 107, for B11 or BF2 or first note B11 notes BF2 again for the dopant that uses, injects energy
It is 1E14~1E16 to measure as 20~100Kev, implantation dosage, and thermal annealing temperatures are 500 to 1000 degrees Celsius.Forming source region 108
When, for the dopant used for P+ or AS+, Implantation Energy is 60~150Kev, and implantation dosage is 1E14~1E16, thermal annealing temperatures
For 800 to 1100 degrees Celsius.
In this step, SGT structures, including 104 He of shielded conductor in groove are formed in first groove 1021
Grid conductor 106.Grid conductor 106 includes the Part I being located in first groove 1021, and in Semiconductor substrate 101
The Part II of Fang Yanshen.The Part I of grid conductor 106 is formed in the first opening 1241 of 104 both sides of shielded conductor,
So as to which shielded conductor 104 is clipped in the middle.It is isolated from each other between shielded conductor 104 and grid conductor 106 by the second insulating layer 123.
The lower part of shielded conductor 104 extends to the lower part of first groove 1021, is existed each other by insulating laminate between Semiconductor substrate 101
Isolation, the insulating laminate include the first insulating layer 122 and the second insulating layer 123.Grid conductor 106 and body area 107 and source region 108
It is adjacent, and be isolated from each other by gate-dielectric 105.
In step s 107, the dielectric layer 109 between the surface deposits of semiconductor structure, as shown in figure 3g.
Interlayer dielectric layer 109 covers the first area of Semiconductor substrate 101 and second area interlayer dielectric layer 109 can be by
Formed selected from least one of silica, silicon nitride, silicon oxynitride, and can be individual layer or laminated construction.In the reality
Apply in example, interlayer dielectric layer 109 for example can be the boron-phosphorosilicate glass (BPSG) that thickness is 2000 to 15000 angstroms.
In step S108, formed in interlayer dielectric layer 109 and reach source region 108, grid conductor 106 and shielded conductor
104 multiple contact holes 125, and contact zone 110 is formed by ion implanting respectively in the bottom of multiple contact holes 125, such as
Shown in Fig. 3 h.
Technique for forming contact hole 125 is, for example, dry etching.The sidewall slope of contact hole 125, such as relative to
Angles of the top of vertical first groove 1021 and second groove 1022 into 85 to 89.9 degree so that the bottom of contact hole 125 is wide
Degree is less than top width.The angle of contact hole 125 is more oblique, beneficial to the filling of subsequent conductive material, caused by reducing blind
The problems such as defect.
In the first area 201 of Semiconductor substrate 101, first group of contact hole in multiple contact holes 125 sequentially passes through
Interlayer dielectric layer 109 and gate-dielectric 105, extend to the desired depth in shielded conductor 104, and second group of contact hole is worn successively
Cross the desired depth in interlayer dielectric layer 109, gate-dielectric 10, the arrival body of source region 108 area 107.The desired depth is, for example,
0.1 to 1 micron.
In the second area 202 of Semiconductor substrate 101, the 3rd group of contact hole in multiple contact holes 125 sequentially passes through
Interlayer dielectric layer 109, extends to the desired depth in grid conductor 106.
In ion implanting, using interlayer dielectric layer as hard mask, the lateral position of contact zone 110 is limited, so as to
To save photoresist mask.For B11 or BF2 or first note B11 notes BF2 to the dopant that the ion implanting uses again,
Implantation Energy is 20~100Kev, and implantation dosage is 1E14~1E16, and thermal annealing temperatures are 500 to 1000 degrees Celsius.In ion
After injection, thermal annealing can be carried out to activate dopant.
In step S109, source electrode 111 and gate electrode 112 are formed, as shown in figure 3i.
The step is for example including deposited metal layer and patterning.The metal layer for example by selected from Ti, TiN, TiSi, W,
One kind or its alloy composition in AL, AlSi, AlSiCu, Cu, Ni.Metal layer pattern is melted into by source electrode 111 by etching
With gate electrode 112.As shown in the figure, source electrode 111 and gate electrode 112 are isolated from each other.
In the first area 201 of Semiconductor substrate 101, source electrode 111 is via in the multiple contact hole 125
One group of contact hole reaches shielded conductor 104, and source region 108 is reached via second group of contact hole in the multiple contact hole 125, from
And source region 108 and shielded conductor 104 are electrically connected to each other.In the second area 202 of Semiconductor substrate 101, gate electrode 112
Grid conductor 106 is reached via the 3rd group of contact hole in the multiple contact hole 125.
After step S109, the metallization of power semiconductor is had been carried out.Further, according to the needs of product,
Passivation layer protection can be increased, complete the processing of power semiconductor Facad structure.By being thinned, carrying on the back a systems such as gold, scribing
Row postchannel process completes the final realization of device.
It should be noted that although in above-mentioned sectional view, the shielded conductor 104 in different grooves is isolated from each other, and grid is led
Body 106 is isolated from each other, however, in actual power semiconductor, from planar structure, the screen in above-mentioned difference groove
Covering conductor 104 can be connected to each other, and grid conductor 106 can also be connected to each other.In one embodiment, the connection mode is for example
It is the grid wiring in the grid conductor 106 and second groove 1022 in different first grooves 1021 by single conductive layer entirety shape
Into, and shielded conductor 104 in different first groove 1021 is integrally formed by single conductive layer.In alternate embodiments,
The connection mode is, for example, that the shielded conductor 104 in different first grooves 1021 is connected to each other using public source electrode,
And public gate electrode is utilized by the grid in the grid conductor 106 in different first grooves 1021 and second groove 1022
Wiring 131 is connected to each other.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Non-exclusive inclusion, so that process, method, article or equipment including a series of elements not only will including those
Element, but also including other elements that are not explicitly listed, or further include as this process, method, article or equipment
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Also there are other identical element in process, method, article or equipment including key element.
For example above according to the embodiment of the present invention, these embodiments do not have all details of detailed descriptionthe, do not limit yet
The specific embodiment that the invention is only.Obviously, as described above, can make many modifications and variations.This specification is chosen simultaneously
These embodiments are specifically described, are in order to preferably explain the principle of the present invention and practical application, so that technical field
Technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention only by claims and
The limitation of its four corner and equivalent.
Claims (28)
1. a kind of manufacture method of power semiconductor, including：
Multiple grooves are formed in the Semiconductor substrate of the first doping type, the multiple groove includes the first ditch of first size
The second groove of groove and the second size, the first size are more than second size；
Splitting bar structure is formed in the first groove, the splitting bar structure includes shielded conductor, grid conductor and is clipped in
Therebetween the second insulating layer；
Grid wiring is formed in the second groove, the grid wiring is connected with the grid conductor；
Form the body area of the second doping type in the region of the Semiconductor substrate adjacent trench, second doping type with
First doping type is opposite；
The source region of first doping type is formed in the body area；And
Form source electrode and gate electrode, the source electrode are electrically connected with the source region and the shielded conductor, the grid
Pole electrode is electrically connected with the grid wiring.
2. according to the method described in claim 1, wherein, the step of forming splitting bar structure, includes：
Insulating laminate is formed on the side wall of the first groove and bottom, the insulating laminate includes the first insulating layer and second
Insulating layer, first insulating layer surround second insulating layer；
The shielded conductor is filled in the first groove；
The first opening positioned at the shielded conductor both sides, the first opening exposure institute are formed on the top of the first groove
State the side wall on first groove top；
Gate-dielectric is formed on the side wall on the first groove top；And
The grid conductor is formed to fill first opening,
Wherein, it is isolated from each other between the grid conductor and the shielded conductor by least one layer in the insulating laminate, institute
State and be isolated from each other between grid conductor and the body area by the gate-dielectric, the shielded conductor and the Semiconductor substrate
Between be isolated from each other by the insulating laminate.
3. according to the method described in claim 2, wherein, the step of forming grid wiring, includes：
First insulating layer is filled in the second groove；
The second opening, the side wall on the second opening exposure second groove top are formed on the top of the second groove；
The gate-dielectric is formed on the side wall on the second groove top；And
The grid wiring is formed to fill second opening；
Wherein, it is isolated from each other between the grid wiring and the body area by the gate-dielectric.
4. according to the method described in claim 3, wherein, the first insulating layer in the first groove and the second groove divides
Not Wei conforma layer and filled layer, while formed.
5. according to the method described in claim 3, between fill shielded conductor the step of and the step of forming the first opening, also
Including planarization steps.
6. according to the method described in claim 5, wherein, before planarization steps, the shielded conductor, described first are insulated
Layer and second insulating layer include the Part I being located in the first groove and in the Semiconductor substrate tables respectively
The Part II extended laterally on face,
In planarization steps, using the Semiconductor substrate as stop-layer, the shielded conductor, second insulating layer are removed
With the respective Part II of first insulating layer so that, the shielded conductor, second insulating layer and first insulation
The respective Part I top of layer is flushed with the surface of first insulating layer.
7. according to the method described in claim 6, wherein, in the step of forming the first opening, remove first insulating layer
Part I be located at the part on the first groove top, the shielded conductor is from the semiconductor substrate surface to downward
Predetermined depth is stretched so as to form first opening that desired depth is extended downwardly from the semiconductor substrate surface.
8. according to the method described in claim 3, wherein, the step of forming grid conductor, includes：Depositing first conductive layer is to fill out
Fill first opening.
9. according to the method described in claim 3, wherein, first insulating layer is made of silica, second insulating layer
By being formed selected from least one of silicon nitride, nitrogen oxides or polysilicon.
10. according to the method described in claim 3, wherein, the depth of the first groove and the second groove is 0.1 to 50
In the range of micron.
11. according to the method described in claim 10, wherein, the width of the first groove is more than or equal to the second groove
1.5 times of width.
12. according to the method for claim 11, wherein, the width of the first groove is in the range of 0.2 to 10 micron.
13. according to the method for claim 12, wherein, the width of the second groove is in the range of 0.1 to 5 micron.
14. according to the method described in claim 3, wherein, first doping type is one kind in N-type and p-type, described the
Two doping types are the another kind in N-type and p-type.
15. according to the method described in claim 1, wherein, the sidewall slope of the first groove so that the first groove
Top width is more than the bottom width of the first groove.
16. according to the method described in claim 1, wherein, the step of filling the shielded conductor and the grid conductor is formed
The step of respectively include deposit at least once.
17. a kind of power semiconductor, including：
Multiple grooves in Semiconductor substrate, the Semiconductor substrate are the first doping type, and the multiple groove includes
The second groove of the first groove of first size and the second size, the first size are more than second size；
Splitting bar structure in the first groove, the splitting bar structure include shielded conductor, grid conductor and are clipped in
Therebetween the second insulating layer；
Grid wiring in the second groove, the grid wiring are connected with the grid conductor；
Positioned at the Semiconductor substrate Zhong Ti areas, the body area is the second doping type adjacent to the first groove top,
Second doping type is opposite with first doping type；
Source region in the body area, the source region are first doping type；
The source electrode being electrically connected with the source region and the shielded conductor；And
The gate electrode being electrically connected with the grid wiring.
18. power semiconductor according to claim 17, wherein, the splitting bar structure includes：
Insulating laminate positioned at the first groove lower sides and bottom, the insulating laminate include the first insulating layer and described
Second insulating layer, first insulating layer surround second insulating layer；
At least a portion is located at the shielded conductor in the first groove, and the shielded conductor extends above the first groove
To its bottom, and it is isolated from each other between the Semiconductor substrate by the insulating laminate；
It is located at the grid conductor of the shielded conductor both sides in the first groove top；
Wherein, it is isolated from each other between the grid conductor and the shielded conductor by least one layer in the insulating laminate, institute
State and be isolated from each other between grid conductor and the body area by the gate-dielectric, the shielded conductor and the Semiconductor substrate
Between be isolated from each other by the insulating laminate.
19. power semiconductor according to claim 18, wherein, first insulating layer fills the second groove
Lower part, the grid wiring fills the top of the second groove, by the grid between the grid wiring and the body area
Pole dielectric is isolated from each other.
20. power semiconductor according to claim 17, wherein, the shielded conductor is from the Semiconductor substrate table
Extend predetermined depth downwards.
21. power semiconductor according to claim 17, wherein, first insulating layer is made of silica, institute
The second insulating layer is stated by being formed selected from least one of silicon nitride, nitrogen oxides or polysilicon.
22. power semiconductor according to claim 19, wherein, the depth of the first groove and the second groove
Degree is in the range of 0.1 to 50 micron.
23. power semiconductor according to claim 22, wherein, the width of the first groove is more than or equal to described
1.5 times of the width of second groove.
24. power semiconductor according to claim 23, wherein, the width of the first groove is micro- 0.2 to 10
In the range of rice.
25. power semiconductor according to claim 24, wherein, the width of the second groove is at 0.1 to 5 micron
In the range of.
26. power semiconductor according to claim 17, wherein, first doping type is in N-type and p-type
One kind, second doping type are the another kind in N-type and p-type.
27. power semiconductor according to claim 17, wherein, the sidewall slope of the first groove so that institute
The top width for stating first groove is more than the bottom width of the first groove.
28. power semiconductor according to claim 17, wherein, the power semiconductor is selected from CMOS devices
One kind in part, BCD devices, mosfet transistor, IGBT and Schottky diode.
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| US20150349091A1 (en) * | 2014-05-31 | 2015-12-03 | Hamza Yilmaz | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN105489649A (en) * | 2014-09-18 | 2016-04-13 | 万国半导体股份有限公司 | Method for improving terminal area low breakdown voltage in groove type power device |
| CN106298941A (en) * | 2016-09-13 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | Shield grid groove power device and manufacture method thereof |
| CN207781609U (en) * | 2017-11-17 | 2018-08-28 | 杭州士兰集成电路有限公司 | Power semiconductor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863969A (en) * | 2020-07-17 | 2020-10-30 | 上海陆芯电子科技有限公司 | Shielded gate trench type MOSFET device and method of manufacturing the same |
| CN112582260A (en) * | 2020-12-04 | 2021-03-30 | 矽力杰半导体技术(杭州)有限公司 | Trench MOSFET and method for manufacturing same |
| CN112582260B (en) * | 2020-12-04 | 2023-08-22 | 杭州芯迈半导体技术有限公司 | Trench MOSFET and manufacturing method thereof |
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