TWI719430B - Integrated chip and method of forming the same - Google Patents

Abstract

The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a gate structure disposed over a substrate between source and drain regions and a dielectric layer laterally extending from over the gate structure to between the gate structure and the drain region. A composite etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. A contact etch stop layer directly contacts an upper surface and sidewalls of the composite etch stop layer. A field plate is laterally surrounded by a first inter-level dielectric (ILD) layer and vertically extends from a top of the first ILD layer, through the contact etch stop layer, and into the composite etch stop layer.

Description

Integrated wafer and its forming method

The embodiment of the present invention relates to an integrated wafer and a method of forming the same.

Modern integrated wafers include millions or billions of semiconductor elements formed on a semiconductor substrate (e.g., silicon). Integrated chips (IC) can use many different types of transistor components depending on the application of the IC. In recent years, the market for cellular and radio frequency (RF) components has gradually expanded, resulting in a significant increase in the use of high-voltage transistor components. For example, high-voltage transistor elements are commonly used in power amplifiers in the RF transmit/receive chain due to their ability to handle high breakdown voltage (BV) (for example, greater than about 50 volts) and high frequencies.

An integrated wafer according to an embodiment of the present invention includes a gate structure, a dielectric layer, a composite etching stop layer, a contact etching stop layer, and a field plate. The gate structure is arranged above the substrate between the source region and the drain region. The dielectric layer extends laterally from above the gate structure to between the gate structure and the drain region. The composite etch stop layer includes a plurality of different dielectric materials stacked on the dielectric layer. Contact etch stop layer Directly contact the upper surface of the composite etch stop layer and a plurality of sidewalls. The field plate is laterally surrounded by the first interlayer dielectric layer, and extends vertically from the top of the first interlayer dielectric layer, extends through the contact etch stop layer, and extends into the composite etch stop layer .

An integrated wafer according to an embodiment of the present invention includes a gate structure, a photoresist protective oxide, a composite etching stop layer, a plurality of conductive contacts, and a field plate. The gate structure is arranged above the substrate. The photoresist protective oxide extends laterally from above the gate structure to beyond the outermost sidewall of the gate structure. The composite etch stop layer includes a first dielectric material above the photoresist protective oxide and a second dielectric material in contact with the upper surface of the first dielectric material. A plurality of conductive contacts are laterally surrounded by the first interlayer dielectric layer above the substrate. A field plate extends from the top of the first interlayer dielectric layer to the composite etch stop layer and includes the same material as the plurality of conductive contacts, wherein the composite etch stop layer laterally contacts the field plate And the composite etch stop layer separates the field plate and the photoresist protection oxide vertically.

A method of forming an integrated wafer according to an embodiment of the present invention includes: forming a gate structure above the substrate between the source region and the drain region in the substrate; A dielectric layer is formed between the pole structure and the drain region; a composite etch stop layer is formed above the dielectric layer, wherein the composite etch stop layer includes a plurality of stacked dielectric materials; and the composite etch stops A first interlayer dielectric layer is formed above the layer; the first interlayer dielectric layer is selectively etched to simultaneously define a plurality of contact openings extending to the substrate and a field plate extending to the composite etch stop layer Openings; and filling the plurality of contact openings and the field plate openings with one or more conductive materials.

100, 800, 2000, 2200, 2300, 2400: high voltage transistor components

102, 802, 2102: base

104, 804: source region

105: Arrow

106: Drain Region

108: gate electrode

110: gate dielectric layer

112: Passage area

114, 204, 702, 2104: drift zone

116, 210: Gate structure

118, 1504: first interlayer dielectric layer

120, 814: Contact

120a: first contact

120b: second contact

120c: third contact

122, 214, 408, 902: field board

124, 402, 404: Dielectric layer

126: second dielectric layer

128: The first post-process metal wire

200, 300, 400, 500, 600, 700a, 700b, 700c, 1000: high voltage LDMOS components

202, 808, 2106: main area

206: Additional STI area

208, 810: contact area

212: Sidewall spacer

302: Quarantine

402: Silicide barrier

404: Field plate etching stop layer

406, 1502: contact etching stop layer

410, 1702: the first metal material

412, 1802: second metal material

414: inner lining

416: second interlayer dielectric layer

418, 504, 604: the first metal wire layer

420: Flat surface

502, 602, 904: the second ILD layer

506, 606: conductive path

704: Deep Well

706: Relatively doped underlying buried layer

708: matrix area

710: buried layer

712: well region

802b: dorsal

802f: Front side surface

806: epitaxial layer

812: conductive material

816: Overlay metal wire layer

818: Electrical Path

900, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2100, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200: cross-sectional view

906, 2120: top view

1002: self-aligned drift zone

1002s: sidewall

1100, 3300: method

1102, 1104, 1106, 1108, 1110, 1112, 1114, 1116, 1118, 1120, 3302, 3304, 3306, 3308, 3310, 3312, 3314, 3316, 3318: Action

1202, 1604, 2702: mask layer

1204: high energy dopant

1602: the first etchant

1606: contact opening

1608: Field Board Opening

1704, 3102: Line

2002: Photoresist protective oxide

2004: Composite etch stop layer

2006, 2302, 2402: the first dielectric material

2008, 2304, 2404: second dielectric material

2108: Horizontal distance

2110: depth

2112, t ₁ , th ₁ : first thickness

2114: width

2122: length

2116, d 3, 004: distance

2118: Silicide layer

2306, 2406: third dielectric material

2408: Fourth Dielectric Material

3002: Etchant

t ₂ , th ₂ : second thickness

th ₃ : third thickness

th ₄ : fourth thickness

th ₅ : thickness

s : Spacing

When read in conjunction with the accompanying drawings, the aspect of the disclosure can be best understood from the following detailed description. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 shows a cross-sectional view of some embodiments of the disclosed high-voltage transistor element with field plates.

2 to 4 show cross-sectional views of some other embodiments of the disclosed laterally diffused MOSFET (LDMOS) device with field plates.

5 to 6 show cross-sectional views of some embodiments of field plate biasing configurations for high-voltage LDMOS devices achieved by metal interconnect wiring.

7A to 7C show cross-sectional views of some embodiments of high-voltage LDMOS devices in different switching isolation configurations.

FIG. 8 shows a cross-sectional view of a high-voltage transistor element with a field plate facing downward.

9A to 9B show some embodiments of the disclosed high-voltage LDMOS with field plates on the metal line layer.

FIG. 10 shows some embodiments of high-voltage LDMOS devices with self-aligned drift regions.

FIG. 11 shows a flowchart of some embodiments of a method of forming a high-voltage transistor element with a field plate.

Figures 12 to 19 illustrate a method of forming a high-voltage transistor element with a field plate Cross-sectional views of some embodiments.

20-24 show some embodiments of the disclosed high-voltage transistor device with a composite etch stop layer defining a field plate.

25 to 32 show cross-sectional views of some embodiments of a method of forming a high-voltage transistor element with a composite etch stop layer defining a field plate.

FIG. 33 shows a flowchart of some embodiments of a method of forming a high-voltage transistor element with a composite etch stop layer defining a field plate.

The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features that may be formed between the first feature and the second feature. An embodiment is formed between the second features such that the first feature and the second feature may not directly contact each other. In addition, the content of the present disclosure may repeat graphical element symbols and/or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spatially relative terms can be used in this article, such as "below", "below", "below", "above", "above" And the like, to describe the relationship between one element or feature and another (some) elements or features as shown in the drawings. In addition to the orientations depicted in the drawings, spatially relative terms are intended to cover different orientations of elements in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the space used in this article is relatively descriptive. The predicate can also be interpreted accordingly.

The high-voltage crystal element is usually constructed with a field plate. The field plate is a conductive element that is placed above the channel region to enhance the performance of the high-voltage transistor element by manipulating the electric field generated by the gate electrode (for example, reducing the peak electric field). By manipulating the electric field generated by the gate electrode, the high-voltage transistor element can achieve a higher breakdown voltage. For example, a laterally diffused metal oxide semiconductor (LDMOS) transistor element usually includes a field plate that extends from the channel region to an adjacent drift region (drift region), and the adjacent The drift region is placed between the channel region and the drain region.

The field plates can be formed in many different ways. For example, the field plate can be formed by extending a conductive gate material (eg, polysilicon) from the gate electrode toward the drift region. However, in this type of configuration, the field plate is synchronized with the gate bias, which increases the burden on the gate-to-drain capacitance (Cgd) and increases the switching of the device loss. Alternatively, the conductive gate material can be patterned to form separate field plates. This type of configuration reduces the gate-drain capacitance (Cgd), but the location of the field plate is usually restricted by design rules. In yet another alternative, non-gate materials can be used to form the field plates. However, such solutions use additional processing steps, which will increase the manufacturing cost of the resulting integrated wafers.

Correspondingly, the present disclosure relates to a high-voltage transistor element having a field plate made of non-gate material, the field plate and the back-end-of-the-line (BEOL) metal layer To form at the same time, in order to achieve a low-cost manufacturing method. In some embodiments, the high-voltage transistor element has a gate electrode disposed above the substrate between the source region and the drain region, and the source region and the drain region are located in the substrate . The dielectric layer extends laterally from above the gate electrode To the drift region arranged between the gate electrode and the drain region. The field plate is located in a first inter-level dielectric (ILD) layer, and the first inter-level dielectric layer covers the substrate. The field plate extends laterally from above the gate electrode to above the drift region, and extends vertically from the dielectric layer to the top surface of the first ILD layer. A plurality of metal contacts having the same material as the field plate extend vertically from the bottom surface of the first ILD layer to the top surface of the first ILD layer.

FIG. 1 shows a cross-sectional view of some embodiments of the disclosed high-voltage transistor device 100 having a field plate 122.

The high-voltage crystal element 100 includes a source region 104 and a drain region 106 disposed in a semiconductor substrate 102. The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 have a second doping type with a higher doping concentration than the semiconductor substrate 102. In some embodiments, the first doping type may be n-type doping, and the second doping type may be p-type doping.

The gate structure 116 is disposed above the semiconductor substrate 102 at a position laterally disposed between the source region 104 and the drain region 106. The gate structure 116 includes a gate electrode 108 separated from the semiconductor substrate 102 by a gate dielectric layer 110. After receiving the bias voltage, the gate electrode 108 is used to generate an electric field, which controls the movement of charge carriers in the channel region 112, which is arranged laterally between the source region 104 and the drain region 106 between. For example, during operation, a gate-source voltage (VGS) can be selectively applied to the gate electrode 108 relative to the source region 104 to form a conductive channel in the channel region 112. When a gate-source voltage is applied to form a conductive channel, a drain-source voltage (VDS) is applied to move the charge carriers between the source region 104 and the drain region 106 (for example, as shown by arrow 105 ).

The channel region 112 extends laterally from the source region 104 to the adjacent drift region 114 (That is, the drain extension area). The drift region 114 includes a second doping type with a relatively low doping concentration, which provides a higher impedance under a high operating voltage. The gate structure 116 is disposed above the channel region 112. In some embodiments, the gate structure 116 may extend from above the channel region 112 to a position overlying a portion of the drift region 114.

The first interlayer dielectric (ILD) layer 118 is disposed on the semiconductor substrate 102. One or more conductive metal structures are disposed in the first ILD layer 118. In some embodiments, the one or more conductive metal structures include a plurality of contacts 120 for providing source regions 104, drain regions 106 or gate electrodes 108 and disposed in the second ILD layer 126 The second ILD layer 126 is overlaid on the first ILD layer 118 for the vertical connection between the metal line layers 128 of the first back end of line (BEOL).

The one or more conductive metal structures may further include a field plate 122 disposed in the first ILD layer 118 at a position overlying the gate electrode 108 and the drift region 114. The field plate 122 includes the same conductive material as the plurality of contacts 120. The field plate 122 may be disposed above the dielectric layer 124, which is configured to separate the field plate 122 from the drift region 114 and the gate electrode 108. In some embodiments, the dielectric layer 124 extends laterally beyond the field plate 122 in one or more directions.

During operation, the field plate 122 is configured to act on the electric field generated by the gate electrode 108. The field plate 122 can be used to change the distribution of the electric field generated by the gate electrode 108 in the drift region 114, which enhances the internal electric field of the drift region 114 and increases the drift doping concentration of the drift region 114, thereby enhancing the high-voltage transistor element 100 breakdown voltage capability (breakdown voltage capability).

FIG. 2 shows a cross-sectional view of some other embodiments of the disclosed high-voltage transistor device including a high-voltage laterally diffused MOSFET (LDMOS) device 200 with a field plate 214.

The LDMOS device 200 includes a source region 104 and a drain region 106 disposed in the semiconductor substrate 102. The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 include highly doped regions having a second doping type different from the first doping type. In some embodiments, the first doping type may be p-type, and the second doping type may be n-type. In some embodiments, the source region 104 and the drain region 106 may have a doping concentration in a range ^{between about 1019 cm −3} and about 1020 cm ^−3.

The contact region 208 (for example, "p-tap" or "n-tap") having the first doping type (for example, p+ doping) is laterally abutted (abut)于源区104。 At the source region 104. The contact area 208 provides an ohmic connection with the semiconductor substrate 102. In some embodiments, the contact area between the p-type 208 may have a range of between about ^-3 and about 10 18 cm -3 doping concentration of 1020cm ^-3. The contact region 208 and the source region 104 are disposed in the body region 202. The body region 202 has a first doping type with a higher doping concentration than the semiconductor substrate 102. For example, the semiconductor substrate 102 may have ^{a doping concentration in a range between about 1014 cm -3} and about 1016 cm ^-3 , and the body region 202 may have a doping concentration between about 1016 cm ^-3 and about 1018 cm ^-3 Doping concentration within the range.

The drain region 106 is disposed in the drift region 204, and the drift region is disposed in the semiconductor substrate 102 at a position laterally adjacent to the body region 202. The drift region 204 includes a second doping type with a relatively low doping concentration, which provides a higher impedance when the LDMOS device 200 is operated at a high voltage. In some embodiments, the drift region 204 may have a doping concentration in a range ^{between about 1015 cm -3} and about 1017 cm ^-3.

The gate structure 210 is disposed above the semiconductor substrate 102 at a position laterally disposed between the source region 104 and the drain region 106. In some embodiments, the gate structure 210 may extend laterally from above the body region 202 to a position overlying a portion of the drift region 204. The gate structure 210 includes a gate electrode 108 separated from the semiconductor substrate 102 by a gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 may include silicon dioxide (SiO ₂ ) or a high-k gate dielectric material, and the gate electrode 108 may include polysilicon ( polysilicon) or metal gate material (for example, aluminum). In some embodiments, the gate structure 210 may also include sidewall spacers 212 disposed on opposite sides of the gate electrode 108. In various embodiments, the sidewall spacers 212 may include nitride-based sidewall spacers (for example, including SiN) or oxide-based sidewall spacers (for example, SiO ₂ , SiOC, etc.).

One or more dielectric layers 124 are disposed above the gate electrode 108 and the drift region 204. In some embodiments, the one or more dielectric layers 124 continuously extend from above a portion of the gate electrode 108 to above a portion of the drift region 204. In some embodiments, one or more dielectric layers 124 may be conformally disposed on the drift region 204, the gate electrode 108, and the sidewall spacers 212.

The field plate 214 is disposed above the one or more dielectric layers 124 and is laterally surrounded by the first ILD layer 118. The field plate 214 extends from above the gate electrode 108 to above the drift region 204. The size of the field plate 214 can vary according to the size and characteristics of the LDMOS device 200. In some embodiments, the field plate 214 may have a size between about 50 nanometers and about 1 micrometer. In other embodiments, the field plate 214 may be larger or smaller. In some embodiments, the first ILD layer 118 may include a dielectric material with a relatively low dielectric constant (for example, less than or equal to about 3.9), which provides electrical isolation between the plurality of contacts 120 and/or the field plates 122 . In some embodiments, the first ILD layer 118 may include ultra-low-k dielectric materials or low-k dielectric materials. Dielectric material (for example, SiCO).

The field plate 214 extends vertically from the dielectric layer 124 to the top surface of the first ILD layer 118. In some embodiments, the field plate 214 can extend vertically to a height greater than or equal to the height of the contact 120 and the top surface of the first ILD layer 118. The field plate 122 has an uneven surface adjacent to one or more dielectric layers 124. The uneven surface makes the field plate 122 have a first thickness t ₁ in the area above the gate electrode 108 and a second thickness t ₂ greater than the first thickness t ₁ in the area overlying the drift region 204.

The plurality of contacts 120 are also surrounded by the first ILD layer 118. The plurality of contacts 120 may include a first contact 120 a coupled to the contact region 208, a second contact 120 b coupled to the drain region 106, and a third contact 120 c coupled to the gate electrode 108. In some embodiments, the first contact 120 a may include a butted contact (not shown), which contacts both the contact region 208 and the source region 104. In some embodiments, the plurality of contacts 120 and the field plate 122 may include the same metal material. For example, the multiple contacts 120 and the field plates 122 may include tungsten (W), tantalum nitride (TaN), titanium (Ti), titanium-nitride (TiN) , Aluminum copper (AlCu), copper (Cu) and/or other similar conductive materials.

FIG. 3 shows a cross-sectional view of some other embodiments of the disclosed high-voltage LDMOS device 300 with a field plate 214.

The LDMOS device 300 includes an isolation region 302 disposed in the drift region 204 at a position laterally disposed between the gate structure 210 and the drain region 106. The isolation region 302 improves the isolation between the gate structure 210 and the drain region 106, thereby preventing the gate structure 210 when the LDMOS element 300 is operated at a large operating voltage. The dielectric breakdown with the drift region 204 is broken down. For example, the isolation region 302 can be introduced into the drift region 204 of the LDMOS device (which is designed to operate at the first breakdown voltage) to increase the breakdown voltage of the LDMOS device 300 without drastically changing the manufacturing process of the LDMOS device. . In some embodiments, the isolation region 302 may include shallow trench isolation (STI). In other embodiments, the isolation region 302 may include field oxide.

FIG. 4 shows a cross-sectional view of some other embodiments of the disclosed high-voltage LDMOS device 400 having a field plate 408.

The LDMOS device 400 includes a plurality of dielectric layers 402 to 404 disposed between the field plate 408 and the gate structure 210 and/or the drift region 204. The plurality of dielectric layers 402 to 404 are configured to electrically isolate the field plate 408 from the gate structure 210 and/or the drift region 204. In an embodiment, the plurality of dielectric layers 402 to 404 may include two or more different dielectric materials. In some embodiments, the plurality of dielectric layers 402 to 404 may include one or more dielectric layers used during a typical CMOS manufacturing process, thereby limiting the use of the field plate 408 and the gate structure 210 and/ Or an additional manufacturing step for electrically isolating the drift region 204.

For example, the plurality of dielectric layers 402 to 404 may include a silicide barrier layer 402. In some embodiments, the silicide blocking layer 402 may include a resist-protection oxide (RPO) layer to prevent the formation of silicide. The silicide barrier layer 402 may be disposed above the gate electrode 108 and the drift region 204. In some embodiments, the silicide barrier layer 402 may continuously extend from above the gate electrode 108 to above the drift region 204.

In some embodiments, the plurality of dielectric layers 402 to 404 may further include a field plate etch stop layer (ESL) 404. Field board ESL 404 available It is disposed above the silicide barrier layer 402 and used to control the etching of the opening for the field plate 408. The field plate ESL 404 may account for the difference in etching depth and/or the difference in etching rate between the contact 120 and the field plate 408 (for example, due to an etch loading effect). In some embodiments, for example, the field plate ESL 404 may include a silicon nitride (SiN) layer.

In some alternative embodiments (not shown), the plurality of dielectric layers 402 to 404 may additionally or alternatively include gate dielectric layers. In such an embodiment, the gate dielectric layer may be configured to be laterally adjacent to the gate structure 210 overlying the drift region 204 at the location. In some embodiments, the dielectric layer oxide may include silicon dioxide (for example, SiO ₂ ) or a high-k gate dielectric material. In still other embodiments, the plurality of dielectric layers 402 to 404 may additionally or alternatively include an ILD layer (for example, the first ILD layer 118).

A contact etch stop layer (CESL) 406 is disposed on the semiconductor substrate 102 and the field plate ESL 404. In some embodiments, the CESL 406 extends above the semiconductor substrate 102 at positions between the plurality of contacts 120 and the field plate 408 such that the CESL 406 is adjacent to the plurality of contacts 120 and the plurality of sidewalls of the field plate 408. The CESL 406 is overlying the gate structure 210. In some embodiments, the CESL 406 can also be overlying the plurality of dielectric layers 402 to 404. In other embodiments, one or more of the plurality of dielectric layers 402 to 404 (for example, the field plate ESL 404) may be overlaid on the CESL 406. In some embodiments, CESL 406 may include a nitride layer. For example, CESL 406 may include silicon nitride (SiN).

The field plate 408 is disposed in the first ILD layer 118 and adjacent to one or more of the CESL 406 and the plurality of dielectric layers 402 to 404. In some embodiments, the field plate 408 extends through the CESL 406 to abut the dielectric layers 402 into the dielectric layer 404 One or more of. In such embodiments, one or more of the plurality of dielectric layers 402 to 404 separates the field plate 408 from the gate structure 210 and the drift region 204.

In some embodiments, the field plate 408 may include a first metal material 410 and a second metal material 412. The first metal material 410 may include a glue layer disposed along the outer edge of the field plate 408, and the second metal material 412 is embedded in the first metal material 410 in the inner region of the field plate 408 (that is, the second The metal material 412 is separated from the CESL 406 by the first metal material 410). In some embodiments, the liner layer 414 may be disposed between the first ILD layer 118 and the first metal material 410.

In some embodiments, the first metal material 410 disposed along the outer edge of the field plate 408 has a top surface disposed along a substantially flat surface 420 (ie, a flat surface formed by a planarization process). The flat surface 420 may be aligned with the top surface of the plurality of contacts 120. In some embodiments, the first metal material 410 includes the same material as the plurality of contacts 120, and the second metal material 412 includes the same material as the first metal wire layer 418 overlying the plurality of contacts 120. For example, in some embodiments, the first metal material 410 may include tungsten (W), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the second metal material 412 may include copper (Cu) or aluminum copper (AlCu).

It should be understood that since the disclosed field plate is integrated with the back end of line (BEOL) metallization layer, the disclosed field plate allows various field plate biasing configurations to easily implement different design considerations. For example, the field plate bias can be changed by changing the metal wiring layer instead of changing the design of the disclosed high-voltage device. In addition, it should be understood that the use of BEOL metal interconnect wiring to bias the high-voltage transistor element allows the use of a single manufacturing process flow to integrate multiple field plate bias configurations on the same chip.

5 to 6 show cross-sectional views of some embodiments of field plate bias configurations for high-voltage transistor devices achieved by BEOL metal interconnect wiring. Although FIGS. 5 to 6 illustrate the connection between the field plate 214 and the contact region 208 or the gate electrode 108 via the first metal line layer (for example, the first metal line layer 504 or the first metal line layer 604), The BEOL metal interconnection wiring is not limited to this. Specifically, it should be understood that the field plate 214 can be connected to the source region by any combination of BEOL metal interconnect layers (for example, the first metal line layer, the first metal via layer, the second metal line layer, etc.) , Gate electrode, drain area or bulk contact.

FIG. 5 shows a cross-sectional view of the high-voltage LDMOS device 500 in which the field plate 214 is electrically coupled to the contact area 208 along the conductive path 506. The field plate 214 is connected to the first metal line layer 504 disposed in the second ILD layer 502. The first metal line layer 504 is coupled to the contact 120 a adjacent to the contact area 208. By electrically coupling the field plate 214 to the contact area 208, the field plate 214 is biased by the source voltage. The field plate 214 is biased by the source voltage to provide low on-state resistance (Rds(on)) and low dynamic power dissipation (for example, low Rds(on) relative to BV). on) *Qgd) high-voltage LDMOS element 500. Low dynamic power dissipation provides good performance during high frequency switching applications.

FIG. 6 shows a cross-sectional view of the high-voltage LDMOS device 600 in which the field plate 214 is electrically coupled to the gate electrode 108 along the conductive path 606. The field plate 214 is connected to the first metal line layer 604 disposed in the second ILD layer 602. The first metal wire layer 604 is connected to the contact 120 b adjacent to the gate electrode 108. By electrically coupling the field plate 214 to the gate electrode 108, the field plate 214 is biased by the gate voltage. By biasing the field plate 214 by the gate voltage, a high-voltage LDMOS device 600 with a low Rds(on) relative to the breakdown voltage can be provided.

Multiple field plate bias configurations can allow the disclosed field plate to form a multi-functional high-voltage transistor element, which can be used in different applications. For example, the on-state impedance Rds(on) of a high-voltage transistor element with a gate bias field plate is lower than that of a high-voltage transistor with a source bias field plate. Rds(on) of the crystal element. However, the Rds(on)*Qgd of the high-voltage transistor element with the source bias field plate is lower than the Rds(on)*Qgd of the high-voltage transistor element with the gate source bias field plate. Therefore, high-voltage transistor elements with gate bias field plates (e.g., high-voltage LDMOS element 500) can be used for low-frequency switching applications (e.g., below 10 MHz), and source bias field plates (e.g., high-voltage LDMOS The high-voltage transistor element of element 600) can be used for high-frequency switching applications (for example, higher than 10 MHz).

7A to 7C show cross-sectional views of some embodiments of the high-voltage LDMOS device 700a to the high-voltage LDMOS device 700c in different switching isolation configurations.

As shown in FIG. 7A, the high-voltage LDMOS element 700a is configured as a low-side switch (for example, a switch connected to the ground in the inverter). In such a configuration, the high-voltage LDMOS element 700a has a floating source region 104 so that the voltage on the source region 104 can be changed during the switching period.

As shown in FIG. 7B, the high-voltage LDMOS element 700b is configured as a high-side switch (for example, a switch connected to VDD in the inverter). In such a configuration, the high-voltage LDMOS element 700b has a source region 104 connected to a source voltage. The high-voltage LDMOS device 700b has a drift region 702 that extends below the body region 202 to prevent charge carriers from traveling from the contact region 208 to the semiconductor substrate 102 (for example, by punch through) To prevent The source voltage rises above the base voltage.

As shown in FIG. 7C, the high-voltage LDMOS device 700c is completely isolated from the substrate to allow independent bias. The high piezoelectric crystal element 700c includes a deep well 704 and an oppositely doped underlying buried layer 706 configured to provide vertical isolation. In some embodiments, the deep well 704 may have a first doping type (for example, the same doping type as the body region 202), and the buried layer 706 may have a second doping type.

The high-voltage LDMOS device 700c further includes one or more additional STI regions 206, which laterally separate the drain region from the bulk region 708 and the buried layer 710 having the second doping type. The base region 708 is overlying the deep well 704, and the buried layer 710 is overlying the well region 712, which has the second doping type and is adjacent to the buried layer 706. The multiple contacts 120 are used to provide a bias voltage for the base region 708 and the buried layer 710 to form the deep well 704 and the junction isolation between the buried layer 706 and the well region 712. The junction isolation allows the fully isolated high-voltage LDMOS element 700c to operate in a range above the bias voltage.

FIG. 8 shows a cross-sectional view of a high-voltage transistor device 800 with a source downward (source downward) field plate 214.

The high piezoelectric crystal element 800 includes a substrate 802 having a first doping type (for example, a p+ doping type) with a high doping concentration. The source region 804 is disposed along the backside 802b of the substrate 802. In various embodiments, the source region 804 may include a highly doped region or a metal layer. The epitaxial layer 806 having the first conductivity type is disposed on the front surface 802f of the substrate 802. The dopant concentration of the epitaxial layer 806 is less than the dopant concentration of the substrate 802. The source contact region 810, the drain region 106, the body region 808, and the drift region 204 are disposed in the top surface of the epitaxial layer 806.

The conductive material 812 extends from the top surface of the epitaxial layer 806 to the substrate 802. The conductive material 812 may include a highly doped deep well region. The conductive material 812 allows the source connection to the backside of the substrate 802 to be made, thereby reducing the complexity of metal wiring and realizing various package compatibility. In some embodiments, the field plate 214 can be biased by a source voltage by means of an electrical path 818 that extends through the contact 814 adjacent to the conductive material 812 and is coupled to the field plate 214 Cladding metal wire layer 816.

9A to 9B show some embodiments of the disclosed high-voltage LDMOS device having a field plate 902 in the metal line layer. Although FIGS. 9A to 9B show the field plate as being located on the first metal line layer, it should be understood that the disclosed field plate is not limited to the first metal line layer, but can be implemented on an alternative layer of the BEOL metallization stack.

As shown in the cross-sectional view 900 of FIG. 9A, the field plate 902 is disposed in the first metal line layer in the second ILD layer 904 overlying the first ILD layer 118. In some embodiments, the field plate 902 has substantially flat top and bottom surfaces, thereby providing the field plate 902 with a flat topology. The field plate 902 is vertically separated from the gate structure 210 and the drift region 204 by means of the first ILD layer 118. The field plate 902 covers the gate electrode 108 and the drift region 204 and is laterally separated from the source region 104 and the drain region 106. For example, the field plate 902 can be separated laterally from the drain region 106 by a distance d. In some embodiments, the field plate 902 may extend laterally from above the gate electrode 108 to above the drift region 204.

As shown in the top view 906 of FIG. 9B, the field plate 902 includes a metal structure overlying portions of the gate electrode 108 and the drift region 204. The metal structure is not connected to the underlying element or to another metal structure on the first metal line layer by means of the contact 120. Specifically, the metal structure will be connected to an overlying via (not shown) configured to connect the field plate to the overlying metal line layer, and the overlying metal line layer will bias the field plate 902.

FIG. 10 shows some embodiments of the disclosed high-voltage LDMOS device 1000 having a self-aligned drift region 1002.

The self-aligned drift region 1002 has sidewalls 1002s that are substantially aligned with the sidewalls of the gate electrode 108 and the gate dielectric layer 110. In certain alternative embodiments, the self-aligned drift region 1002 may be formed to have sidewalls 1002s that are substantially aligned with the edges of the sidewall spacers 212. By aligning the self-aligned drift region 1002 with the sidewalls of the gate electrode 108 and the gate dielectric layer 110, the self-aligned drift region 1002 is laterally separated from the body region 202 by the spacing s, thereby making the gate-drain The pole overlap is minimized and low gate-drain charge (Qgd) and good high frequency performance are achieved. The field plate 214 overlying the self-aligned drift region 1002 can further reduce the gate-drain charge (Qgd).

FIG. 11 shows a flowchart of some embodiments of a method 1100 of forming a high-voltage transistor element with a field plate. The method can use process steps that have been used during the standard CMOS manufacturing process to form the field plate, and thus can provide a low-cost, multi-functional field plate.

Although the disclosed methods (such as method 1100 and method 3300) are illustrated and described herein as a series of actions or events, it should be understood that the illustrated sequence of such actions or events should not be interpreted in a restrictive sense. For example, in addition to the actions or events illustrated and/or described herein, some actions may occur in a different order and/or simultaneously with other actions or events. In addition, not all of the illustrated actions may be required to implement one or more aspects or embodiments described herein. In addition, one or more of the actions described herein may be performed in one or more separate actions and/or stages.

At 1102, the substrate is provided with a source region and a drain region separated by a channel region. In some embodiments, the substrate may further include a drift region, which is located adjacent to the channel A drift region between the source region and the drain region at the location of the region.

At 1104, a gate structure is formed over the substrate at a position between the source region and the drain region. The gate structure may include a gate dielectric layer and an overlying gate electrode.

At 1106, a self-aligned process can be used to form the drift region. In some embodiments, the self-aligned process selectively lays out the semiconductor substrate according to the gate structure to form the drift region.

At 1108, one or more dielectric layers are selectively formed over the gate electrode and a portion of the drift region.

At 1110, a contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer are formed over the substrate.

At 1112, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings.

At 1114, the plurality of contact openings and field plate openings are filled with the first metal material.

At 1116, a planarization process may be performed to remove excess first metal material overlying the first ILD layer.

At 1118, a second metal material corresponding to the first metal line layer is deposited. In some embodiments, the second metal material may further fill the field plate opening. In such embodiments, the second metal material is embedded in the first metal material in the opening of the field plate.

At 1120, a second interlayer dielectric (ILD) layer is formed over the first ILD layer and over the first metal line layer structure.

12-19 show cross-sectional views of some embodiments of methods of forming MOSFET devices with field plates. Although FIGS. 12 to 19 are described with reference to the method 1100, it should be understood that the structures disclosed in FIGS. 12 to 19 are not limited to such methods, but instead Can be used alone as a structure independent of the method.

FIG. 12 shows some embodiments of a cross-sectional view 1200 corresponding to action 1102.

As shown in the cross-sectional view 1200, a semiconductor substrate 102 is provided. The semiconductor substrate 102 may be intrinsically doped to have the first doping type. In various embodiments, the semiconductor substrate 102 may include any type of semiconductor body (for example, silicon, SOI), which includes but is not limited to a semiconductor chip or a wafer or one or more dies on the wafer, and any other type The semiconductor and/or the epitaxial layer formed thereon and/or otherwise associated with it.

Various implantation steps can be used to selectively pattern the semiconductor substrate 102 to form a plurality of implant regions (for example, well regions, contact regions, etc.). For example, the semiconductor substrate 102 can be selectively patterned to form the body region 202, the drift region 204, the source region 104, the drain region 106, and the contact region 208. The semiconductor substrate 102 can be selectively shielded (for example, using a photoresist mask) and then high-energy dopants 1204 (for example, p-type dopant species such as boron; or n-type dopants such as phosphorous ) Is introduced into the exposed area of the semiconductor substrate 102 to form a plurality of implanted regions. For example, as shown in the cross-sectional view 1200, the mask layer 1202 is selectively patterned to expose a portion of the semiconductor substrate 102, and a high-energy dopant 1204 is then implanted into the portion to form a source region 104 and the drain region 106.

It should be understood that the implanted region shown in the cross-sectional view 1200 is an example of a possible implanted region, and the semiconductor substrate 102 may include other configurations of implanted regions, such as those shown in FIGS. 1 to 10 Any one of the incoming zones.

FIG. 13 shows some embodiments of a cross-sectional view 1300 corresponding to action 1104.

As shown in the cross-sectional view 1300, the gate structure 210 is formed above the semiconductor substrate 102 at a position between the source region 104 and the drain region 106. The gate structure 210 may be formed by forming a gate dielectric layer 110 on the semiconductor substrate 102 and by forming a gate electrode material 108 on the gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 and the gate electrode material 108 may be deposited by vapor deposition technology. The gate dielectric layer 110 and the gate electrode material 108 may be subsequently patterned and etched (eg, according to a photoresist mask) to define the gate structure 210. In some embodiments, a nitride or oxide-based material may be deposited on the semiconductor substrate 102 and the nitride or oxide-based material may be selectively etched to form the sidewall spacers 212 to form the sidewall spacers 212 on the gate electrode 108. Side wall spacers 212 are formed on the opposite side.

FIG. 14 shows some embodiments of a cross-sectional view 1400 corresponding to action 1108.

As shown in the cross-sectional view 1400, one or more dielectric layers 124 are selectively formed over the gate electrode 108 and the drift region 204. In some embodiments, one or more dielectric layers 124 may be deposited by vapor deposition techniques, and then patterned and etched (for example, according to a photoresist mask). In some embodiments, one or more dielectric layers 124 may be etched to expose a portion of the gate electrode 108 and spaced laterally from the drain region 106.

In some embodiments, the one or more dielectric layers 124 may include a silicide barrier layer, such as a photoresist protective oxide (RPO) layer. In other embodiments, the one or more dielectric layers 124 may further and/or alternatively include a field plate etch stop layer (ESL). In some embodiments, the field plate ESL may be a silicon nitride (SiN) layer formed by vapor deposition technology. In still other embodiments, the one or more dielectric layers 124 may further and/or alternatively include a gate dielectric layer or an interlayer dielectric (ILD) layer.

FIG. 15 shows some embodiments of a cross-sectional view 1500 corresponding to action 1110.

As shown in the cross-sectional view 1500, a contact etch stop layer (CESL) 1502 is formed over the semiconductor substrate 102. In some embodiments, CESL 1502 can be formed by a vapor deposition process. A first interlayer dielectric (ILD) layer 1504 is subsequently formed over CESL 1502. In some embodiments, the first ILD layer 1504 may include an ultra-low dielectric constant dielectric material or a low dielectric constant dielectric material (for example, SiCO). In some embodiments, the first ILD layer 1504 can also be formed by a vapor deposition process. In other embodiments, the first ILD layer 1504 may be formed by a spin coating process. It should be understood that the term inter-layer dielectric (ILD) layer as used herein may also refer to inter-metal dielectric (IMD) layer.

FIG. 16 shows some embodiments of a cross-sectional view 1600 corresponding to action 1112.

As shown in the cross-sectional view 1600, the first ILD layer 1504 is selectively exposed to the first etchant 1602, which is used to form the contact opening 1606 and the field plate opening 1608. In some embodiments, the contact opening 1606 may be smaller than the field plate opening 1608. In some embodiments, the first ILD layer 1504 is selectively exposed to the first etchant 1602 according to the mask layer 1604 (for example, a photoresist layer or a hard mask layer). In some embodiments, the first etchant 1602 may have a large etching selectivity between the first ILD layer 1504 in the one or more dielectric layers 124 and the field plate ESL. In some embodiments, the first etchant 1602 may include a dry etchant. In some embodiments, the dry etchant may have an etching chemical substance including oxygen (oxygen; O ₂ ), nitrogen (nitrogen; N ₂ ), hydrogen (hydrogen; H ₂ ), argon (argon; Ar). ) And/or one or more of fluorine species (for example, CF ₄ , CHF ₃ , C ₄ F _8, etc.). In other embodiments, the first etchant 1602 may include a wet etchant including buffered hydroflouric acid (BHF).

FIG. 17 shows some embodiments of the cross-sectional view 1700 corresponding to actions 1114 to 1116.

As shown in the cross-sectional view 1700, the contact opening 1606 and the field plate opening 1608 are filled with a first metal material 1702. In some embodiments, the first metal material 1702 may be deposited by means of vapor deposition techniques (eg, CVD, PVD, PE-CVD, etc.). In some embodiments, the first metal material 1702 may be formed by depositing a seed layer by means of physical vapor deposition before a plating process (for example, an electroplating or an electroless plating process). A planarization process (for example, chemical mechanical planarization) may be subsequently performed to remove the excess first metal material 1702 and to form a flat surface along the line 1704.

In some embodiments, the first metal material 1702 may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the diffusion barrier layer and/or the liner layer may be deposited into the contact opening 1606 and the field plate opening 1608 before depositing the first metal material 1702.

FIG. 18 shows some embodiments of a cross-sectional view 1800 corresponding to action 1118.

As shown in the cross-sectional view 1800, a second metallic material 1802 is deposited. The second metal material 1802 is formed in the remaining openings in the field plate openings and above the first ILD layer 118. In some embodiments, the second metal material 1802 may be deposited by means of vapor deposition techniques (eg, CVD, PVD, PE-CVD, etc.). In some embodiments, the second metal material 1802 can be formed by depositing a seed layer by means of physical vapor deposition before the plating process. In some embodiments, the second metal material 1802 may include copper (Cu) or aluminum copper (AlCu) alloy.

After formation, the second metal material 1802 can be selectively patterned to define one or more metal structures overlying the first metal line layer 418 of the first ILD layer 118. In some embodiments, a patterned mask layer (for example, a photoresist layer or a hard mask layer) (not shown) may be formed over the second metal material 1802 and then aligned with the patterned mask layer The second metal material 1802 in the exposed area is etched to selectively pattern the second metal material 1802.

FIG. 19 shows some embodiments of a cross-sectional view 1900 corresponding to action 1120.

As shown in the cross-sectional view 1900, the second ILD layer 416 is formed over the one or more metal structures of the first ILD layer 118 and the first metal line layer 418. In various embodiments, the second ILD layer 416 may be formed by depositing a second ILD material over one or more metal structures of the first ILD layer 118 and the first metal line layer 418. After the second ILD layer 416 is formed, a planarization process (for example, CMP) is performed to remove the excess second ILD layer 416 and expose the top surface of one or more metal structures of the first metal line layer 418. In various embodiments, the second ILD layer 416 may include an ultra-low dielectric constant dielectric material or a low dielectric constant dielectric material (for example, SiCO) formed by a vapor deposition processor or a spin coating process. .

It should be understood that the height difference of the plurality of contacts (for example, the contact 120) and the field plate (for example, the field plate 122) may cause difficulties during the manufacturing of the disclosed transistor device. For example, since the field plate (e.g., field plate 122) is formed over the dielectric layer 124 (e.g., photoresist protective oxide), the field plate (e.g., field plate 122) has more contacts (e.g., The contact 120) is smaller in height. However, the same etching process is used to form a field plate (for example, the field plate 122) and a plurality of contacts (for example, the contact 120). The height difference can cause excessive field plate openings (for example, field plate opening 1608 of FIG. 16) Over-etching or under-etching of contact openings (for example, contact opening 1606 of FIG. 16), the over-etching leads to conductive paths between the field plate (for example, the field plate 122) and the transistor element The incomplete etching results in multiple contacts (for example, contact 120) and source regions (for example, source region 104), drain regions (for example, drain region 106), and/or Poor connection between gate regions (eg, gate region 116).

To prevent over-etching of the field plate openings or incomplete etching of the contact openings, in some embodiments, a composite etch stop layer can be used to control the etching depth of the field plate openings. By controlling the etching depth of the field plate opening, the composite etch stop layer allows the multiple contacts (for example, the contact 120) and the field plate (for example, the field plate 122) to be accurately formed to have different heights.

FIG. 20 shows a cross-sectional view of some embodiments of the disclosed high voltage transistor device 2000 with a composite etch stop layer defining a field plate.

The high-voltage crystal element 2000 includes a gate structure 116 disposed on the semiconductor substrate 102. The gate structure 116 includes a gate dielectric layer 110 and an overlying gate electrode 108. In some embodiments, the gate structure 116 may have a first thickness th _{1 in} a range between about 1000 angstroms and about 2000 angstroms. The source region 104 and the drain region 106 are disposed in the semiconductor substrate 102 on opposite sides of the gate structure 116.

The photoresist protective oxide (RPO) 2002 is disposed above the gate structure 116. The RPO 2002 extends from directly above the gate structure 116 to laterally beyond the outermost sidewall of the gate structure 116. In some embodiments, the RPO 2002 may extend vertically from the upper surface of the gate structure 116 to the upper surface of the semiconductor substrate 102, and extend laterally from directly above the gate structure 116 to between the gate structure 116 and the drain region 106 between. In some embodiments, RPO 2002 may include silicon dioxide, silicon nitride, or the like. In some embodiments, the RPO 2002 may have a second thickness th _{2 in} a range between about 100 angstroms and about 1000 angstroms.

The composite etch stop layer 2004 is disposed above the RPO 2002. In some embodiments, the composite etch stop layer 2004 directly contacts one or more upper surfaces of the RPO 2002. The first interlayer dielectric (ILD) layer 118 and the field plate 122 are disposed above the composite etch stop layer 2004. The first ILD layer 118 surrounds the field plate 122 and a plurality of contacts 120 that are coupled to the source region 104, the drain region 106 and the gate structure 116. In some embodiments, the field plate 122 and the plurality of contacts 120 may include diffusion barriers (not shown) surrounding a conductive core that includes one or more metals.

The composite etch stop layer 2004 includes a plurality of different dielectric materials 2006 to 2008 stacked on the RPO 2002. In some embodiments, the plurality of different dielectric materials 2006 to 2008 may have outermost sidewalls that are substantially aligned along a line perpendicular to the upper surface of the semiconductor substrate 102. In some embodiments, the plurality of different dielectric materials 2006 to 2008 may have the outermost sidewall that is substantially aligned with the outermost sidewall of the RPO 2002. In such embodiments, the RPO 2002 has a first width that is substantially equal to the second width of the composite etch stop layer 2004. The plurality of different dielectric materials 2006 to 2008 have different etching characteristics, and the etching characteristics provide different etching selectivities to the etchant for corresponding ones of the plurality of different dielectric materials 2006 to 2008. Different etch selectivities can allow the composite etch stop layer 2004 to slow down the etching of the field plate opening (ie, the opening that defines the field plate 122), and thus tightly control the height of the field plate and allow multiple contacts 120 and the field plate 122 (For example, allowing multiple contacts 120 to have a higher height than the field plate 122).

For example, in some embodiments, the bottom of the field plate 122 along the interface and The composite etch stop layer 2004 contacts the interface vertically higher than the bottom surface of one or more of the plurality of contacts 120 (eg, contacts coupled to the source region 104 and the drain region 106). In such embodiments, during the manufacture of the high-voltage transistor element 2000, the composite etch stop layer 2004 reduces the etching rate of the etchant used to form the field plate openings (ie, the openings that define the field plate 122). The reduction in the etching rate causes the field plate 122 to have a bottom surface that is higher than the bottom surface of one or more of the plurality of contacts 120.

In some embodiments, the composite etch stop layer 2004 may include a first dielectric material 2006 in direct contact with the upper surface of the RPO 2002 and a second dielectric material 2008 in direct contact with the upper surface of the first dielectric material 2006. In some embodiments, the first dielectric material 2006 may have a third thickness th ₃ , and the second dielectric material 2008 may have a fourth thickness th ₄ . In some embodiments, the RPO 2002 and the composite etch stop layer 2004 may each have a substantially continuous thickness between the outermost sidewalls. If the third thickness th ₃ and the fourth thickness th _{4 are} too small (for example, less than the minimum value described below), the composite etch stop layer 2004 cannot effectively terminate the etching to form the field plate opening. If the third thickness th ₃ and the fourth thickness th _{4 are} too large (for example, greater than the maximum value described below), the effect of the field plate 122 on the high-voltage transistor device 2000 is reduced, thereby adversely affecting the device performance.

In some embodiments, the first dielectric material 2006 may include or may be silicon nitride (Si _x N _y ), and the second dielectric material 2008 may include or may be silicon dioxide (SiO ₂ ). In such embodiments, the first thickness th ₁ may be within a first range between about 50 angstroms and about 400 angstroms, and the second thickness th ₂ may be between about 150 angstroms and about 700 angstroms. 2. Within the scope. In other embodiments, the first dielectric material 2006 may include or may be _{silicon dioxide (SiO 2} ), and the second dielectric material 2008 may include or may be silicon nitride (SiN _x ) or silicon oxynitride (SiO 2) _x N _y ). In such embodiments, the first thickness th ₁ may be in a first range between about 600 angstroms and about 900 angstroms. In some embodiments, the second thickness th ₂ may be in a second range between about 100 angstroms and about 500 angstroms.

21A to 21B show some other embodiments of the disclosed high voltage transistor device with a composite etch stop layer defining a field plate.

As shown in the cross-sectional view 2100 of FIG. 21A, the high-voltage transistor element includes a semiconductor substrate 102 having a body region 2106 disposed in a drift region 2104 above the substrate 2102. The source region 104 is disposed in the body region 2106, and the drain region 106 is disposed in the drift region 2104. In some embodiments, the source region 104, the drain region 106, and the drift region 2104 may have a first doping type (for example, n-type), and the body region 2106 and the substrate 2102 have a second doping type opposite to the first doping type. Two-doped type (for example, p-type). In some embodiments, the source region 104 and the drain region 106 may include highly doped regions (ie, n+ regions) with a higher doping concentration than the drift region 2104.

The gate structure 116 is disposed above the semiconductor substrate 102 between the source region 104 and the drain region 106. The RPO 2002 is disposed above the gate structure 116 and extends laterally beyond the outermost sidewall of the gate structure 116. The composite etch stop layer 2004 is disposed between the RPO 2002 and the field plate 122. In some embodiments, the RPO 2002 may enclose the field plate 122 (ie, extend beyond the outermost sidewall of the field plate 122) at one or more lateral distances 2108, the lateral distance being between about 0 microns and about 2 microns. Within the range of time.

In some embodiments, the field plate 122 may extend a non-zero depth 2110 into the composite etch stop layer 2004. In such embodiments, the field plate 122 contacts the sidewalls of the composite etch stop layer 2004. In various embodiments, the field plate 122 may also contact the horizontally extending surface of the composite etch stop layer 2004 or the horizontally extending surface of the RPO 2002. in In some embodiments, the non-zero depth 2110 may be in a range between about 400 angstroms and about 700 angstroms. Since the field plate 122 extends into the composite etch stop layer 2004, the composite etch stop layer 2004 has a first thickness 2112 directly below the field plate 122 and a second thickness greater than the first thickness 2112 outside the field plate 122. In some embodiments, the first thickness 2112 is in a range between about 0 angstroms and about 10000 angstroms. In some other embodiments, the first thickness 2112 is in a range between about 600 angstroms and about 300 angstroms.

As shown in the top view 2120 of FIG. 21B (along the cross-sectional line AA' of FIG. 21A), the field plate 122 has a width 2114 that extends a certain distance in the first direction, and the distance is in the range of about 150 nanometers. Between meters and about 2000 nanometers. The field plate 122 also has a length 2122 that extends in the second direction (perpendicular to the first direction) at a distance of less than about 1000 microns.

Referring again to the cross-sectional view 2100 of FIG. 21A, in some embodiments, the field plate 122 may be separated laterally from the gate structure 116 by a distance 2116. For example, the field plate 122 may be separated laterally from the gate structure 116 by a distance 2116 in a range between about 0 nanometers and about 500 nanometers. In other embodiments (not shown), the field plate 122 may overlap the gate structure 116 laterally (that is, extend directly above). For example, the field plate 122 may laterally overlap the gate structure 116 by a distance in a range between about 0 nanometers and about 200 nanometers.

In some embodiments, the silicide layer 2118 is disposed on the source region 104, the drain region 106, and the portion of the gate structure 116 not covered by the RPO 2002. In various embodiments, the silicide layer 2118 may include a compound having silicon and a metal, such as nickel, platinum, titanium, tungsten, magnesium, or the like. In some embodiments, the silicide layer 2118 has a thickness between about 150 angstroms and The thickness ranges between about 400 angstroms.

FIG. 22 shows a cross-sectional view of some other embodiments of the disclosed high-voltage transistor device 2200 with a composite etch stop layer defining a field plate.

The high-voltage crystal element 2200 includes a gate electrode 108 disposed above the semiconductor substrate 102. The RPO 2002 and the composite etch stop layer 2004 are located above the gate electrode 108 and the semiconductor substrate 102. A contact etch stop layer (CESL) 406 is disposed above the composite etch stop layer 2004. In some embodiments, the bottom surface of the composite etch stop layer 2004 may directly contact the RPO 2002, and the top surface of the composite etch stop layer 2004 may directly contact the CESL 406. The CESL 406 extends laterally beyond the outermost sidewall of the composite etch stop layer 2004 and contacts the semiconductor substrate 102. In some embodiments, CESL 406 may have a thickness th _{5 in} a range between about 100 angstroms and about 1000 angstroms. In some embodiments, CESL 406 may include silicon nitride, silicon carbide, or the like.

The field plate 408 is disposed in the first ILD layer 118 above the CESL 406. In some embodiments, the field plate 408 may include a first metal material 410 and a second metal material 412. The composite etch stop layer 2004 is disposed laterally between the field plate 408 and the gate structure 116, and vertically disposed between the field plate 122 and the semiconductor substrate 102. The RPO 2002 and the composite etch stop layer 2004 have sidewalls in contact with the CESL 406. The composite etch stop layer 2004 further has a horizontally extending surface (for example, an upper surface) in contact with the CESL 406.

In some embodiments, the field plate 122 may extend into one or more of a plurality of different dielectric materials 2006 to 2008 in the composite etch stop layer 2004. For example, in some embodiments, the composite etch stop layer 2004 may include a first dielectric material 2006 and a second dielectric material 2006 in contact with the upper surface of the first dielectric material 2006. Dielectric Materials 2008. The field plate 122 may extend through the second dielectric material 2008 (for example, silicon oxide) and have a bottom surface in contact with the first dielectric material 2006 (for example, silicon nitride). In such an embodiment, the second dielectric material 2008 can vertically separate the bottommost point of the field plate 122 from the RPO 2002. In other embodiments, the field plate 122 may further extend through the first dielectric material 2006 and have a bottom surface and/or sidewalls in contact with the RPO 2002. In some embodiments, the field plate 122 may extend vertically through the second dielectric material 2008, and is also laterally separated from the gate structure 116 by the second dielectric material 2008.

Although the disclosed composite etch stop layer 2004 is shown in FIGS. 20-22 as having two different dielectric materials 2006 to 2008 stacked on the RPO 2002, it should be understood that the disclosed composite etch stop layer 2004 is not limited to this type of configuration. Specifically, in various embodiments, the composite etch stop layer 2004 may include other layers of dielectric materials. Figures 23-24 show some non-limiting examples of alternative embodiments of the disclosed composite etch stop layer 2004.

FIG. 23 shows a cross-sectional view of some other embodiments of the disclosed high voltage transistor device 2300 with a composite etch stop layer defining a field plate.

The high-voltage crystal element 2300 includes a composite etch stop layer 2004 disposed above the RPO 2002. The composite etch stop layer 2004 includes a first dielectric material 2302, a second dielectric material 2304 in contact with the upper surface of the first dielectric material 2302, and a third dielectric material 2306 in contact with the upper surface of the second dielectric material 2304 . In some embodiments, the first dielectric material 2302 may include or may be _{silicon dioxide (SiO 2} ), and the second dielectric material 2304 may include or may be silicon nitride (Si _x N _y ) or silicon oxynitride ( SiO _x N _y ), and the third dielectric material 2306 may include or may be silicon dioxide (SiO ₂ ).

In some embodiments, the first dielectric material 2302 may have a first thickness, The second dielectric material 2304 may have a second thickness, and the third dielectric material 2306 may have a third thickness. In some embodiments, the first thickness may be in a first range between about 300 angstroms and about 900 angstroms, the second thickness may be in a second range between about 50 angstroms and about 200 angstroms, and the first thickness The third thickness may be in a third range between about 200 angstroms and about 600 angstroms.

FIG. 24 shows a cross-sectional view of some other embodiments of the disclosed high-voltage transistor element 2400 with a composite etch stop layer defining a field plate.

The high-voltage crystal element 2400 includes a composite etch stop layer 2004 disposed above the RPO 2002. The composite etch stop layer 2004 includes a first dielectric material 2402, a second dielectric material 2404 in contact with the upper surface of the first dielectric material 2402, and a third dielectric material 2406 in contact with the upper surface of the second dielectric material 2404 And the fourth dielectric material 2408 in contact with the upper surface of the third dielectric material 2406. In some embodiments, the first dielectric material 2402 may include or may be _{silicon dioxide (SiO 2} ), and the second dielectric material 2404 may include or may be silicon nitride (Si _x N _y ) or silicon oxynitride ( SiO _x N _y ), the third dielectric material 2406 may include or may be _{silicon dioxide (SiO 2} ), and the fourth dielectric material 2408 may include or may be silicon nitride (Si _x N _y ) or silicon oxynitride (SiO _x N _y ).

In some embodiments, the first dielectric material 2402 may have a first thickness, the second dielectric material 2404 may have a second thickness, the third dielectric material 2406 may have a third thickness, and the fourth dielectric material 2408 may Has a fourth thickness. In some embodiments, the first thickness may be in a first range between about 300 angstroms and about 900 angstroms, the second thickness may be in a second range between about 50 angstroms and about 200 angstroms, and the third The thickness may be in a third range between about 200 angstroms and about 600 angstroms, and the fourth thickness may be in a fourth range between about 50 angstroms and about 200 angstroms.

25 to 32 show cross-sectional views of some embodiments of a method of forming a high-voltage transistor element with a composite etch stop layer defining a field plate. Although the cross-sectional view 2500 to the cross-sectional view 3200 shown in FIGS. 25 to 32 are described with reference to one method, it should be understood that the structure shown in FIGS. 25 to 32 is not limited to the method, but may be independent于说方法。 In the method.

As shown in the cross-sectional view 2500 of FIG. 25, the semiconductor substrate 102 is selectively patterned to form a plurality of implant regions (eg, well regions, contact regions, etc.). In some embodiments, the semiconductor substrate 102 may be selectively patterned to form the body region 2106, the drift region 2104, the source region 104, and the drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively patterned to form different implanted regions (for example, any of the implanted regions shown in FIGS. 1 to 10). In some embodiments, the semiconductor substrate 102 can be selectively shielded (for example, using a photoresist mask) and then high-energy dopants (for example, p-type dopant species such as boron; or n-type dopants) A dopant, such as phosphorous, is introduced into the exposed area of the semiconductor substrate 102 to form a plurality of implanted regions.

The gate structure 116 is formed on the semiconductor substrate 102 between the source region 104 and the drain region 106. The gate structure 116 can be formed by depositing a gate dielectric layer 110 on the semiconductor substrate 102 and by depositing a gate electrode material 108 on the gate dielectric layer 110. The gate dielectric layer 110 and the gate electrode material 108 may then be patterned (eg, etched according to a photoresist mask and/or a hard mask) to define the gate structure 116.

As shown in the cross-sectional view 2600 of FIG. 26, a photoresist protective oxide (RPO) 2002 is formed over the gate structure 116. The RPO 2002 extends laterally from directly above the gate structure 116 to exceed the outermost sidewall of the gate structure 116. RPO 2002 is configured to block the formation of silicide on the underlying layer. In some embodiments, RPO 2002 may be deposited by vapor deposition technology (eg, CVD). In some embodiments, RPO 2002 may include _{silicon dioxide (SiO 2} ), silicon nitride, or the like.

As shown in the cross-sectional view 2700 of FIG. 27, a composite etch stop layer 2004 including a plurality of different dielectric materials 2006 to 2008 is selectively formed over the RPO 2002. In some embodiments, a plurality of different dielectric materials 2006 to 2008 may be sequentially deposited by vapor deposition technology. In some embodiments, the composite etch stop layer 2004 may include a stacked layer including a silicon nitride (Si _x N _y ) layer, a silicon oxynitride (SiO _x N _y ) layer, and a _{silicon dioxide (SiO 2} ) layer. Two or more than two of the layers.

In some embodiments, the same mask layer 2702 (for example, a photoresist layer) and an etching process can be used to pattern a plurality of different dielectric materials 2006 to 2008 and RPO 2002. Using the same mask layer 2702 to pattern a plurality of different dielectric materials 2006 to 2008 and RPO 2002 can reduce the cost of forming the composite etch stop layer 2004. In such embodiments, the plurality of different dielectric materials 2006 to 2008 and RPO 2002 may have substantially aligned sidewalls.

As shown in the cross-sectional view 2800 of FIG. 28, a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the composite etch stop layer 2004. In some embodiments, the CESL 406 may be formed by a vapor deposition process. The CESL may include a nitride layer (for example, Si ₃ N ₄ ), a carbide layer (SiC), or the like.

As shown in the cross-sectional view 2900 of FIG. 29, a first interlayer dielectric (ILD) layer 118 is formed over the CESL 406. In some embodiments, the first ILD layer 118 may include an oxide (for example, SiO ₂ ), an ultra-low dielectric constant dielectric material, a low dielectric constant dielectric material (for example, SiCO), or the like. In some embodiments, the first ILD layer 118 may be formed by a vapor deposition process.

As shown in the cross-sectional view 3000 of FIG. 30, the first ILD layer 118 is selectively exposed to an etchant 3002 (for example, according to the mask layer 3003) to form a plurality of contact openings 1606 and fields in the first ILD layer 118板开1608。 Board opening 1608. The contact opening 1606 and the field plate opening 1608 have a non-zero distance 3004 in the etching depth difference. In some embodiments, the non-zero distance 3004 may be in the range between about 400 angstroms and about 2000 angstroms. In some embodiments, the field plate opening 1608 extends into the composite etch stop layer 2004 so that the composite etch stops The sidewalls of layer 2004 define field plate openings 1608. In various embodiments, the composite etch stop layer 2004 or RPO 2002 may define the bottom of the field plate opening 1608.

In some embodiments, the etchant 3002 can reduce the thickness of the composite etch stop layer 2004 by an amount in a range between about 400 angstroms and about 700 angstroms. In some embodiments, the thickness of the composite etch stop layer 2004 directly below the field plate opening 1608 is in a range between about 0 angstroms and about 1,000 angstroms. In some other embodiments, the thickness of the composite etch stop layer 2004 directly below the field plate opening 1608 is in a range between about 300 angstroms and about 900 angstroms.

The etchant 3002 used to form the contact opening 1608 and the field plate opening 1608 is selected to etch through the material of the CESL 406. However, since the composite etch stop layer 2004 is formed of a plurality of different materials, the composite etch stop layer 2004 can resist etching by the etchant 3002 to a higher degree. The composite etch stop layer 2004 in turn allows the contact opening 1606 to extend to the semiconductor substrate 102 while preventing the field plate opening 1608 from extending to the semiconductor substrate 102. The composite etch stop layer 2004 also allows high uniformity of the etching depth at different positions on a substrate, between multiple substrates of the same lot, and/or above multiple substrates of different batches. For example, the composite etch stop layer 2004 allows the etch depth of field plate openings 1608 on different substrates to be within a deviation of about 2% or less. This uniformity of etch depth allows for improved device uniformity and performance beyond devices that do not have a composite etch stop layer 2004.

As shown in the cross-sectional view 3100 of FIG. 31, a plurality of contact openings 1606 and field plate openings 1608 are filled with one or more conductive materials. In some embodiments, one or more conductive materials may be deposited by means of vapor deposition techniques (eg, CVD, PVD, PE-CVD, etc.) and/or plating processes (eg, electroplating or electroless plating processes). A planarization process (for example, chemical mechanical planarization) may be subsequently performed to remove the excess conductive material or materials and form a flat surface along the line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), titanium (Ti), titanium nitride (TiN), and/or tantalum nitride (TaN). In some embodiments, the diffusion barrier layer and/or the liner layer may be deposited into the plurality of contact openings 1606 and the field plate openings 1608 before depositing one or more conductive materials.

As shown in the cross-sectional view 3200 of FIG. 32, the second ILD layer 126 is formed above the first ILD layer 118, and the first back end of line (BEOL) metal line layer 128 is formed in the second ILD layer 126. In various embodiments, the second ILD layer 126 may be formed by depositing a second ILD material over the first ILD layer 118. The second ILD layer 126 is then etched to form trenches extending in the second ILD layer 126. The trench is filled with conductive material, and a planarization process (for example, CMP) is performed to remove excess conductive material from above the second ILD layer 126.

FIG. 33 shows a flowchart of some embodiments of a method 3300 for forming a high-voltage transistor element having a composite etch stop layer defining a field plate.

At 3302, the gate structure is formed over the substrate. FIG. 25 shows a cross-sectional view 2500 of some embodiments corresponding to action 3302.

At 3304, the source and drain regions are formed in the substrate on opposite sides of the gate structure. In some other embodiments, one or more additional doped regions (eg, body region, drift region, etc.) may also be formed in the substrate. FIG. 25 shows a cross-sectional view 2500 corresponding to some embodiments of action 3304.

At 3306, a photoresist protective oxide (RPO) is formed above the gate structure and laterally between the gate structure and the drain region. FIG. 26 shows a cross-sectional view 2600 of some embodiments corresponding to action 3306.

At 3308, a composite etch stop layer is formed over the RPO. FIG. 27 shows a cross-sectional view 2700 of some embodiments corresponding to action 3308.

At 3310, a contact etch stop layer (CESL) is formed on the composite etch stop layer. FIG. 28 shows a cross-sectional view 2800 of some embodiments corresponding to action 3310.

At 3312, a first interlayer dielectric (ILD) layer is formed over CESL. FIG. 29 shows a cross-sectional view 2900 of some embodiments corresponding to action 3312.

At 3314, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings. The multiple contact openings and the field plate openings have different depths. FIG. 30 shows a cross-sectional view 3000 of some embodiments corresponding to action 3314.

At 3316, multiple contact openings and field plate openings are filled with one or more conductive materials. FIG. 31 shows a cross-sectional view 3100 of some embodiments corresponding to action 3316.

At 3318, conductive interconnects are formed in the second ILD layer above the first ILD layer. FIG. 32 shows a cross-sectional view 3200 of some embodiments corresponding to action 3318.

Therefore, the content of this disclosure is about a high-voltage transistor element with a field plate. The field plate and the formation of the conductive contact are formed at the same time. The element has a composite etch stop layer for realizing the height difference between the field plate and the conductive contact.

In some embodiments, the disclosure relates to an integrated wafer. The integrated chip includes: a gate structure, which is arranged above the substrate between the source region and the drain region; a dielectric layer, which extends laterally from above the gate structure to between the gate structure and the drain region; and the composite etching is terminated A layer having a plurality of different dielectric materials stacked above the dielectric layer; contacting the etch stop layer, directly contacting the upper surface of the composite etch stop layer and a plurality of sidewalls; and a field plate, which is laterally surrounded by the first ILD layer , And extend vertically from the top of the first ILD layer, extend through the contact etch stop layer, and extend into the composite etch stop layer. In some embodiments, the composite etch stop layer has a first dielectric material and a second dielectric material in contact with the upper surface of the first dielectric material. In some embodiments, the field plate extends vertically through the second dielectric material, and the field plate is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material includes silicon nitride, and the second dielectric material includes silicon dioxide. In some embodiments, the first dielectric material includes silicon dioxide, and the second dielectric material includes silicon nitride or silicon oxynitride. In some embodiments, the field plate extends vertically through the second dielectric material, and the field plate is vertically separated from the gate structure by the first dielectric material. In some embodiments, the composite etch stop layer has a first thickness directly below the field plate and has a second thickness outside the field plate. In some embodiments, the composite etch stop layer laterally contacts the multiple sidewalls of the field plate. In some embodiments, the bottom of the field plate is vertically separated from the dielectric layer by a composite etch stop layer. In some embodiments, the dielectric layer includes a photoresist protective oxide having a lower surface in contact with the gate structure and an upper surface in contact with the composite etch stop layer.

In other embodiments, the disclosure relates to an integrated chip. product The bulk wafer includes: a gate structure, which is arranged above the substrate; a photoresist protective oxide, which extends laterally from above the gate structure to beyond the outermost sidewall of the gate structure; a composite etch stop layer, which has a photoresist protective oxide above the A first dielectric material and a second dielectric material in contact with the upper surface of the first dielectric material; a plurality of conductive contacts, which are laterally surrounded by a first interlayer dielectric (ILD) layer above the substrate; and a field plate , Extending from the top of the first ILD layer to the composite etch stop layer and containing the same material as the plurality of conductive contacts, the composite etch stop layer laterally contacts the multiple sidewalls of the field plate, and the composite etch stop layer makes The bottom of the field plate is vertically separated from the photoresist protective oxide. In some embodiments, the field plate extends vertically through the second dielectric material, and the field plate is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material is an oxide, and the second dielectric material is a nitride. In some embodiments, the composite etch stop layer further includes a third dielectric material in contact with the upper surface of the second dielectric material, and the first dielectric material and the third dielectric material are the same material. In some embodiments, the integrated wafer further includes a contact etch stop layer in direct contact with the upper surface of the composite etch stop layer and the plurality of sidewalls, and the field plate extends through the contact etch stop layer. In some embodiments, the photoresist protective oxide has a first width, and the first width is substantially equal to the second width of the composite etch stop layer.

In still other embodiments, the present disclosure relates to a method of forming an integrated wafer. The method includes: forming a gate structure above the substrate between the source region and the drain region in the substrate; forming a dielectric layer above the gate structure and between the gate structure and the drain region; above the dielectric layer A composite etch stop layer is formed, the composite etch stop layer includes a plurality of stacked dielectric materials; a first interlayer dielectric (ILD) layer is formed above the composite etch stop layer; the first ILD layer is selectively etched to simultaneously define Multiple contact openings extending to the substrate and field plate openings extending to the composite etch stop layer; And filling a plurality of contact openings and field plate openings with one or more conductive materials. In some embodiments, the composite etch stop layer includes a first dielectric material and a second dielectric material in contact with the upper surface of the first dielectric material. In some embodiments, the field plate opening extends vertically through the second dielectric material, and the field plate opening is laterally separated from the gate structure by the second dielectric material. In some embodiments, the method further includes: forming a mask layer on the composite etch stop layer; and etching the composite etch stop layer and the dielectric layer according to the mask layer.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspect of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other manufacturing processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present disclosure, and those skilled in the art can make various changes in this article without departing from the spirit and scope of the present disclosure. Changes, substitutions and changes.

102‧‧‧Base

104‧‧‧Source area

106‧‧‧Dip pole area

108‧‧‧Gate electrode

110‧‧‧Gate Dielectric Layer

118‧‧‧The first interlayer dielectric layer

120‧‧‧Contact

202‧‧‧Main area

204‧‧‧Drift Zone

206‧‧‧Additional STI area

208‧‧‧Contact area

212‧‧‧Side wall spacer

406‧‧‧Contact etching stop layer

408‧‧‧field board

410‧‧‧The first metal material

412‧‧‧Second Metal Material

414‧‧‧Inner lining

416‧‧‧Second Interlayer Dielectric Layer

418‧‧‧The first metal wire layer

2002‧‧‧Photoresist protective oxide

2004‧‧‧Composite etching stop layer

2006: The first dielectric material

2008: The second dielectric material

2200: high voltage transistor components

th ₅ : thickness

Claims (11)

An integrated chip, comprising: a gate structure arranged above a substrate between a source region and a drain region; and a dielectric layer extending laterally from above the gate structure to the gate structure and the drain Between the polar regions; a composite etch stop layer, including a plurality of different dielectric materials stacked above the dielectric layer; contact the etch stop layer, directly contact the upper surface of the composite etch stop layer and a plurality of sidewalls; And a field plate, which is laterally surrounded by a first interlayer dielectric layer, and extends vertically from the top of the first interlayer dielectric layer, extends through the contact etch stop layer, and extends to the composite etch stop In the layer, wherein the composite etch stop layer completely separates the field plate from the dielectric layer. The integrated wafer according to claim 1, wherein the composite etch stop layer includes a first dielectric material and a second dielectric material in contact with the upper surface of the first dielectric material. The integrated chip according to claim 2, wherein the field plate extends vertically through the second dielectric material, and the field plate is connected to the gate through the second dielectric material. The pole structures are separated laterally or vertically separated from the gate structure by the first dielectric material. The integrated wafer according to claim 1, wherein the composite etch stop layer has a first thickness directly below the field plate and has a second thickness outside the field plate. The integrated wafer described in item 1 of the scope of patent application, wherein the composite The etch stop layer laterally contacts the sidewalls of the field plate. The integrated wafer according to claim 1, wherein the bottom of the field plate is vertically separated from the dielectric layer by the composite etch stop layer. The integrated wafer according to the first item of the scope of patent application, wherein the dielectric layer includes a photoresist protective oxide, the photoresist protective oxide has a lower surface in contact with the gate structure and the composite wafer The upper surface contacted by the etch stop layer. An integrated wafer comprising: a gate structure arranged above a substrate; a photoresist protective oxide extending laterally from above the gate structure to exceed the outermost sidewall of the gate structure; a composite etching stop layer, including the The photoresist protects the first dielectric material above the oxide and the second dielectric material in contact with the upper surface of the first dielectric material; a plurality of conductive contacts are dielectric by the first interlayer above the substrate And a field plate that extends from the top of the first interlayer dielectric layer to the composite etch stop layer and includes the same material as the plurality of conductive contacts, wherein the composite etch stop layer The multiple sidewalls of the field plate are laterally contacted, and the composite etch stop layer completely separates the field plate from the photoresist protection oxide vertically. The integrated wafer according to the 8th patent application, wherein the composite etch stop layer further comprises: a third dielectric material contacting the upper surface of the second dielectric material, wherein the first dielectric material And the third dielectric material is the same material. A method for forming an integrated wafer includes: forming a gate junction on the substrate between the source region and the drain region in the substrate A dielectric layer is formed above the gate structure and between the gate structure and the drain region; a composite etch stop layer is formed above the dielectric layer, wherein the composite etch stop layer includes A plurality of stacked dielectric materials; forming a first interlayer dielectric layer above the composite etch stop layer; selectively etching the first interlayer dielectric layer to simultaneously define a plurality of layers extending to the substrate Contact openings and field plate openings extending to the composite etch stop layer; and filling the plurality of contact openings and the field plate openings with one or more conductive materials to form a plurality of conductive contacts and field plates, wherein The field plate extends vertically from the top of the first interlayer dielectric layer into the composite etch stop layer, and the field plate is completely connected to the dielectric layer by the composite etch stop layer. Separate. The method for forming an integrated wafer as described in item 10 of the scope of patent application further includes: forming a mask layer above the composite etch stop layer; and etching the composite etch stop layer and the composite etch stop layer according to the mask layer. The dielectric layer.

Images