CN107910271B - Power semiconductor device and method of manufacturing the same - Google Patents
Power semiconductor device and method of manufacturing the same Download PDFInfo
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- CN107910271B CN107910271B CN201711148755.6A CN201711148755A CN107910271B CN 107910271 B CN107910271 B CN 107910271B CN 201711148755 A CN201711148755 A CN 201711148755A CN 107910271 B CN107910271 B CN 107910271B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application discloses a power semiconductor device and a method of manufacturing the same. The method comprises the following steps: forming a plurality of trenches in a semiconductor substrate, the plurality of trenches including a first trench of a first size and a second trench of a second size, the first size being greater than the second size; forming a split gate structure in the first trench; forming a gate wiring in the second trench, the gate wiring being connected to a gate conductor; a body region in the semiconductor substrate; forming a source region in the body region; and forming a source electrode electrically connected to the source region and the shield conductor and a gate electrode electrically connected to the gate wiring. The method utilizes the filling effect of grooves with different sizes to simultaneously form the grid conductor and the grid wiring, thereby simplifying the process and reducing the manufacturing cost.
Description
Technical Field
The present application relates to the technical field of electronic devices, and more particularly, to a power semiconductor device and a method of manufacturing the same.
Background
Power semiconductor devices, also known as power electronics devices, include power diodes, thyristors, VDMOS (vertical double diffused metal oxide semiconductor) field effect transistors, LDMOS (lateral diffused metal oxide semiconductor) field effect transistors, IGBTs (insulated gate bipolar transistors), and the like. The VDMOS field effect transistor includes a source region and a drain region formed on opposite surfaces of a semiconductor substrate, and in an on state, a current flows mainly along a longitudinal direction of the semiconductor substrate.
In high frequency operation of a power semiconductor device, lower on-loss and switching loss are important indicators for evaluating device performance. On the basis of the VDMOS field effect transistor, a trench type MOS field effect transistor has been further developed, in which a gate conductor is formed in the trench, and a gate dielectric is formed on the trench sidewall to separate the gate conductor and the semiconductor layer, thereby forming a channel in the semiconductor layer in the direction of the trench sidewall. The Trench (Trench) process eliminates the effect of the parasitic JFET resistance of the planar structure by changing the channel from horizontal to vertical, thereby greatly reducing the cell size. On the basis of increasing the cell density and the total width of the channel in the chip in unit area, the channel width-to-length ratio of the device on the unit silicon chip can be increased, so that the current is increased, the on-resistance is reduced and related parameters are optimized, and the aim that the die with smaller size has higher power and high performance is fulfilled, so that the trench technology is increasingly applied to novel power semiconductor devices.
However, as the cell density increases, the inter-electrode resistance increases, and the switching loss increases accordingly, and the gate-drain capacitance Cgd directly relates to the switching characteristics of the device. In order to reduce the gate-drain capacitance Cgd, a split gate trench (Split Gate Trench, abbreviated as SGT) power semiconductor device has been further developed in which the gate conductor extends to the drift region while the gate conductor is separated from the drain by a thick oxide, thereby reducing the gate-drain capacitance Cgd, improving the switching speed, and reducing the switching loss. At the same time, the shielding conductor under the gate conductor and the source electrode are connected together and grounded together, thereby introducing a charge balance effect, and reducing the surface electric field (Reduced Surface Field, abbreviated as RESURF) effect in the vertical direction of the power semiconductor device, further reducing the on-resistance Rdson, thereby reducing the on-loss.
FIGS. 1a and 1b are cross-sectional views showing main steps of a method of manufacturing an SGT power semiconductor device according to the prior art, respectively. As shown in fig. 1a, a trench 102 is formed in a semiconductor substrate 101. A first insulating layer 103 is formed in a lower portion of the trench 102, and a shield conductor 104 fills the trench 102. At the upper portion of the trench 102, two openings separated by a shield conductor 104 are formed. Further, as shown in fig. 1b, a gate dielectric 105 is formed on the upper sidewalls of the trench 102 and the exposed portions of the shield conductor 104, and then a conductive material is filled in the two openings separated by the shield conductor 104 to form two gate conductors 106.
In the SGT power semiconductor device, shield conductor 104 is connected to the source electrode of the power semiconductor device for generating RESURF effects. Two gate conductors 106 are located on either side of the shield conductor 104. The shield conductor 104 is separated from the drain region of the power semiconductor device by a first insulating layer 103 and from the gate electrode 106 by a gate dielectric 105. The gate conductor 106 is separated from the well region in the semiconductor substrate 101 by the gate dielectric 105, thereby forming a channel in the well region. As shown, the thickness of the first insulating layer 103 is less than the thickness of the gate dielectric 105.
According to the SGT theory, whatever SGT structure, the material of the shielding conductor 104 needs to be isolated from the second conductive material and the material used for isolation needs to meet certain capacitance parameters, otherwise, failures such as gate-source short circuit, abnormal gate-drain capacitance Cgd, etc. are prone to occur. How to optimize the device structure and meet the parameter and reliability requirements of the product, and at the same time, the most efficient and low cost wiring method is what is needed to be researched by the person skilled in the art.
Disclosure of Invention
In view of the above problems, an object of the present application is to provide a power semiconductor device and a method of manufacturing the same, in which a gate conductor and a gate wiring are simultaneously formed using filling effects of trenches of different sizes, so that a process can be simplified.
According to an aspect of the present application, there is provided a method of manufacturing a power semiconductor device, including: forming a plurality of trenches in a semiconductor substrate of a first doping type, the plurality of trenches comprising a first trench of a first size and a second trench of a second size, the first size being greater than the second size; forming a split gate structure in the first trench, the split gate structure comprising a shield conductor, a gate conductor and a second insulating layer sandwiched therebetween; forming a gate wiring in the second trench, the gate wiring being connected to the gate conductor; forming a body region of a second doping type in a region of the semiconductor substrate adjacent to the trench, the second doping type being opposite to the first doping type; forming a source region of the first doping type in the body region; and forming a source electrode electrically connected to the source region and the shield conductor and a gate electrode electrically connected to the gate wiring.
Preferably, the step of forming the split gate structure includes: forming an insulating stack on sidewalls and a bottom of the first trench, the insulating stack including a first insulating layer and a second insulating layer, the first insulating layer surrounding the second insulating layer; filling the shielding conductor in the first groove; forming first openings positioned on two sides of the shielding conductor at the upper part of the first groove, wherein the first openings expose the side wall of the upper part of the first groove; forming a gate dielectric on sidewalls of the first trench upper portion; and forming the gate conductor to fill the first opening, wherein the gate conductor and the shield conductor are isolated from each other by at least one layer of the insulating stack, the gate conductor and the body are isolated from each other by the gate dielectric, and the shield conductor and the semiconductor substrate are isolated from each other by the insulating stack.
Preferably, the step of forming the gate wiring includes: filling the first insulating layer in the second trench; forming a second opening in the upper portion of the second trench, the second opening exposing the sidewall of the upper portion of the second trench; forming the gate dielectric on sidewalls of the second trench upper portion; and forming the gate wiring to fill the second opening; wherein the gate wiring and the body region are isolated from each other by the gate dielectric.
Preferably, the first insulating layers in the first and second trenches are a conformal layer and a fill layer, respectively, and are formed simultaneously.
Preferably, between the step of filling the shielding conductor and the step of forming the first opening, a planarization step is further included.
Preferably, before the planarization step, the shielding conductor, the first insulating layer and the second insulating layer respectively include a first portion located in the first trench and a second portion extending laterally on the surface of the semiconductor substrate, and in the planarization step, the respective second portions of the shielding conductor, the second insulating layer and the first insulating layer are removed with the semiconductor substrate as a stop layer such that top ends of the respective first portions of the shielding conductor, the second insulating layer and the first insulating layer are flush with the surface of the first insulating layer.
Preferably, in the step of forming the first opening, a portion of the first insulating layer located at an upper portion of the first trench is removed, and the shield conductor extends downward from the semiconductor substrate surface by a predetermined depth to form the first opening extending downward from the semiconductor substrate surface by a predetermined depth.
Preferably, the step of forming the gate conductor comprises: a first conductive layer is deposited to fill the first opening.
Preferably, the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride, or polysilicon.
Preferably, the depth of the first and second trenches is in the range of 0.1 to 50 microns.
Preferably, the width of the first groove is 1.5 times or more the width of the second groove.
Preferably, the width of the first trench is in the range of 0.2 to 10 micrometers.
Preferably, the width of the second trench is in the range of 0.1 to 5 micrometers.
Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.
Preferably, the sidewalls of the first trench are sloped such that a top width of the first trench is greater than a bottom width of the first trench.
Preferably, the step of filling the shielding conductor and the step of forming the gate conductor each comprise at least one deposition.
According to another aspect of the present application, there is provided a power semiconductor device including: a plurality of trenches in a semiconductor substrate, the semiconductor substrate being of a first doping type, the plurality of trenches comprising a first trench of a first size and a second trench of a second size, the first size being greater than the second size; a split gate structure located in the first trench, the split gate structure comprising a shield conductor, a gate conductor, and a second insulating layer sandwiched therebetween; a gate wiring located in the second trench, the gate wiring being connected to the gate conductor; a body region in the semiconductor substrate, the body region being adjacent to an upper portion of the first trench and being of a second doping type, the second doping type being opposite to the first doping type; the source region is positioned in the body region and is of the first doping type; a source electrode electrically connected to the source region and the shield conductor; and a gate electrode electrically connected to the gate wiring.
Preferably, the split gate structure includes: an insulating stack located on the lower sidewall and bottom of the first trench, the insulating stack comprising a first insulating layer and the second insulating layer, the first insulating layer surrounding the second insulating layer; at least a portion of a shield conductor located in the first trench, the shield conductor extending from above the first trench to a bottom thereof and being isolated from the semiconductor substrate by the insulating stack; gate conductors located on both sides of the shield conductor in the upper portion of the first trench; wherein the gate conductor and the shield conductor are isolated from each other by at least one layer of the insulating stack, the gate conductor and the body region are isolated from each other by the gate dielectric, and the shield conductor and the semiconductor substrate are isolated from each other by the insulating stack.
Preferably, the first insulating layer fills a lower portion of the second trench, the gate wire fills an upper portion of the second trench, and the gate wire and the body region are isolated from each other by the gate dielectric.
Preferably, the shield conductor extends downward from the semiconductor substrate surface by a predetermined depth.
Preferably, the first insulating layer is composed of silicon oxide, and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride, or polysilicon.
Preferably, the depth of the first and second trenches is in the range of 0.1 to 50 microns.
Preferably, the width of the first groove is 1.5 times or more the width of the second groove.
Preferably, the width of the first trench is in the range of 0.2 to 10 micrometers.
Preferably, the width of the second trench is in the range of 0.1 to 5 micrometers.
Preferably, the first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type.
Preferably, the sidewalls of the first trench are sloped such that a top width of the first trench is greater than a bottom width of the first trench.
Preferably, the power semiconductor device is one selected from the group consisting of a CMOS device, a BCD device, a MOSFET transistor, an IGBT, and a schottky diode.
In a method according to an embodiment of the present application, an SGT structure is formed in a power semiconductor device, wherein an insulating stack is formed between a shield conductor and a semiconductor substrate, thereby reducing a gate-drain capacitance Cgd.
The method utilizes the filling effect of grooves with different sizes to simultaneously form the gate conductor and the gate wiring, thereby simplifying the process. The SGT structure is realized through simpler process steps, the problems of complex process, easy occurrence of gate-source short circuit, abnormal gate-drain capacitance Cgd and the like in the conventional process are solved, and the wiring method is most efficient and low in cost by combining specific process steps while meeting the requirements of parameters and reliability of products. Compared with the prior art, the method can reduce the photoresist mask adopted in the current manufacturing process by 3 to 4 photoresist masks based on the 0.25 to 0.35um process.
The split gate power semiconductor device structure for reducing the source-drain capacitance and the forming method thereof can be applied to products such as CMOS, BCD, power MOSFET, high-power transistor, IGBT, schottky and the like.
Drawings
The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application with reference to the accompanying drawings, in which:
fig. 1a and 1b show a cross-sectional view of the main steps of a method for manufacturing a power semiconductor device according to the prior art, respectively.
Fig. 2 shows a flowchart of a method of manufacturing a power semiconductor device according to an embodiment of the present application.
Fig. 3a to 3i show cross-sectional views of different stages of a method of manufacturing a semiconductor device according to an embodiment of the application.
Detailed Description
The application will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.
It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.
If, for the purposes of describing a situation directly on top of another layer, another region, the expression "a directly on top of B" or "a directly on top of B and adjoining it" will be used herein. In the present application, "a is directly in B" means that a is in B and a is adjacent to B, instead of a being in the doped region formed in B.
In the present application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a semiconductor device, including all layers or regions that have been formed.
Numerous specific details of the application, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.
Unless specifically indicated below, the various portions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as GaAs, inP, gaN, siC, and group IV semiconductors such as Si, ge.
Fig. 2 illustrates a flow chart of a method of fabricating an SGT power semiconductor device according to an embodiment of the present application, and fig. 3a to 3i illustrate cross-sectional views in different steps, respectively. The steps of the manufacturing method according to the embodiment of the present application are described below with reference to fig. 2 and 3a to 3 i.
The method starts with a semiconductor substrate 101. The semiconductor substrate is, for example, a silicon substrate doped to an N-type, and the silicon substrate is uniformly doped in a longitudinal direction and has a resistivity in a range of, for example, 1 to 15 Ω·cm. The semiconductor substrate has opposite first and second surfaces. Preferably, the voltage dividing ring structure of the power semiconductor is formed on the first surface of the semiconductor substrate through photolithography, etching, ion implantation, impurity activation and other processes, and the voltage dividing ring structure is a well-known structural part of the device structure in the art, and will not be described in detail herein. Preferably, the semiconductor substrate 101 employed in the present embodiment may be formed with a semiconductor device such as a MOS field effect transistor, an IGBT insulated gate field effect transistor, a schottky diode, or the like.
In step S101, a first trench 1021 and a second trench 1022 are formed in a first region 201 and a second region 202 of the semiconductor substrate 101, respectively, as shown in fig. 3 a.
The process for forming the first trench 1021 and the second trench 1022 includes forming a resist mask by photolithography and etching, and etching to remove an exposed portion of the semiconductor substrate 101 through an opening of the resist mask.
In this embodiment, the first region 201 refers to the source and shield conductor routing regions in the SGT structure, and the second region 202 refers to the gate conductor routing region in the SGT structure.
The first trench 1021 and the second trench 1022 extend downward from the surface of the semiconductor substrate 101, and reach a predetermined depth in the semiconductor substrate 101. The depth of the first trenches 1021 and the second trenches 1022 is in the range of 0.1 to 50 micrometers. The width of the first trench 1021 is 1.5 times or more the width of the second trench 1022. In this embodiment, the width of the first trench 1021 is in the range of 0.2 to 10 micrometers. The width of the second trenches 1022 is in the range of 0.1 to 5 microns. The width of the trench of the SGT structure is much wider than the trench of a conventional trench power semiconductor device of the same conduction efficiency level, and the depth of the trench is also much deeper than the trench of the conventional trench power semiconductor device.
Preferably, the sidewalls of the first trenches 1021 and the second trenches 1022 are inclined, e.g., at an angle of 85 to 89 degrees relative to the top of the vertical trenches, such that the bottom width of the trenches is less than the top width. The angle of the groove is inclined, so that the filling of each subsequent dielectric layer and conductive material is facilitated, and the defects caused by filling gaps are reduced.
In step S102, an insulating stack comprising a conformal first insulating layer 122 and a second insulating layer 123 is sequentially formed on the surface of the semiconductor substrate 101, as shown in fig. 3 b.
In the first trench 1021, the first insulating layer 122 surrounds the second insulating layer 123. In the second trench 1022, the first insulating layer 122 fills an inner space of the trench, and in this region, the second insulating layer 123 covers over the first insulating layer 122. The size of the first trench 1021 is larger than that of the second trench 1022, and thus, even if the first insulating layer 122 is deposited and formed in the same process, insulating layers of different filling effects can be obtained. The first insulating layer 122 in the first trench 1021 is a conformal layer, and the first insulating layer 122 in the second trench 1022 is a filling layer. When the width of the second trench 1022 is, for example, 2 times or more the thickness of the first insulating layer 122, the first insulating layer 122 may completely fill the second trench 1022.
The first insulating layer 122 and the second insulating layer 123 are composed of different insulating materials. In this embodiment, the first insulating layer 122 is composed of, for example, silicon oxide. The second insulating layer 123 is composed of, for example, at least one selected from silicon nitride, oxynitride, or polysilicon. Preferably, the second insulating layer 123 is composed of silicon nitride. The thickness of the first insulating layer 122 is, for example, 500 to 50000 angstroms, and the thickness of the second insulating layer 123 is, for example, 50 to 5000 angstroms. The larger the thickness of the first insulating layer 122 is, the smaller the gate-drain capacitance Cgd is.
The process for forming the first insulating layer 122 includes forming an oxide layer on the inner wall of the first trench 1021 by thermal oxidation, chemical Vapor Deposition (CVD), or high-density plasma chemical vapor deposition. The oxide layer conformally covers the sidewalls and bottom of the first trench 1021, thereby still preserving a portion of the interior space of the first trench 1021.
The process for forming the second insulating layer 123 includes forming a nitride layer on the surface of the first insulating layer 122 by Chemical Vapor Deposition (CVD) or high-density plasma chemical vapor deposition. The nitride layer conformally covers the surface of the first insulating layer 122, thereby still preserving a portion of the interior space of the first trench 1021.
In step S103, a shield conductor 104 is formed in the first trench 1021 as shown in fig. 3 c.
The shield conductor 104 is composed of, for example, doped amorphous silicon or polysilicon. The process for forming the shield conductor 104 includes, for example, depositing polysilicon using a sputtering or the like process such that the polysilicon fills the remaining portion of the first trench 1021, and removing polysilicon located outside the first trench 1021 using Chemical Mechanical Planarization (CMP) such that the polysilicon filling the first trench 1021 forms the shield conductor 104.
The polysilicon is deposited at a deposition rate of, for example, 1 to 100 angstroms per minute, at a deposition temperature of, for example, 510 to 650 degrees celsius, and at a thickness of, for example, 1000 to 100000 angstroms. By controlling the doping concentration of the shield conductor 104, its resistance can be adjusted. In this embodiment, the sheet resistance Rs of the shield conductor 104 is, for example, less than 20 ohms. Further, the smaller the sheet resistance Rs of the shield conductor 104, the greater the oxide thickness formed during the subsequent oxide layer compared to silicon. Further, the material of the shielding conductor 104 is amorphous, which is easier to form a lower sheet resistance Rs.
In the deposition step described above, one or more depositions of material forming the shield conductor 104 may be employed. In a plurality of depositions, the rate of the subsequent deposition step is smaller than that of the previous deposition step, so that the deposition rate is gradually reduced. The slower the deposition rate, the better the filling effect during trench filling, the more difficult the trench bottom filling than the trench top, so the rate of front deposition needs to be less than the rate of any one deposition later when filling multiple times.
In the chemical mechanical planarization step described above, the semiconductor substrate 101 is employed as a stop layer. At the first trench 1021, the planarization removes not only the portion of the polysilicon outside the first trench 1021, but also the portions of the second insulating layer 123 and the first insulating layer 122 outside the first trench 1021. Thus, in the first trench 1021, the top of the shield conductor 104, the second insulating layer 123, and the first insulating layer 122 are flush with the surface of the semiconductor substrate 101. At the second trench 1022, the planarization removes not only the portion of the first insulating layer 122 located outside the second trench 1022, but also the second insulating layer 123 and the polysilicon over the first insulating layer 122. Thus, the top of the first insulating layer 122 is flush with the surface of the semiconductor substrate 101.
In step S104, a portion of the first insulating layer 122 is etched away, thereby forming first openings 1241 on both sides of the shield conductor 104 in the upper portion of the first trench 1021 and forming second openings 1022 in the upper portion of the second trench 1022, as shown in fig. 3 d. The first and second openings 1241 and 1022 re-expose upper sidewalls of the first trench 1021.
The etching process is, for example, wet etching. Due to the selectivity of the etchant, the exposed portion of the first insulating layer 122 is removed with respect to the semiconductor substrate 101, the second insulating layer 123, and the shield conductor 104. The etching back etches portions of the first insulating layer 122 inside the first trenches 1021 and the second trenches 1022, thereby exposing the surface of the semiconductor substrate 101. The height at which the second insulating layer 123 and a portion of the shield conductor 104 extend upward from the surface of the semiconductor substrate 101 corresponds to the thickness of the first insulating layer 122, for example, 500 to 50000 angstroms. The extended height facilitates subsequent contact opening processes. The first insulating layer 122 extends downward from the surface of the semiconductor substrate 101 to a depth of, for example, 0.5 to 5 micrometers. After etching, a portion of the first insulating layer 122 located at the lower side wall and bottom of the first trench 1021 remains so that the lower portion of the shield conductor 104 and the semiconductor substrate 101 are still isolated from each other by the insulating stack. A portion of the first insulating layer 122 located at a lower portion of the second trench 1022 remains. As described above, since the first insulating layer 122 is a filling layer in the second trench 1022, a shield conductor is not formed therein.
In step S105, a gate dielectric 105 is formed on top of the shield conductor 104 and the upper sidewalls of the first trenches 1021, and a gate dielectric 105 is formed on the upper sidewalls of the second trenches 1022, as shown in fig. 3 e.
The process for forming gate dielectric 105 may employ thermal oxidation. The temperature of the thermal oxidation is, for example, 950 to 1200 degrees celsius. The exposed silicon material of the semiconductor substrate 101 and the shield conductor 104 forms silicon oxide during thermal oxidation. In the thermal oxidation step, the surface of the semiconductor substrate 101 is also exposed to the atmosphere. The gate dielectric 105 covers not only the upper sidewalls of the first trench 1021 and the second trench 1022, but also the surface of the semiconductor substrate 101.
Compared to the dense semiconductor substrate 101, the shielding conductor 104 is a heavily doped amorphous or polycrystalline material, which has a relatively loose structure and a relatively high doping concentration. As a result, the thickness of the second portion of the gate dielectric 105 on the surface of the shield conductor 104 is greater than the thickness of the first portion on the surface of the semiconductor substrate 101 and in the first trenches 1021 and the second trenches 1022. The first portion of gate dielectric 105 is, for example, 50 to 5000 angstroms thick and the second portion is, for example, 60 to 10000 angstroms thick.
In step S106, the gate conductor 106 is formed in the first opening 1241, the gate wiring 131 is formed in the second opening 1242, and the body region 107 and the source region 108 are formed in the region of the semiconductor substrate 101 adjacent to the first trench 1021, as shown in fig. 3 f.
The gate conductor 106 and the gate wiring 131 are composed of, for example, doped amorphous silicon or polysilicon. The process for forming the gate conductor 106 and the gate wiring 131 includes, for example, depositing polysilicon using a process such as sputtering so that the polysilicon fills the remaining portions of the first trench 1021 and the second trench 1022, and removing polysilicon outside the first opening 1241 and the second opening 1242 using Chemical Mechanical Planarization (CMP) so that the polysilicon fills the openings on both sides of the shield conductor 104, thereby forming the gate conductor 106 in the first opening 1241 and the gate wiring 131 in the second opening 1242.
The polysilicon is deposited at a deposition rate of, for example, 1 to 100 angstroms per minute, at a deposition temperature of, for example, 510 to 650 degrees celsius, and at a thickness of, for example, 1000 to 100000 angstroms. By controlling the doping concentration of the gate conductor 106, its resistance can be adjusted. In this embodiment, the sheet resistance Rs of the gate conductor 106 is, for example, less than 20 ohms. Further, the smaller the sheet resistance Rs of the gate conductor 106, the greater the oxide thickness formed during subsequent oxide layers compared to silicon. Further, the material of the gate conductor 106 is amorphous, which is easier to form into a lower sheet resistance Rs.
In the deposition step described above, one or more depositions of material forming the gate conductor 106 may be employed. In a plurality of depositions, the rate of the subsequent deposition step is smaller than that of the previous deposition step, so that the deposition rate is gradually reduced. The slower the deposition rate, the better the filling effect during trench filling, the more difficult the trench bottom filling than the trench top, so the rate of front deposition needs to be less than the rate of any one deposition later when filling multiple times.
Next, a P-type body region 107 is formed in the semiconductor substrate 101, and an N-type source region is formed in the body region 107. The process for forming the body region 107 and the source region 108 is, for example, a plurality of ion implantations. Different types of doped regions are formed by selecting appropriate dopants and then thermally annealing to activate the impurities. In the ion implantation, using the shield conductor 104 and the gate conductor 106 as hard masks, lateral positions of the body region 107 and the source region 108 can be defined, so that a photoresist mask can be omitted. The angle of the ion implantation is, for example, zero angle, i.e., vertical implantation with respect to the surface of the semiconductor substrate 101. By controlling the energy of the ion implantation, the implantation depth of the body region 107 and the source region 108 can be defined, thereby defining the vertical position.
The dopant used in forming body region 107 may be B11 or BF2, or may be B11 followed by BF2, with an implant energy of 20-100 Kev, an implant dose of 1E 14-1E 16, and a thermal anneal temperature of 500-1000 degrees celsius. In forming the source region 108, the dopant used is p+ or as+, the implant energy is 60-150 Kev, the implant dose is 1E 14-1E 16, and the thermal annealing temperature is 800-1100 degrees celsius.
In this step, an SGT structure is formed in first trench 1021, including shield conductor 104 and gate conductor 106 located in the trench. The gate conductor 106 includes a first portion located in the first trench 1021 and a second portion extending over the semiconductor substrate 101. A first portion of the gate conductor 106 is formed in the first opening 1241 on both sides of the shield conductor 104 so that the shield conductor 104 is sandwiched therebetween. The shield conductor 104 and the gate conductor 106 are isolated from each other by a second insulating layer 123. The lower portion of the shield conductor 104 extends to the lower portion of the first trench 1021, and is isolated from the semiconductor substrate 101 by an insulating stack including a first insulating layer 122 and a second insulating layer 123. The gate conductor 106 is adjacent to the body region 107 and the source region 108 and is isolated from each other by the gate dielectric 105.
In step S107, an interlayer dielectric layer 109 is deposited on the surface of the semiconductor structure, as shown in fig. 3 g.
The interlayer dielectric layer 109 covers the first region and the second region of the semiconductor substrate 101. The interlayer dielectric layer 109 may be composed of at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and may have a single-layer or stacked-layer structure. In this embodiment, interlayer dielectric layer 109 may be, for example, borophosphosilicate glass (BPSG) having a thickness of 2000 to 15000 angstroms.
In step S108, a plurality of contact holes 125 reaching the source region 108, the gate conductor 106 and the shield conductor 104 are formed in the interlayer dielectric layer 109, and contact regions 110 are formed at bottoms of the plurality of contact holes 125, respectively, by ion implantation, as shown in fig. 3 h.
The process for forming the contact hole 125 is, for example, dry etching. The sidewalls of the contact holes 125 are inclined, for example, at an angle of 85 to 89.9 degrees with respect to the top of the vertical first trenches 1021 and second trenches 1022, such that the bottom width of the contact holes 125 is less than the top width. The contact hole 125 has a relatively inclined angle, which is beneficial to the filling of the subsequent conductive material and reduces the defects caused by filling gaps.
In a first region 201 of the semiconductor substrate 101, a first set of contact holes of the plurality of contact holes 125 extend sequentially through the interlayer dielectric layer 109 and the gate dielectric 105 to a predetermined depth in the shield conductor 104, and a second set of contact holes sequentially through the interlayer dielectric layer 109, the gate dielectric 10, the source region 108 to a predetermined depth in the body region 107. The predetermined depth is, for example, 0.1 to 1 micron.
In the second region 202 of the semiconductor substrate 101, a third set of contact holes of the plurality of contact holes 125 sequentially extend through the interlayer dielectric layer 109 to a predetermined depth in the gate conductor 106.
In the ion implantation, the interlayer dielectric layer is used as a hard mask to define the lateral position of the contact region 110, so that the photoresist mask can be omitted. The doping agent adopted by the ion implantation is B11 or BF2, or B11 is firstly implanted and BF2 is then implanted, the implantation energy is 20-100 Kev, the implantation dosage is 1E 14-1E 16, and the thermal annealing temperature is 500-1000 ℃. After ion implantation, a thermal anneal may be performed to activate the dopants.
In step S109, the source electrode 111 and the gate electrode 112 are formed as shown in fig. 3 i.
This step includes, for example, depositing a metal layer and patterning. The metal layer is composed of, for example, one selected from Ti, tiN, tiSi, W, AL, alSi, alSiCu, cu, ni or an alloy thereof. The metal layer is patterned into a source electrode 111 and a gate electrode 112 by etching. As shown, the source electrode 111 and the gate electrode 112 are isolated from each other.
In the first region 201 of the semiconductor substrate 101, the source electrode 111 reaches the shielding conductor 104 via a first set of contact holes of the plurality of contact holes 125, reaches the source region 108 via a second set of contact holes of the plurality of contact holes 125, thereby electrically connecting the source region 108 and the shielding conductor 104 to each other. In the second region 202 of the semiconductor substrate 101, the gate electrode 112 reaches the gate conductor 106 via a third set of contact holes of the plurality of contact holes 125.
After step S109, the metallization of the power semiconductor device has been achieved. Further, passivation layer protection can be added according to the requirements of products, and the processing of the front structure of the semiconductor device with the power is completed. And finally realizing the device through a series of subsequent processes such as thinning, gold backing, scribing and the like.
It should be noted that although the shield conductors 104 in the different trenches are isolated from each other and the gate conductors 106 are isolated from each other in the above-described cross-sectional view, in an actual power semiconductor device, the shield conductors 104 in the different trenches may be connected to each other and the gate conductors 106 may be connected to each other as viewed in a planar structure. In one embodiment, the connection is, for example, such that the gate conductor 106 in the different first trench 1021 and the gate wiring in the second trench 1022 are integrally formed of a single conductive layer, and the shield conductor 104 in the different first trench 1021 is integrally formed of a single conductive layer. In an alternative embodiment, the connection manner is, for example, to connect the shield conductors 104 in the different first trenches 1021 to each other with a common source electrode, and to connect the gate conductors 106 in the different first trenches 1021 to the gate wiring 131 in the second trenches 1022 with a common gate electrode.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Embodiments in accordance with the present application, as described above, are not intended to be exhaustive or to limit the application to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Claims (27)
1. A method of manufacturing a power semiconductor device, comprising:
forming a plurality of trenches in a semiconductor substrate of a first doping type, the plurality of trenches comprising a first trench of a first size and a second trench of a second size, the first size being greater than the second size;
simultaneously forming a first insulating layer in the first trench and the second trench, wherein the first insulating layer is a conformal layer in the first trench and is a filling layer in the second trench;
forming a split gate structure in the first trench, the split gate structure including a shield conductor, a gate conductor, and a second insulating layer sandwiched therebetween, the first insulating layer surrounding the second insulating layer at a lower portion of the first trench to form an insulating stack;
etching back the first insulating layer in the second trench and forming a gate wiring on the first insulating layer, the gate wiring being connected to the gate conductor;
forming a body region of a second doping type in a region of the semiconductor substrate adjacent to the trench, the second doping type being opposite to the first doping type;
forming a source region of the first doping type in the body region; and
a source electrode and a gate electrode are formed, the source electrode being electrically connected to the source region and the shield conductor, the gate electrode being electrically connected to the gate wiring.
2. The method of claim 1, wherein the etching back forms first openings on both sides of the shield conductor at an upper portion of the first trench, the first openings exposing sidewalls of the upper portion of the first trench, the step of forming a split gate structure comprising:
filling the shielding conductor in the first groove;
forming a gate dielectric on sidewalls of the first trench upper portion; and
the gate conductor is formed to fill the first opening,
wherein the gate conductor and the shield conductor are isolated from each other by the second insulating layer, the gate conductor and the body region are isolated from each other by the gate dielectric, and the shield conductor and the semiconductor substrate are isolated from each other by the insulating stack.
3. The method of claim 2, wherein the etching back forms a second opening at an upper portion of the second trench, the second opening exposing sidewalls of the upper portion of the second trench, the forming the gate wiring comprising:
forming the gate dielectric on sidewalls of the second trench upper portion; and
forming the gate wiring to fill the second opening;
wherein the gate wiring and the body region are isolated from each other by the gate dielectric.
4. The method of claim 3, further comprising a planarization step between the step of filling the shield conductor and the step of etching back.
5. The method of claim 4 wherein prior to the planarizing step, the shield conductor, the first insulating layer, and the second insulating layer each include a first portion located in the first trench and a second portion extending laterally over the semiconductor substrate surface,
in the planarization step, the semiconductor substrate is used as a stop layer, and the respective second portions of the shielding conductor, the second insulating layer and the first insulating layer are removed, so that the top ends of the respective first portions of the shielding conductor, the second insulating layer and the first insulating layer are flush with the surface of the first insulating layer.
6. The method of claim 5 wherein, in the step of etching back, a portion of the first insulating layer having the first portion located at an upper portion of the first trench is removed, the shield conductor extending downwardly from the semiconductor substrate surface a predetermined depth to form the first opening extending downwardly from the semiconductor substrate surface a predetermined depth.
7. The method of claim 3, wherein forming the gate conductor comprises: a first conductive layer is deposited to fill the first opening.
8. The method of claim 3, wherein the first insulating layer is composed of silicon oxide and the second insulating layer is composed of at least one selected from silicon nitride, oxynitride, or polysilicon.
9. The method of claim 3, wherein the first and second trenches have a depth in the range of 0.1 to 50 microns.
10. The method of claim 9, wherein the width of the first trench is 1.5 times or more the width of the second trench.
11. The method of claim 10, wherein the first trench has a width in the range of 0.2 to 10 microns.
12. The method of claim 11, wherein the second trench has a width in the range of 0.1 to 5 microns.
13. The method of claim 3, wherein the first doping type is one of N-type and P-type and the second doping type is the other of N-type and P-type.
14. The method of claim 1, wherein sidewalls of the first trench are sloped such that a top width of the first trench is greater than a bottom width of the first trench.
15. The method of claim 1, wherein the step of filling the shield conductor and the step of forming the gate conductor each comprise at least one deposition.
16. A power semiconductor device, comprising:
a plurality of trenches in a semiconductor substrate, the semiconductor substrate being of a first doping type, the plurality of trenches comprising a first trench of a first size and a second trench of a second size, the first size being greater than the second size;
a first insulating layer located at a lower portion of the first trench and a lower portion of the second trench;
a split gate structure located at an upper portion of the first trench, the split gate structure including a shield conductor, a gate conductor, and a second insulating layer sandwiched therebetween, the first insulating layer surrounding the second insulating layer at a lower portion of the first trench to form an insulating stack;
a gate wiring located in the second trench, the gate wiring being connected to the gate conductor;
a body region in the semiconductor substrate, the body region being adjacent to an upper portion of the first trench and being of a second doping type, the second doping type being opposite to the first doping type;
the source region is positioned in the body region and is of the first doping type;
a source electrode electrically connected to the source region and the shield conductor; and
a gate electrode electrically connected to the gate wiring,
wherein the first insulating layer is a conformal layer in the first trench and is a filling layer in the second trench, the first insulating layer being formed simultaneously in the first trench and the second trench.
17. The power semiconductor device of claim 16 wherein said split gate structure comprises:
at least a portion of a shield conductor located in the first trench, the shield conductor extending from above the first trench to a bottom thereof and being isolated from the semiconductor substrate by the insulating stack;
gate conductors located on both sides of the shield conductor in the upper portion of the first trench;
wherein the gate conductor and the shield conductor are isolated from each other by the second insulating layer, the gate conductor and the body region are isolated from each other by a gate dielectric, and the shield conductor and the semiconductor substrate are isolated from each other by the insulating stack.
18. The power semiconductor device of claim 17 wherein the gate wire fills an upper portion of the second trench, the gate wire and the body region being isolated from each other by the gate dielectric.
19. The power semiconductor device of claim 16 wherein said shield conductor extends downwardly from said semiconductor substrate surface a predetermined depth.
20. The power semiconductor device of claim 16 wherein the first insulating layer is comprised of silicon oxide and the second insulating layer is comprised of at least one selected from the group consisting of silicon nitride, oxynitride, and polysilicon.
21. The power semiconductor device of claim 18 wherein the first and second trenches have a depth in the range of 0.1 to 50 microns.
22. The power semiconductor device of claim 21 wherein a width of the first trench is 1.5 times or more a width of the second trench.
23. The power semiconductor device of claim 22 wherein a width of said first trench is in a range of 0.2 to 10 microns.
24. The power semiconductor device of claim 23 wherein a width of said second trench is in a range of 0.1 to 5 microns.
25. The power semiconductor device of claim 16 wherein said first doping type is one of N-type and P-type and said second doping type is the other of N-type and P-type.
26. The power semiconductor device of claim 16 wherein sidewalls of said first trench are sloped such that a top width of said first trench is greater than a bottom width of said first trench.
27. The power semiconductor device of claim 16, wherein the power semiconductor device is one selected from the group consisting of a CMOS device, a BCD device, a MOSFET transistor, an IGBT, and a schottky diode.
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| CN112582260B (en) * | 2020-12-04 | 2023-08-22 | 杭州芯迈半导体技术有限公司 | Trench MOSFET and manufacturing method thereof |
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