CN106158030B - Method and relevant memory device to memory device program - Google Patents
Method and relevant memory device to memory device program Download PDFInfo
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- CN106158030B CN106158030B CN201510207775.0A CN201510207775A CN106158030B CN 106158030 B CN106158030 B CN 106158030B CN 201510207775 A CN201510207775 A CN 201510207775A CN 106158030 B CN106158030 B CN 106158030B
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Abstract
The invention discloses the methods that a kind of pair of memory device is programmed, comprising the following steps: executes an insertion programming, comprising: program in one first period to one first storage unit, and accordingly verify in one second period to first storage unit；One second storage unit is programmed in a third period, and accordingly second storage unit is verified in one the 4th period, the 4th period is between first period and second period；And an at least delay period is inserted between first period and second period, to ensure the unit time resistance change of first storage unit less than a threshold value.
Description
Technical field
The present invention relates to a kind of memory operating method and relevant memory devices, and in particular to one kind is to storage
The method of device device programming and relevant memory device.
Background technique
Memory program operation is typically divided into two classes: single storage unit programming operation and page programming operation.The former
The programming-being dependent on repeatedly verifies operations to ensure that storage unit magnitude is fallen within the target range.The latter be then verification operation it
The preceding storage unit to whole page is programmed.
However, for the Ovonics unified memory (phase change memory, PCM) influenced by resistance drift effect
For, resistive memory cell can change over time.This resistance variations can make the resistive memory cell value being verified in list
The final resistance value of mistake is generated during storage unit programming operation or page programming operation, and leads to final resistance value point
Cloth broadens.
Therefore, the resistance drift effect between storage unit can be slowed down and improve depositing for data reliability by how providing one kind
Reservoir programming technique is one of the project that current industry is endeavoured.
Summary of the invention
The present invention relates to the method for a kind of pair of memory device program and relevant memory devices.
An embodiment according to the present invention, the method for proposing a kind of pair of memory device program, the memory device include
Multiple storage units.Method includes the following steps: executing an insertion programming, comprising: single to the storage in one first period
One first storage unit programming in member, and accordingly first storage unit is verified in one second period；One
Three periods programmed one second storage unit in the storage unit, and accordingly single to second storage in one the 4th period
Member is verified, and the 4th period is between first period and second period；And first period and this second
An at least delay period is inserted between period, to ensure the unit time resistance change of first storage unit less than a threshold
Value.
Another embodiment according to the present invention, proposes a kind of memory device.The memory device include memory array,
Column decoder, line decoder and controller.The memory array includes multiple storage units.The column decoder passes through a plurality of word
It accords with line and connects the storage unit.The line decoder connects the storage unit by multiple bit lines.The controller executes one and inserts
Enter programming, make the column decoder and the line decoder: is single to one first storage in the storage unit in one first period
Metaprogramming, and accordingly first storage unit is verified in one second period；It is single to the storage in a third period
One second storage unit programming in member, and accordingly second storage unit is verified in one the 4th period, the 4th
Period is between first period and second period；And at least one is inserted between first period and second period
Delay period, to ensure the unit time resistance change of first storage unit less than a threshold value.
More preferably understand to have to above-mentioned and other aspect of the invention, preferred embodiment is cited below particularly, and cooperates attached
Figure, is described in detail below:
Detailed description of the invention
Fig. 1 is the memory device of an embodiment according to the present invention；
Fig. 2 shows the normalized resistance drift characteristic of an example storage unit；
Fig. 3 is the flow chart of the memory program of an embodiment according to the present invention；
Fig. 4 is the flow chart of the insertion scheduling of an embodiment according to the present invention；
Fig. 5 is the flow chart of the insertion programming of an embodiment according to the present invention；
Fig. 6 show an embodiment according to the present invention an example reset after ISPP sequence；
Fig. 7 show another of an embodiment according to the present invention reset after ISPP sequence；
Fig. 8 A is shown based on the obtained illustrative resistance drift distribution of insertion programming technique provided by the invention；
Fig. 8 B is shown based on the obtained illustrative resistance drift distribution of initial program technology；
Fig. 9 shows calculating from the Drift Parameter in 8A and 8B figure.
[description of symbols]
100: memory device
102: memory array
104: column decoder
106: sensing amplifier/data input structure
108: line decoder
110: controller
112: consult table
202: normalized resistance characteristic curve
300,400,500: flow chart
302,304,306,308,310,312,402,404,502,504,506,508,510,512,514: step
MC (1,1)~MC (M, N): storage unit
WL (1)~WL (M): character line
BL (1)~BL (N): bit line
RDR: quick drift region
SDR: drift region at a slow speed
Δ r: resistance change
Δ t: unit time
P (n, m): programming operation
V (n, m): verification operation
D, D1, D2, D3: delay period
TP: programming time
TV: the verification time
TD: delay time
T1~Tk、T1'~Tk': interval time
IP: initial stage
PV: programming and Qualify Phase
VD: verifying and delayed phase
Specific embodiment
It is described in detail by the following examples, embodiment only to illustrate as example, is not limiting upon the present invention
The range to be protected.In addition, unnecessary element is omitted in the attached drawing in embodiment, to clearly show that technology of the invention is special
Point.
Fig. 1 is the memory device 100 of an embodiment according to the present invention.Memory device 100 includes memory array
102, column decoder 104, sensing amplifier/data input structure 106, line decoder 108 and controller 110.Memory array
Column 102 include multiple storage unit MC (1,1), MC (1,2) ... and MC (M, N) (referred to here as storage unit MC).Storage is single
First MC can be the storage unit of Ovonics unified memory (phase change memory, PCM) storage unit or other types.
Column decoder 104 is connected to storage unit MC by a plurality of character line WL (1)-WL (M) (referred to here as character line WL).In response to
The received address information of institute, column decoder 104 can be selected by the character line WL from the storage unit MC that M is arranged wherein it
One.Sensing amplifier/data input structure 106 can be detected by bit line BL (1)-BL (N) (referred to here as bit line BL) and is stored in
Data in storage unit MC.For example, sensing amplifier/data input structure 106 includes for reading, setting and again
If the current source of mode, and line decoder 108 is coupled to by bit line BL.Line decoder 108 is connected to by the bit line BL
Storage unit MC.In response to the received address information of institute, line decoder 108 can be by the bit line BL from the storage unit of N row
One of selection in MC.Controller 110 can control column decoder 104 and line decoder 108 to execute programming operation, verifying behaviour
Make, delay operates or other operations.In one embodiment, memory device 100 can further include that a consult table 112 is multiple to record
It is associated with the parameter of the resistance characteristic of storage unit MC.The parameter being stored in consult table 112 is for controller 110 for formulating
Optimal Programming Strategy.
Please refer to Fig. 2 and Fig. 3.Fig. 2 shows the normalized resistance characteristic of an example storage unit MC.Fig. 3 is according to this hair
The flow chart 300 of the memory program of a bright embodiment.
In general, the resistance of a storage unit MC can drift and can be by exponential function below come model at any time
Change:
Its middle term time R0Indicate initial resistance, item time t0Indicate that reference time, item time γ indicate resistance Drift Parameter.
By by equation eq1 divided by R0And make γ=0.1 and t0=1, the normalized resistance characteristic that can be obtained in Fig. 2 is bent
Line 202.In general, the resistance characteristic curve of storage unit MC can be divided into two regions: quick drift region RDR and float at a slow speed
Move area SDR.In one embodiment, quick drift region RDR and drift region SDR can pass through the tangent slope of resistance characteristic at a slow speed
(Δ r/ Δ t) is distinguished.For example, the curve section of a threshold value is greater than for tangent slope, can be regarded as falling in quickly
Drift region RDR；And the curve section for tangent slope less than a threshold value, then it can be regarded as falling in drift region SDR at a slow speed.Cause
This, unit time of the storage unit MC in quick drift region RDR, ((Δ r) was greater than in drift region at a slow speed Δ t) resistance change
Unit time resistance change in SDR.As shown in Fig. 2, rapidly rising in the quick drift region RDR of curve 202, and at a slow speed
Drift region SDR slowly rises.Since the data in storage unit MC are determined by its resistance value, therefore when a storage unit MC is operated
In its quick drift region RDR, it will reduce the reliability of data.
To solve the problems, such as that resistance drift, executable insertion (interleaving) scheduling of controller 110 exist to avoid operation
Quick drift region RDR (step 302).For example, controller 110 can be based on the parameter being stored in consult table 112, adaptability
Ground rearranges the operation in increment step pulse program (Incremental Step Pulse Programming, ISPP) time
Sequence is to ensure there are enough interval times between the corresponding verification operation of each programming operation.In one embodiment, it is inserted into
The strategy of scheduling is contemplated that the following conditions:
1. ensuring to there are enough interval times to exist to avoid operation between the corresponding verification operation of each programming operation
Quick drift region RDR；And/or
2. making interval time difference minimum/equalization between the storage unit MC；And
3. being inserted into delay period (delay operation) if necessary to meet one or two above-mentioned conditions.
In step 304, the executable insertion programming of controller 110 is to control 108 row of execution of column decoder 104 and line decoder
Programmed/verified/delay operation after journey.For example, controller 110 can control column decoder 104 and line decoder 108:
Storage unit MC (1,1) shown in Fig. 1 is programmed in the first period, and accordingly in the second period to this
Storage unit MC (1,1) is verified；
Storage unit MC (1,2) is programmed in the third period, and accordingly in the 4th period to storage unit MC
(1,2) is verified, and the 4th period is between the first period and the second period；And
It is inserted into an at least delay period, between the first period and the second period to ensure the list of (1,1) storage unit MC
Position time resistance change is less than a threshold value, that is to say, that, it is ensured that in the SDR of drift region at a slow speed or non-of storage unit MC (1,1)
Quick drift region is read out.
In step 306, controller 110 can check whether the operation of the storage unit after all schedulings (for example, programmed/verified/
Delay operation) all it is performed.If it is not, thening follow the steps 308, next operation is performed.
After the storage unit operation after all schedulings is all performed, controller 110 can check whether all storage lists
First MC (or the target group in storage unit MC, such as storage unit MC (1,1) to MC (1, n), n are the integer less than N)
All shielded (step 310).If still there is remaining not shielded storage unit MC, 312 are thened follow the steps, next programming phases
These not shielded storage unit MC are applied to according to ISPP scheme.
Fig. 4 is the flow chart 400 of the insertion scheduling of an embodiment according to the present invention.In step 402, controller 402 can
Based on above-mentioned insertion scheduling strategy, determine that the insertion time stores to avoid in the target for each Destination Storage Unit MC
The quick drift region RDR of unit MC is read out.
The insertion time can indicate the interval time between the corresponding verification operation of programming operation.In one embodiment, it inserts
The angle of incidence can be obtained by searching consult table 112, which records multiple resistance characteristics about storage unit MC
Parameter.The parameter for example including temperature, programming time, the verification time, target insertion the time and delay time at least its
One of.In another embodiment, the insertion time can be obtained by executing and test one or more times accesses to storage unit MC.
For example, storage unit MC can be read to obtain reading result data in controller 110, and is modeled based on result data is read
The resistance characteristic of storage unit MC is to determine the insertion time.
In step 404, controller 110 come scheduling ISPP sequence again and can determine unscreened storage based on the insertion time
The operation of unit MC.For example, controller 110 can according to insertion the time determine will be in the corresponding verification operation of programming operation
Between interval time in the how many a delay periods of insertion, programming operation or verification operation.Based on the ISPP sequence after scheduling again
Column, can then be determined the operation of non-shielded memory cell MC.
Fig. 5 is the flow chart 500 of the insertion programming of an embodiment according to the present invention.As previously mentioned, insertion programming includes
Execute programmed/verified/delay operation of ISPP sequence after resetting.As shown in figure 5, controller 110 first judges to store for target
Whether the current operation of unit MC is verification operation (step 502).If so, controller 110 will carry out Destination Storage Unit MC
Verifying.For example, controller 110 can verify that the storage unit magnitude of Destination Storage Unit MC (for example, voltage, electric current or electricity
Resistance value) whether fall in (step 504) in target resistance region.If so, Destination Storage Unit MC is then shielded from by controller 110
Operation (step 506) later.Conversely, if the judging result of step 502 be it is no, controller 110 will check current operation
It whether is programming (step 508).If so, controller 110 will be programmed Destination Storage Unit MC.For example, controller
110 can search consult table 112 to obtain a program conditions (step 510), and be carried out with programming pulse to Destination Storage Unit MC
Program (step 512).If it is not, then controller 110 may wait for (delay) delay period TD to meet insertion scheduling strategy (step
514)。
Fig. 6 show an embodiment according to the present invention an example reset after ISPP sequence.In Fig. 6, " X (n, m) " table
Show and is programmed/verifies (X=P or V) behaviour to n-th of storage unit in Destination Storage Unit group in m-th of ISPP step
Make；" D " indicates delay period.Assuming that Destination Storage Unit group includes k storage unit (for example, MC (1,1) to MC (1, k), k
For the integer less than or equal to N), then P (1,1) is indicated in the 1st ISPP step to the programming operation of (1,1) storage unit MC；P
(2,1) it indicates in the 1st ISPP step to the programming operation P (2,1) of storage unit MC (1,2)；P (k-1,1) is indicated the 1st
To the programming operation of (1, k-1) storage unit MC when a ISPP step；P (k, 1) indicates single to storage in the 1st ISPP step
The programming operation of first MC (1, k), and so on.Similarly, P (1,2) is indicated in the 2nd ISPP step to storage unit MC
The programming operation of (1,1)；P (2,2) is indicated in the 2nd ISPP step to the programming operation P (2,1) of storage unit MC (1,2)；
P (k-1,2) is indicated in the 2nd ISPP step to the programming operation of (1, k-1) storage unit MC；P (k, 2) is indicated at the 2nd
To the programming operation of (1, k) storage unit MC when ISPP step, and so on.
In this embodiment, each programming operation has its corresponding verification operation.As shown in fig. 6, corresponding to programming operation P
The V (1,1) of (1,1) is indicated in the 1st ISPP step to the verification operation of (1,1) storage unit MC；Corresponding to programming operation P
The V (2,1) of (2,1) is indicated in the 1st ISPP step to the verification operation of (1,2) storage unit MC；Corresponding to programming operation P
The V (k-1,1) of (k-1,1) is indicated in the 1st ISPP step to the verification operation of (1, k-1) storage unit MC；Corresponding to volume
The V (k, 1) that journey operates P (k, 1) is indicated in the 1st ISPP step to the verification operation of (1, k) storage unit MC, with such
It pushes away.
In the example of fig. 6, the programming time of each programming operation is TP, the verification time of a verification operation is TV, and respectively prolong
The delay time in slow period D is TD.If TP> > TVAnd TP=TD, for Destination Storage Unit (such as MC (1,1) to MC (1, k))
The insertion time will be equal to TP, and each interval time T between the corresponding verification operation of each programming operation1To TkIt can indicate
Are as follows:
It can be seen that by equation eq2, interval time T1To TkIt is approximately equal to insertion time (1*TP).It is walked for identical ISPP
For rank, it can be considered across a programming operation between the corresponding verification operation of each programming operation, in addition to the last one programming
Corresponding verification operation is operated across a delay period D.It is tested as shown in fig. 6, programming operation P (1,1) is corresponding
Across programming operation P (2,1) between card operation V (1,1)；Between programming operation P (2,1) corresponding verification operation V (2,1)
Across programming operation P (3,1)；Across programming operation between programming operation P (k-1,1) corresponding verification operation V (k-1,1)
P (k, 1)；Across a delay period D between programming operation P (k, 1) corresponding verification operation V (k, 1).
Fig. 7 show another of an embodiment according to the present invention reset after ISPP sequence.Between Fig. 6 and Fig. 7 example
Main difference be in Fig. 7 for each Destination Storage Unit MC (1,1) to MC (1, k) the insertion time be 3*TP.If TP> >
TVAnd TP=TD, each interval time T between each corresponding verification operation of programming operation1' to Tk' may be expressed as:
It can be seen that by equation eq3, interval time T1' to Tk' it is approximately equal to insertion time (3*TP).For identical ISPP
For step, it can be considered across three programming operations between the corresponding verification operation of each programming operation, in addition to the last one volume
Journey operates (such as P (k, 1)) corresponding verification operation (such as V (k, 1)) across three delay period D, as shown in Figure 7.
It will be appreciated that the present invention is not limited with above-mentioned example.In another embodiment, multiple Destination Storage Unit institutes
Corresponding insertion time can select according to actual demand, and can be unequal.
Based on the scheduling rule in the 6th, 7 figures, ISPP sequence may include an initial stage (Initial Phase) after rearrangement
IP, a programming and the verifying of Qualify Phase (Program&Verify Phase) PV and one and delayed phase (Verify&Dummy
Phase)VD.In initial stage IP, a part in multiple Destination Storage Units, which is programmed in order and is not executed, to be tested
Card.That is, multiple programming operations are performed in order in this stage IP, and any verification operation is not executed.Initial stage
The quantity of programming operation is determined by being inserted into the time in IP.As shown in fig. 6, two (1+ is inserted into the programming pulse wave in the time) storages are single
First MC (1,1), MC (1,2) are programmed (P (1,1) and P (2,1)) in order in initial stage IP.Similarly, as shown in fig. 7,
Four (the programming pulse wave in the 1+ insertion time) storage unit MC (1,1) to MC (Isosorbide-5-Nitrae) are compiled in order in initial stage IP
Journey (P (1,1) to P (4,1)).
Programming and Qualify Phase PV can be considered the mixing of programming operation and verification operation.In one embodiment, programming operation
It is alternately performed in this stage PV with verification operation.By taking Fig. 6 as an example, verification operation V (1,1), programming operation P (3,1), test
Card operation (2,1), programming operation (4,1) ..., and verification operation V (k-1,1) alternately held in programming and Qualify Phase PV
Row.
Verifying and delayed phase VD can be considered the mixing of verification operation and delay operation.As shown in fig. 6, verifying and postponing
In stage VD, and then delay period (postpones to operate) D to verification operation V (k, 1).In Fig. 7, delay period D1, verification operation V
(k-2,1), delay period D2, verification operation V (k-1,1), delay period D3 and proving period V (k, 1) are in this stage VD
Alternately executed.
Please refer to Fig. 8 A and Fig. 8 B.Fig. 8 A shows obtained illustrative based on insertion programming technique provided by the invention
Resistance drift distribution.Fig. 8 B is shown based on the obtained illustrative resistance drift distribution of initial program technology, the initial program
In technology, each verification operation and then its corresponding programming operation.
To compare for convenience, the resistance drift in 8A and 8B figure, which is distributed, obtains (such as 100 seconds) after same time, and
For the storage unit (such as 256 storage units) of identical quantity.In fig. 8 a, the insertion time is approximately equal to 16*TP(about 1.6 μ
S, wherein TP=100ns), and initial resistivity value (R0) is equal to 1M Ω.By can be seen that in the figure, insertion programming technique be can produce
More close resistance drift distribution.
Fig. 9 shows calculating from the Drift Parameter (γ) in 8A and 8B figure.As shown in figure 9, insertion provided by the invention
The Drift Parameter that programming technique can make more averagely reduces 33%, therefore can slow down resistance drift effect.
To sum up, the embodiment of the present invention can pass through the insertion operation between the corresponding verification operation of programming operation
To avoid the reading resistive memory cell value in quick drift region.These operations may include delay period, insertion programming operation, insert
Enter verification operation or other operations.Based on insertion scheduling strategy, the order of ISPP sequence can and being suitably inserting the time by
It rearranges, to obtain more close resistance drift distribution.Therefore, the resistance drift effect between storage unit is reduced,
And the reliability of reading data also can get improvement.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in protection of the invention
Within the scope of.
Claims (10)
1. the method for a kind of pair of memory device program, which includes multiple storage units, this method comprises:
Execute an insertion programming, comprising:
One first storage unit in the storage unit is programmed in one first period, and accordingly in one second period to this
First storage unit is verified；
One second storage unit in the storage unit is programmed in a third period, and accordingly in one the 4th period to this
Second storage unit is verified, and the 4th period is between first period and second period；And
It is inserted into an at least delay period, between first period and second period to ensure the unit of first storage unit
Time resistance change is less than a threshold value.
2. the method as described in claim 1, which is characterized in that further include:
Execute an insertion scheduling, comprising:
According to the resistance characteristic of the storage unit, the insertion time of the storage unit is determined；And
The operation executed to the storage unit is determined according to the insertion time, wherein the operation includes a programming operation, one
Verification operation and corresponding to an at least delay period delay operate.
3. method according to claim 2, which is characterized in that the insertion time indicates the corresponding verifying behaviour of each programming operation
An interval time between work, and the quantity of an at least delay period is determined by the insertion time；When wherein determining the insertion
Between further include:
A consult table is searched to obtain the insertion time；
Wherein the consult table records multiple parameters, and the parameter is relevant to the resistance characteristic of the storage unit.
4. method according to claim 2, which is characterized in that the insertion scheduling further include:
Keep individual insertion times of the storage unit impartial；
Determine the insertion time further include:
The storage unit is read to obtain reading result data；And
The resistance characteristic of the storage unit is modeled based on the reading result data to determine the insertion time.
5. method according to claim 2, which is characterized in that insertion programming further include:
One initial stage, comprising:
Multiple first programming operations are executed in order and do not execute any verification operation；
One programming and Qualify Phase, comprising:
Alternately execute multiple second programming operations and multiple first verification operations；And
One verifying and delayed phase, comprising:
Alternately execute one or more second verification operations and one or more first delay operations；
Wherein the quantity of first programming operation in the initial stage is determined by the insertion time.
6. a kind of memory device, comprising:
One memory array, including multiple storage units；
One column decoder connects the storage unit by a plurality of character line；
One line decoder connects the storage unit by multiple bit lines；And
One controller executes an insertion programming, makes the column decoder and the line decoder:
One first storage unit in the storage unit is programmed in one first period, and accordingly in one second period to this
First storage unit is verified；
One second storage unit in the storage unit is programmed in a third period, and accordingly in one the 4th period to this
Second storage unit is verified, and the 4th period is between first period and second period；And
It is inserted into an at least delay period, between first period and second period to ensure the unit of first storage unit
Time resistance change is less than a threshold value.
7. memory device as claimed in claim 6, which is characterized in that the controller execute one insertion scheduling with:
According to the resistance characteristic of the storage unit, the insertion time of the storage unit is determined；And
The operation executed to the storage unit is determined according to the insertion time, wherein the operation includes a programming operation, one
Verification operation and corresponding to an at least delay period delay operate.
8. memory device as claimed in claim 7, which is characterized in that the insertion time indicates that each programming operation is corresponding
An interval time between verification operation, and the quantity of an at least delay period is determined by the insertion time, the wherein storage
Device device further include:
One consult table, records multiple parameters, and the parameter is relevant to the resistance characteristic of the storage unit.
9. memory device as claimed in claim 7, which is characterized in that the controller controls the column decoder and the row is translated
Code device obtains reading result data to read the storage unit, and models the storage list based on the reading result data
The resistance characteristic of member is to determine the insertion time, wherein individual insertion times of the storage unit are impartial.
10. memory device as claimed in claim 7, which is characterized in that insertion programming further include:
One initial stage, comprising:
Multiple first programming operations are executed in order and do not execute any verification operation；
One programming and Qualify Phase, comprising:
Alternately execute multiple second programming operations and multiple first verification operations；And
One verifying and delayed phase, comprising:
Alternately execute one or more second verification operations and one or more first delay operations；
Wherein the quantity of first programming operation in the initial stage is determined by the insertion time.
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| US6349056B1 (en) * | 2000-12-28 | 2002-02-19 | Sandisk Corporation | Method and structure for efficient data verification operation for non-volatile memories |
| JP3935139B2 (en) * | 2002-11-29 | 2007-06-20 | 株式会社東芝 | Semiconductor memory device |
| JP5091999B2 (en) * | 2010-09-24 | 2012-12-05 | シャープ株式会社 | Semiconductor memory device |
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