CN105701294B - Realize the method and system of chip complex engineering modification - Google Patents
Realize the method and system of chip complex engineering modification Download PDFInfo
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Abstract
The present invention provides a kind of method and system for realizing the modification of chip complex engineering, which comprises searches original register transfer level circuit and original gate level netlist, obtains its mutual corresponding key signal；It modifies to the key signal in original register transfer level circuit, generates register transfer level circuit 1；It is inserted into the first register after the key signal of register transfer level circuit 1, by the modification result cache after modifying to the key signal of original register transfer level circuit into first register, generates register transfer level circuit 2；It is inserted into the second register after the key signal of original gate level netlist, generates gate level netlist 1；According to register transfer level circuit 2 and gate level netlist 1, gate level netlist 2 is obtained；Preservation and/or output register switching stage circuit 1 and gate level netlist 2, complete the modification of chip complex engineering.Purpose project modification is realized in the least logic change of the present invention, accelerates the redesign period of chip.
Description
Technical field
The present invention relates to network communication field more particularly to a kind of method and system for realizing the modification of chip complex engineering.
Background technique
Currently, the development of network technology and popularizing for informationization application, various hardware chips have obtained more and more extensive
Using.
Along with the development of science and technology, chip complexity is higher and higher, simultaneously, it is desirable that and the R&D cycle of chip is shorter and shorter,
In this way, to adapt to the speed of development in science and technology；Correspondingly, in order to meet above-mentioned requirements, more and more chips are had in chip
After development late stage or chip flow find chip defect back, engineering modification is made further to remedy.
Mainly for gate level netlist, the readability of gate level netlist is excessively poor for engineering modification, and can be based on posting when comprehensive
Storage switching stage circuit does complex optimization, the modification of the engineering of the complexity be typically all need to be added in a large amount of combinational logic or
Part logic is modified, the difficulty of this modification at least two o'clock is to be difficult inside gate level netlist and register transfer level first
Corresponding signal in circuit, there are many amount of logic followed by changed, and there are many logic of influence, and engineering modification is caused to be increasingly difficult to,
The engineering modification of some complexity can not even be realized.
Summary of the invention
The purpose of the present invention is to provide a kind of method and system for realizing the modification of chip complex engineering.
One of to achieve the above object, the method for the realization chip complex engineering modification of an embodiment of the present invention includes:
Original register transfer level circuit and original gate level netlist are searched, its mutual corresponding key signal is obtained；
It modifies to the key signal in original register transfer level circuit, generates register transfer level circuit 1；
It is inserted into the first register after the key signal of the register transfer level circuit 1, original register will be turned
Change grade circuit key signal modify after modification result cache into first register, generate register transfer level
Circuit 2；
It is inserted into the second register after the key signal of original gate level netlist, generates gate level netlist 1；
According to register transfer level circuit 2 and gate level netlist 1, gate level netlist 2 is obtained；
Preservation and/or output register switching stage circuit 1 and gate level netlist 2, complete the modification of chip complex engineering.
As being further described for an embodiment of the present invention, " after the key signal of the register transfer level circuit 1
It is inserted into the first register, after generating register transfer level circuit 2 ", the method also includes:
It is matched according to the register transfer level circuit 2 and generates gate level netlist 2a.
As being further described for an embodiment of the present invention, " according to register transfer level circuit 2 and gate level netlist 1,
Gate level netlist 2 " is obtained to specifically include:
According to gate level netlist 2a and gate level netlist 1, the ECO script file for matching original gate level netlist is obtained；
The ECO script file is loaded on original gate level netlist, obtains gate level netlist 2.
As being further described for an embodiment of the present invention, the method also includes:
The gate level netlist 2a and gate level netlist 1 are compared using Conformal software, obtains and matches original gate leve net
The ECO script file of table.
As being further described for an embodiment of the present invention, " save and/or export new register transfer level circuit and
After new gate level netlist ", the method also includes:
The register transfer level circuit 1 and gate level netlist 2 are subjected to formal verification, after being identified through verifying, completed
The modification of chip complex engineering.
One of to achieve the above object, the system for realizing the modification of chip complex engineering of an embodiment of the present invention is described
System includes: data acquisition module, for searching original register transfer level circuit and original gate level netlist, obtains its phase
Mutual corresponding key signal；
Data processing module, for modifying to the key signal in original register transfer level circuit, generation is posted
Storage switching stage circuit 1；
It is inserted into the first register after the key signal of the register transfer level circuit 1, original register will be turned
Change grade circuit key signal modify after modification result cache into first register, generate register transfer level
Circuit 2；
It is inserted into the second register after the key signal of original gate level netlist, generates gate level netlist 1；
According to register transfer level circuit 2 and gate level netlist 1, gate level netlist 2 is obtained；
Output module is stored, for preservation and/or output register switching stage circuit 1 and gate level netlist 2, it is multiple to complete chip
The modification of general labourer's journey.
As being further described for an embodiment of the present invention, the data processing module is also used to: according to the deposit
The matching of device switching stage circuit 2 generates gate level netlist 2a.
As being further described for an embodiment of the present invention, the data processing module is also used to:
According to gate level netlist 2a and gate level netlist 1, the ECO script file for matching original gate level netlist is obtained；
The ECO script file is loaded on original gate level netlist, obtains gate level netlist 2.
As being further described for an embodiment of the present invention, the data processing module is also used to:
The gate level netlist 2a and gate level netlist 1 are compared using Conformal software, obtains and matches original gate leve net
The ECO script file of table.
As being further described for an embodiment of the present invention, the data processing module is also used to:
The register transfer level circuit 1 and gate level netlist 2 are subjected to formal verification, after being identified through verifying, completed
The modification of chip complex engineering.
Compared with prior art, the beneficial effects of the present invention are: the present invention realize chip complex engineering modification method and
System, by finding out key signal common on register transfer level circuit and gate level netlist, and respectively after its key signal
Increase corresponding register and generate new netlist, engineering modification script is generated based on new netlist and applies to original gate level netlist,
It realizes the modification of chip complex engineering, realizes that purpose project is modified to change using least logic, accelerate setting again for chip
Count the period.
Detailed description of the invention
Fig. 1 is the flow chart that the method for chip complex engineering modification is realized in an embodiment of the present invention；
Fig. 2 a-2i is specific example application schematic diagram in an embodiment of the present invention；
Fig. 3 is the module map for realizing the system of chip complex engineering modification in an embodiment of the present invention in embodiment.
Specific embodiment
Below with reference to specific embodiment shown in the drawings, the present invention will be described in detail.But these embodiments are simultaneously
The present invention is not limited, structure that those skilled in the art are made according to these embodiments, method or functionally
Transformation is included within the scope of protection of the present invention.
As shown in Figure 1, the method for realizing the modification of chip complex engineering provided in one embodiment of the present invention, described
Method includes:
S1, original register transfer level circuit and original gate level netlist are searched, obtains its corresponding key signal.
In a specific example of the invention, need to compare original register transfer level circuit and original gate leve net respectively
Table searches the key signal that its common needs is modified.
The register transfer level circuit is usually by referred to as RTL.
It is described in detail below for the convenience of description, lifting a specific example.
In conjunction with shown in Fig. 2 a, 2b, Fig. 2 a is original register transfer level circuit；Fig. 2 b is original gate level netlist.
By comparison it is found that the key signal in original register transfer level circuit is " a ", in original gate level netlist
Corresponding key signal is " n4 ".
Further, the method for realizing the modification of chip complex engineering further include:
S2, it modifies to the key signal in original register transfer level circuit, generates register transfer level circuit
1。
Above-mentioned example is connected to need for " in0&&in1 " in the key signal " a " to be revised as when this engineering is modified
“in0||in1”。
In conjunction with shown in Fig. 2 c, 2d, Fig. 2 c is to modify to the key signal " a " in original register transfer level circuit
Logical code；Fig. 2 d is to convert to register generated after the key signal modification in original register transfer level circuit
Grade circuit 1.
By Fig. 2 d it is found that in modified register transfer level circuit, key signal " a ", via " in0&&in1 "
Be revised as " in0 | | in1 ", it is not described in detail herein.
Further, the method for realizing the modification of chip complex engineering further include:
S3, it is inserted into the first register after the key signal of the register transfer level circuit 1, it will be to original register
The key signal of switching stage circuit modify after modification result cache into first register, generate register conversion
Grade circuit 2；
Connecting above-mentioned example, traditional register transfer level circuit modification, after modifying to key signal " a ",
It will continue to influence signal b and export out0, i.e., after being fixed to signal at one in register transfer level circuit, repair at this
Circuit after the number of converting to all is affected, in this way, needing to change and largely patrol in modification register transfer level circuitry processes
Circuit is collected, modification is complicated, and error probability is high.
In the present invention, the first register is inserted into after the key signal of register transfer level circuit 1, and will post original
The key signal of storage switching stage circuit modify after modification result cache into first register, in formal verification
When, the circuit before only influencing the first register being newly inserted into the modification of key signal can be in this way, during modification
The location revision for reducing logic circuit simplifies complicated logic Modification process, meanwhile, successful probability is higher.In connecting
Example is stated, in conjunction with shown in Fig. 2 e, Fig. 2 e is newly-generated register transfer level circuit 2.
By Fig. 2 e it is found that after modifying to the key signal " a " of original register transfer level circuit, result is modified
It is indicated with " aF1 ", and a " aF1 " is written in the first register, generates new register transfer level circuit 2.
Further, after the step S3, the method also includes:
S4, generation gate level netlist 2a is matched according to the register transfer level circuit 2.
Above-mentioned example is connected, in conjunction with shown in Fig. 2 g, Fig. 2 g is newly-generated gate level netlist 2a.
It should be noted that according to register transfer level circuit produce gate level netlist software there are many, do not do herein in detail
Carefully repeat.
Further, the method for realizing the modification of chip complex engineering further include:
S5, it is inserted into the second register after the key signal of original gate level netlist, generates gate level netlist 1；
Above-mentioned example is connected, in conjunction with shown in Fig. 2 f, Fig. 2 f is newly-generated gate level netlist 1.
Known to comparison original gate level netlist and newly-generated gate level netlist 1 as shown in Figure 2 b:
In newly-generated gate level netlist 1 increase logical code "
//add for ECO
SDFFQ_X1M_A9TU aF1_reg(.D(n4),.SI(1′b0),.SE(1′b0),.CK(ClockCore),.Q
(aF1));”
Further, the method also includes:
S6, according to register transfer level circuit 2 and gate level netlist 1, obtain gate level netlist 2.
In a preferred embodiment of the invention, the step S6 is specifically included:
M1, according to gate level netlist 2a and gate level netlist 1, obtain the ECO script file for matching original gate level netlist.
It should be noted that in above-mentioned example the gate level netlist 2a and gate leve net can be compared using various ways
Table 1 in the preferred embodiment of the present invention, compares the gate level netlist 2a and gate level netlist 1 using Conformal software,
Obtain the ECO script file for matching original gate level netlist.
Above-mentioned example is connected, in conjunction with shown in Fig. 2 h, Fig. 2 h is the ECO script file of the original gate level netlist of matching.
M2, the ECO script file is loaded on original gate level netlist, obtain gate level netlist 2.
Above-mentioned example is connected, in conjunction with shown in Fig. 2 i, Fig. 2 i is the gate level netlist 2 that will eventually be obtained.
Further, the method also includes:
S7, preservation and/or output register switching stage circuit 1 and gate level netlist 2 complete the modification of chip complex engineering.
In a preferred embodiment of the invention, the step S7 further include:
The register transfer level circuit 1 and gate level netlist 2 are subjected to formal verification, after being identified through verifying, completed
The modification of chip complex engineering, is not described in detail herein.
It should be noted that part steps of the S1 into S7 can carry out simultaneously in above-mentioned example, it can also be first laggard
Row, acquisition sequence do not influence final modification as a result, in specific example of the present invention, for convenience of explanation, using step S1 ~ S7
It elaborates to the entire method for realizing the modification of chip complex engineering, but in actual application, above-mentioned part steps are held
Row sequence is successively limited there is no specific.
Such as: step S2 and step S5 can be carried out successively, can also be carried out, be not described in detail simultaneously herein.
As shown in connection with fig. 3, in one embodiment of the present invention, multiplex system in same framework, the system comprises: number
According to acquisition module 100, data processing module 200, storage output module 300.
Data acquisition module 100 obtains it for searching original register transfer level circuit and original gate level netlist
Corresponding key signal.
In a specific example of the invention, data acquisition module 100 needs to compare original register transfer level circuit respectively
With original gate level netlist, the key signal that its common needs is modified is searched.
The register transfer level circuit is usually by referred to as RTL.
It is described in detail below for the convenience of description, lifting a specific example.
In conjunction with shown in Fig. 2 a, 2b, Fig. 2 a is original register transfer level circuit；Fig. 2 b is original gate level netlist.
By comparison it is found that the key signal in original register transfer level circuit is " a ", in original gate level netlist
Corresponding key signal is " n4 ".
Further, in an embodiment of the present invention, data processing module 200 is used for original register transfer level electricity
Key signal in road is modified, and register transfer level circuit 1 is generated.
Above-mentioned example is connected to need for " in0&&in1 " in the key signal " a " to be revised as when this engineering is modified
“in0||in1”。
In conjunction with shown in Fig. 2 c, 2d, Fig. 2 c is to modify to the key signal " a " in original register transfer level circuit
Logical code；Fig. 2 d is to convert to register generated after the key signal modification in original register transfer level circuit
Grade circuit 1.
By Fig. 2 d it is found that in modified register transfer level circuit, key signal " a ", via " in0&&in1 "
Be revised as " in0 | | in1 ", it is not described in detail herein.
Further, in an embodiment of the present invention, data processing module 200 is also used to: in the register transfer level
It is inserted into the first register after the key signal of circuit 1, will modify to the key signal of original register transfer level circuit
Modification result cache afterwards generates register transfer level circuit 2 and generates register transfer level circuit into first register
2；
Connecting above-mentioned example, traditional register transfer level circuit modification, after modifying to key signal " a ",
It will continue to influence signal b and export out0, i.e., after being fixed to signal at one in register transfer level circuit, repair at this
Circuit after the number of converting to all is affected, in this way, needing to change and largely patrol in modification register transfer level circuitry processes
Circuit is collected, modification is complicated, and error probability is high.
In the present invention, the first register is inserted into after the key signal of register transfer level circuit 1, and will post original
The key signal of storage switching stage circuit modify after modification result cache into first register, in formal verification
When, the circuit before only influencing the first register being newly inserted into the modification of key signal can be in this way, during modification
The location revision for reducing logic circuit simplifies complicated logic Modification process, meanwhile, successful probability is higher.In connecting
Example is stated, in conjunction with shown in Fig. 2 e, Fig. 2 e is newly-generated register transfer level circuit 2.
By Fig. 2 e it is found that after modifying to the key signal " a " of original register transfer level circuit, result is modified
It is indicated with " aF1 ", and a " aF1 " is written in the first register, generates new register transfer level circuit 2.
Further, in an embodiment of the present invention, data processing module 200 is also used to: being converted according to the register
The grade matching of circuit 2 generates gate level netlist 2a.
Above-mentioned example is connected, in conjunction with shown in Fig. 2 g, Fig. 2 g is newly-generated gate level netlist 2a.
It should be noted that according to register transfer level circuit produce gate level netlist software there are many, do not do herein in detail
Carefully repeat.
Further, in an embodiment of the present invention, data processing module 200 is also used to: in original gate level netlist
It is inserted into the second register after key signal, generates gate level netlist 1；
Above-mentioned example is connected, in conjunction with shown in Fig. 2 f, Fig. 2 f is newly-generated gate level netlist 1.
Known to comparison original gate level netlist and newly-generated gate level netlist 1 as shown in Figure 2 b:
In newly-generated gate level netlist 1 increase logical code "
//add for ECO
SDFFQ_X1M_A9TU aF1_reg(.D(n4),.SI(1′b0),.SE(1′b0),.CK(ClockCore),.Q
(aF1));”
Further, in an embodiment of the present invention, data processing module 200 is also used to: according to register transfer level electricity
Road 2 and gate level netlist 1 obtain gate level netlist 2.
In a preferred embodiment of the invention, data processing module 200 is specifically used for:
According to gate level netlist 2a and gate level netlist 1, the ECO script file for matching original gate level netlist is obtained.
It should be noted that data processing module 200 can compare the gate leve net using various ways in above-mentioned example
Table 2a and gate level netlist 1 in the preferred embodiment of the present invention, compare the gate level netlist 2a using Conformal software
And gate level netlist 1, obtain the ECO script file for matching original gate level netlist.
Above-mentioned example is connected, in conjunction with shown in Fig. 2 h, Fig. 2 h is the ECO script file of the original gate level netlist of matching.
Data processing module 200 also loads the ECO script file on original gate level netlist, obtains gate level netlist 2.
Above-mentioned example is connected, in conjunction with shown in Fig. 2 i, Fig. 2 i is the gate level netlist 2 that will eventually be obtained.
Further, in an embodiment of the present invention, storage output module 300 is used for: saving and/or output register turns
Grade circuit 1 and gate level netlist 2 are changed, the modification of chip complex engineering is completed.
In a preferred embodiment of the invention, data processing module is also used to:
The register transfer level circuit 1 and gate level netlist 2 are subjected to formal verification, after being identified through verifying, completed
The modification of chip complex engineering, is not described in detail herein.
In conclusion the method and system for realizing the modification of chip complex engineering of the invention, by finding out register conversion
Common key signal on grade circuit and gate level netlist, and increase corresponding register after its key signal respectively and generate newly
Netlist generates engineering modification script based on new netlist and applies to original gate level netlist, to realize that chip complex engineering is modified.
The present invention after key signal by being added level-one register, so that formal verification tool does not need analysis and closes
A large amount of combinational logic and register logical after key signals, and the logic before analysis of key signal is only needed, so that form
The amount of logic of verification tool analysis greatly reduces, and then obtains engineering modification；The present invention is inserted into accordingly after key signal
Register after gate level netlist obtained and original gate level netlist in addition in timing differ a cycle other than, patrol
It is identical to collect operation behavior, and then then the engineering obtained based on the gate level netlist after conversion can be modified into script and be applied directly to original
On the gate level netlist of beginning, to realize the complex engineering modification of original netlist；Simultaneously as the present invention is added after key signal
Corresponding register, so that in formal verification tool when analysis project is modified, the register number being related to is relatively fewer,
A possibility that combinational logic quantity of its correspondence analysis is also relatively fewer, obtains engineering modification is higher；And then with least
Purpose project modification is realized in logic change, accelerates the redesign period of chip.
For convenience of description, it is divided into various modules when description apparatus above with function to describe respectively.Certainly, implementing this
The function of each module can be realized in the same or multiple software and or hardware when application.
As seen through the above description of the embodiments, those skilled in the art can be understood that the application can
It is realized by the mode of general hardware platform.Based on this understanding, the technical solution of the application is substantially in other words to existing
The part for having technology to contribute is embodied in the form of the product of interchanger.
Device embodiments described above are only schematical, wherein the module as illustrated by the separation member
It may or may not be physically separated, the component shown as module may or may not be physics mould
Block, it can it is in one place, or may be distributed on multiple network modules.It can be selected according to the actual needs
In some or all of the modules realize the purpose of present embodiment scheme.Those of ordinary skill in the art are not paying creation
Property labour in the case where, it can understand and implement.
The application can describe in the general context of computer-executable instructions executed by a computer, such as program
Module.Generally, program module includes routines performing specific tasks or implementing specific abstract data types, programs, objects, group
Part, data structure etc..The application can also be practiced in a distributed computing environment, in these distributed computing environments, by
Task is executed by the connected remote processing devices of communication network.In a distributed computing environment, program module can be with
It is saved in medium positioned at the local and remote computer including saving equipment.
It should be appreciated that although this specification is described in terms of embodiments, but not each embodiment only includes one
A independent technical solution, this description of the specification is merely for the sake of clarity, and those skilled in the art should will say
As a whole, the technical solution in each embodiment may also be suitably combined to form those skilled in the art can for bright book
With the other embodiments of understanding.
The series of detailed descriptions listed above only for feasible embodiment of the invention specifically
Protection scope bright, that they are not intended to limit the invention, it is all without departing from equivalent implementations made by technical spirit of the present invention
Or change should all be included in the protection scope of the present invention.
Claims (8)
1. a kind of method for realizing the modification of chip complex engineering, which is characterized in that the described method includes:
Original register transfer level circuit and original gate level netlist are searched, its mutual corresponding key signal is obtained；
It modifies to the key signal in original register transfer level circuit, generates register transfer level circuit 1；
It is inserted into the first register after the key signal of the register transfer level circuit 1, it will be to original register transfer level
The key signal of circuit modify after modification result cache into first register, generate register transfer level circuit
2；
It is matched according to the register transfer level circuit 2 and generates gate level netlist 2a；
It is inserted into the second register after the key signal of original gate level netlist, generates gate level netlist 1；
According to gate level netlist 2a and gate level netlist 1, gate level netlist 2 is obtained；
Preservation and/or output register switching stage circuit 1 and gate level netlist 2, complete the modification of chip complex engineering.
2. the method according to claim 1 for realizing the modification of chip complex engineering, which is characterized in that " according to gate level netlist
2a and gate level netlist 1 obtain gate level netlist 2 " and specifically include:
According to gate level netlist 2a and gate level netlist 1, the ECO script file for matching original gate level netlist is obtained；
The ECO script file is loaded on original gate level netlist, obtains gate level netlist 2.
3. the method according to claim 2 for realizing the modification of chip complex engineering, which is characterized in that
The method also includes:
The gate level netlist 2a and gate level netlist 1 are compared using Conformal software, obtains and matches original gate level netlist
ECO script file.
4. the method according to claim 1-3 for realizing the modification of chip complex engineering, which is characterized in that " save
And/or export new register transfer level circuit and new gate level netlist " after, the method also includes:
The register transfer level circuit 1 and gate level netlist 2 are subjected to formal verification, after being identified through verifying, complete chip
The modification of complex engineering.
5. a kind of system for realizing the modification of chip complex engineering, which is characterized in that the system comprises:
It is mutually right to obtain it for searching original register transfer level circuit and original gate level netlist for data acquisition module
The key signal answered；
Data processing module generates register for modifying to the key signal in original register transfer level circuit
Switching stage circuit 1；
It is inserted into the first register after the key signal of the register transfer level circuit 1, it will be to original register transfer level
The key signal of circuit modify after modification result cache into first register, generate register transfer level circuit
2；
It is matched according to the register transfer level circuit 2 and generates gate level netlist 2a；
It is inserted into the second register after the key signal of original gate level netlist, generates gate level netlist 1；
According to gate level netlist 2a and gate level netlist 1, gate level netlist 2 is obtained；
Output module is stored, for preservation and/or output register switching stage circuit 1 and gate level netlist 2, completes chip complexity work
The modification of journey.
6. the system according to claim 5 for realizing the modification of chip complex engineering, which is characterized in that the data processing mould
Block is also used to:
According to gate level netlist 2a and gate level netlist 1, the ECO script file for matching original gate level netlist is obtained；
The ECO script file is loaded on original gate level netlist, obtains gate level netlist 2.
7. the system according to claim 6 for realizing the modification of chip complex engineering, which is characterized in that the data processing mould
Block is also used to:
The gate level netlist 2a and gate level netlist 1 are compared using Conformal software, obtains and matches original gate level netlist
ECO script file.
8. according to the described in any item systems for realizing the modification of chip complex engineering of claim 5-7, which is characterized in that the number
It is also used to according to processing module:
The register transfer level circuit 1 and gate level netlist 2 are subjected to formal verification, after being identified through verifying, complete chip
The modification of complex engineering.
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| CN112329362B (en) * | 2020-10-30 | 2023-12-26 | 苏州盛科通信股份有限公司 | General method, device and storage medium for complex engineering modification of chip |
| CN112347722B (en) * | 2020-11-12 | 2023-12-26 | 苏州盛科通信股份有限公司 | Method and device for efficiently evaluating chip Feed-through flow number of stages |
| CN113919254B (en) * | 2021-11-13 | 2022-05-31 | 奇捷科技(深圳)有限公司 | Register transfer level signal mapping construction method, device, equipment and storage medium |
| CN116542191B (en) * | 2023-07-06 | 2023-12-05 | 奇捷科技(深圳)有限公司 | Logic correction method, device, equipment and storage medium |
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