CN113919256A - Boolean satisfiability verification method, system, CNF generation method and storage device - Google Patents
Boolean satisfiability verification method, system, CNF generation method and storage device Download PDFInfo
- Publication number
- CN113919256A CN113919256A CN202111145455.9A CN202111145455A CN113919256A CN 113919256 A CN113919256 A CN 113919256A CN 202111145455 A CN202111145455 A CN 202111145455A CN 113919256 A CN113919256 A CN 113919256A
- Authority
- CN
- China
- Prior art keywords
- node
- cnf
- circuit
- boolean satisfiability
- verification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Abstract
The invention provides a method and a system for verifying Boolean satisfiability, a CNF generation method in the verification process and a storage device, wherein the CNF generation method in the Boolean satisfiability verification comprises the following steps: and in the process of converting each node of the MITER circuit into the CNF, releasing the occupied memory of the CNF which is not required to be called by the subsequent node. By adopting the technical scheme of the invention, the memory occupation in the Boolean satisfiability verification can be reduced.
Description
Technical Field
The invention relates to the technical field of equivalence verification of combined circuits, in particular to a Boolean satisfiability verification method and system, a CNF generation method in the verification process and a storage device.
Background
Equivalence verification techniques are commonly used to verify the correspondence between register transfer level design (RTL) and gate level netlists, and between gate level netlists and gate level netlists. During the processes of scan chain insertion, clock tree synthesis and the like, the equivalence verification technology can be used for ensuring the consistency of the netlist function. Equivalence verification techniques have been incorporated into integrated circuit standard design flows and are useful in verifying ECO. For example, when a designer modifies a gate-level netlist, an OR gate is wrongly written as a NOR gate due to a hand error, and the equivalence checking tool can very easily find such an error by comparing a register transfer level design with the gate-level netlist.
The boolean satisfiability verification tool is one of the main engines for implementing equivalence verification, and the main process of equivalence verification using the boolean satisfiability verification tool includes the analysis of a design to be verified, comparison point matching, CNF (joint Normal Form) generation, and boolean satisfiability verification. In the process of generating the CNF of the design to be verified, a large amount of cache data can be generated during iteration, and the embodiment in the process of verifying the equivalence is that the memory occupation is large.
The high quality equivalence verification tool must have low memory usage and high operating speed. Therefore, it is very valuable to solve a large amount of cache data generated in the CNF generation process of the design to be verified and reduce the memory occupation of the equivalence verification.
Disclosure of Invention
The invention aims to provide a Boolean satisfiability verification method, a system, a CNF generation method in the verification process and a storage device aiming at the defect of large memory occupation in the equivalence verification process in the prior art.
In an embodiment of the present invention, a method for verifying boolean satisfiability is provided, which includes:
step S1: reading a reference circuit to be verified and an implementation circuit;
step S2: comparing point matching is carried out on the reference circuit and the realizing circuit;
step S3: constructing a terminator circuit for the logic cone formed after the comparison points are matched;
step S4: converting the MITER circuit to generate a CNF;
step S5: introducing a CNF corresponding to a terminator circuit end node into a Boolean satisfiability verification tool for Boolean satisfiability verification;
in step S4, in the process of converting each node of the pointer circuit into the CNF, the occupied memory of the CNF that is not required to be called by the subsequent node is released.
In the embodiment of the invention, after the CNF of the current node is generated, the memory occupied by the CNF corresponding to the previous node is released.
In the embodiment of the invention, after the CNF corresponding to the end node of the MITER circuit is generated, the occupied memory of the CNF corresponding to all nodes in front of the end node is released.
In the embodiment of the invention, if one node in the MITER circuit corresponds to a plurality of loads, the node is connected with the plurality of loads
Counting the load number of each node and marking the load number on each node;
in the process of generating the CNF, when the CNF corresponding to a certain node is called for 1 time, subtracting 1 from the load number of the node;
and when the number of the loads corresponding to a certain node is 0, releasing the memory occupied by the corresponding CNF of the node.
The embodiment of the invention also provides a Boolean satisfiability verification system, which adopts the Boolean satisfiability verification method when performing Boolean satisfiability verification.
In an embodiment of the present invention, a CNF generation method in a boolean satisfiability verification process is further provided, which includes:
and in the process of converting each node of the MITER circuit into the CNF, releasing the occupied memory of the CNF which is not required to be called by the subsequent node.
In the embodiment of the invention, after the CNF of the current node is generated, the memory occupied by the CNF corresponding to the previous node is released.
In the embodiment of the invention, after the CNF corresponding to the end node of the MITER circuit is generated, the occupied memory of the CNF corresponding to all nodes in front of the end node is released.
In the embodiment of the invention, if one node in the MITER circuit corresponds to a plurality of loads, the node is connected with the plurality of loads
Counting the load number of each node and marking the load number on each node;
in the process of generating the CNF, when the CNF corresponding to a certain node is called for 1 time, subtracting 1 from the load number of the node;
and when the number of the loads corresponding to a certain node is 0, releasing the memory occupied by the corresponding CNF of the node.
In an embodiment of the present invention, a storage device is further provided, where a computer program is stored, and when the computer program is executed, the CNF generation method in the boolean satisfiability verification process is executed.
Compared with the prior art, in the technical scheme of the invention, in the process of converting each node of the pointer circuit into the CNF, the occupied memory of the CNF which is not required to be called by the subsequent node is released, a large amount of memory can be rapidly released, a large amount of cache data generated in iteration is reduced, and the occupied memory of the CNF is reduced.
Drawings
FIG. 1 is a flow chart of a Boolean satisfiability verification method of an embodiment of the present invention.
Fig. 2(a) and 2(b) are schematic diagrams of the reference circuit Cref and the implementation circuit Cimp, respectively.
Figure 3 is a schematic diagram of a mitier circuit.
Fig. 4 is a schematic diagram of node marking during CNF conversion by the mitier circuit.
Fig. 5 is a CNF release flow diagram when there are multiple load nodes in the mitter circuit.
Detailed Description
As shown in fig. 1, in the embodiment of the present invention, a boolean satisfiability verification method is proposed, which includes steps S1-S5. The following description will be made separately.
Step S1: the reference circuit Cref to be verified and the implementation circuit Cimp are read.
As shown in FIG. 2, the boxes represent storage elements, such as registers, latches, etc., which serve as compare points for the second step of comparison. The triangles represent logic cones connected to the inputs of the storage elements, the top of the logic cone being the input of the register, and the bottom of the cone being the primary input or the output of a next-level storage element (schematically represented in fig. 2 as primary input).
Step S2: and carrying out comparison point matching on the reference circuit and the implementation circuit.
The comparison points are M1 of the reference circuit Cref in fig. 2(a) and M1 of the implementation circuit Cimp in fig. 2(b), because the names of the comparison points are identical, and thus, the two comparison points in fig. 2 are matched.
Step S3: and carrying out construction of a pointer on the logic cone formed after the comparison points are matched.
Assuming that the logic cone of the reference circuit in fig. 2(a) is an and gate and the logic cone of the implementation circuit in fig. 2(b) is an or gate, the procedure of constructing the mitigator circuit is to bind the corresponding inputs of the and gates and connect the output as an input to the xor gate, as shown in fig. 3.
Step S4: and converting the MITER circuit to generate the CNF.
Assuming that there is no constant 0/1 at the input, traversing from input to output and numbering from 1, the number of each node corresponds to the corresponding CNF representation.
Taking fig. 4 as an example:
the CNF corresponding to node 1 is (10),
the CNF corresponding to node 2 is (20),
the CNF corresponding to the node 3 is (10) (20) (1-30) (2-30) (-1-230),
the CNF corresponding to node 4 is (10) (20) (-140) (-240) (12-40),
the CNF corresponding to the node 5 is (10) (20) (1-30) (2-30) (-1-230) (-140) (-240) (12-40) (-5340) (-5-3-40) (5-340) (53-40) (50).
Step S5: and importing the CNF corresponding to the end node of the pointer circuit into a Boolean satisfiability verification tool for Boolean satisfiability verification.
Specifically, the CNF corresponding to the node 5 is led to a boolean satisfiability verification tool, such as Minisat, to obtain a verification result. If the output result is Satisable, it is indicated that the reference circuit to be verified and the implementation circuit are not equivalent, and if the output result is Unsitoseable, it is indicated that the reference circuit to be verified and the implementation circuit are equivalent. The circuit in fig. 3 is clearly not equivalent.
In step S4, in order to reduce the memory occupation during the equivalence verification process, in the process of converting each node of the mitier circuit into a CNF, the memory occupation of the CNF that is not required to be called by the subsequent node is released. Specifically, there are several embodiments as follows.
The first embodiment: and after the CNF of the current node is generated, releasing the memory occupied by the CNF of the superior node.
Taking the CNF corresponding to fig. 4 as an example, in the conventional method, the CNFs of all nodes need to be saved, but actually, the CNF of the output end, that is, the node 5, needs to be used for boolean satisfiability verification.
That is, in fig. 4, after the CNFs of the node 3 and the node 4 are generated, the memory occupied by the CNFs of the node 1 and the node 2 is released; and after the CNF of the node 5 is generated, releasing the occupied memory of the CNFs of the node 3 and the node 4. Thus, after the CNF of the node 5 is generated, the CNF contains 11 clauses instead of the traditional 25 clauses in total, and the occupied memory of the CNF can be reduced by 60%.
The second embodiment: and after the CNFs of all the nodes are generated, releasing the memory occupied by other CNFs except the CNF corresponding to the output node once again.
That is, in fig. 4, after the corresponding CNFs of the node 1, the node 2, the node 3, the node 4, and the node 5 are generated, the occupied memories of the CNFs of the node 1, the node 2, the node 3, and the node 4 are released.
Although the first implementation scheme occupies the minimum memory, the first implementation scheme is only suitable for a circuit without a condition that one node corresponds to multiple loads, if one node corresponds to multiple loads, after the upper CNF is released, the corresponding current CNF generation needs to be iterated again, and the verification time is increased. One node corresponds to the case of multiple loads, taking the input end node 1 in fig. 4 as an example, the node corresponds to two loads, namely, the node 3 and the node 4, and if the CNF of the node 1 is released after the CNF of the node 3 is generated, the CNF of the node 1 needs to be iteratively generated again when the CNF of the node 4 is generated. Fig. 4 is simple, and if the node 1 has multiple levels of upper levels, the more the number of levels of the upper levels is, the longer the time required for the second iteration is, and the effect of the overall equivalence verification is reduced.
Therefore, as shown in fig. 5, for the case where there is one node corresponding to a plurality of loads in the mititor circuit, the third embodiment is adopted:
counting the load number of each node and marking the load number on each node;
when the CNF corresponding to the node is called for 1 time, subtracting 1 from the load number of the node;
and when the number of the loads corresponding to the node is 0, releasing the memory occupied by the CNF of the node.
Also for example in fig. 4: node 1 has two loads, node 3 and node 4, so the load count required by node 1 is 2, after the CNF corresponding to node 3 is generated, the load count of node 1 is decremented by 1, after the CNF corresponding to node 4 is generated, the load count of node 1 is decremented by 1 again, that is, 0, at this time, the memory occupied by the CNF corresponding to node 1 can be released.
In summary, in the technical solution of the present invention, in the process of converting each node of the mitter circuit into the CNF, the occupied memory of the CNF, which is not required to be called by the subsequent node, is released, so that a large amount of memory can be quickly released, a large amount of cache data generated during iteration is reduced, and the occupied memory of the CNF is reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A Boolean satisfiability verification method, comprising:
step S1: reading a reference circuit to be verified and an implementation circuit;
step S2: comparing point matching is carried out on the reference circuit and the realizing circuit;
step S3: constructing a terminator circuit for the logic cone formed after the comparison points are matched;
step S4: converting the MITER circuit to generate a CNF;
step S5: introducing a CNF corresponding to a terminator circuit end node into a Boolean satisfiability verification tool for Boolean satisfiability verification;
in step S4, in the process of converting each node of the pointer circuit into the CNF, the occupied memory of the CNF that is not required to be called by the subsequent node is released.
2. The boolean satisfiability verification method according to claim 1, characterized in that after the CNF of the current node is generated, the occupied memory of the CNF corresponding to the previous node is released.
3. The Boolean satisfiability verification method according to claim 1, wherein after the CNF corresponding to the end node of the mitor circuit is generated, the occupied memory of the CNF corresponding to all nodes before the end node is released.
4. The Boolean satisfiability verification method according to claim 1, characterized in that if there is a situation where one node in the miter circuit corresponds to multiple loads, then
Counting the load number of each node and marking the load number on each node;
in the process of generating the CNF, when the CNF corresponding to a certain node is called for 1 time, subtracting 1 from the load number of the node;
and when the number of the loads corresponding to a certain node is 0, releasing the memory occupied by the corresponding CNF of the node.
5. A Boolean satisfiability verification system, characterized in that when performing Boolean satisfiability verification, the Boolean satisfiability verification method according to any one of claims 1 to 4 is used.
6. A CNF generation method in a Boolean satisfiability verification process is characterized by comprising the following steps:
and in the process of converting each node of the MITER circuit into the CNF, releasing the occupied memory of the CNF which is not required to be called by the subsequent node.
7. The CNF generation method in the Boolean satisfiability verification process of claim 6, wherein after the CNF of the current node is generated, an occupied memory of the CNF corresponding to the previous node is released.
8. The CNF generation method in the Boolean satisfiability verification process of claim 6, wherein after the CNF corresponding to the end node of the mitor circuit is generated, the occupied memory of the CNF corresponding to all nodes in front of the end node is released.
9. The CNF generation method for Boolean satisfiability verification as claimed in claim 6, wherein if there is a case where one node in the mitizer circuit corresponds to a plurality of loads, then
Counting the load number of each node and marking the load number on each node;
in the process of generating the CNF, when the CNF corresponding to a certain node is called for 1 time, subtracting 1 from the load number of the node;
and when the number of the loads corresponding to a certain node is 0, releasing the memory occupied by the corresponding CNF of the node.
10. A storage device, characterized in that a computer program is stored in the storage device, which, when executed, executes the CNF generation method in the boolean satisfiability verification process according to any one of claims 6 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111145455.9A CN113919256A (en) | 2021-09-28 | 2021-09-28 | Boolean satisfiability verification method, system, CNF generation method and storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111145455.9A CN113919256A (en) | 2021-09-28 | 2021-09-28 | Boolean satisfiability verification method, system, CNF generation method and storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113919256A true CN113919256A (en) | 2022-01-11 |
Family
ID=79236866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111145455.9A Pending CN113919256A (en) | 2021-09-28 | 2021-09-28 | Boolean satisfiability verification method, system, CNF generation method and storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113919256A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116050311A (en) * | 2023-02-06 | 2023-05-02 | 中国科学院软件研究所 | Combined operation circuit equivalence verification method and system based on complete simulation |
-
2021
- 2021-09-28 CN CN202111145455.9A patent/CN113919256A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116050311A (en) * | 2023-02-06 | 2023-05-02 | 中国科学院软件研究所 | Combined operation circuit equivalence verification method and system based on complete simulation |
| CN116050311B (en) * | 2023-02-06 | 2023-08-08 | 中国科学院软件研究所 | Combined operation circuit equivalence verification method and system based on complete simulation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7162706B2 (en) | Method for analyzing and validating clock integration properties in circuit systems | |
| US7711536B2 (en) | System and method for verification aware synthesis | |
| US8789004B2 (en) | Automatic flow of megacell generation | |
| US7594200B2 (en) | Method for finding multi-cycle clock gating | |
| US8291358B2 (en) | Synchronous to asynchronous logic conversion | |
| CN116205171B (en) | Matching method, device, equipment and storage medium of power switch unit | |
| US6658630B1 (en) | Method to translate UDPs using gate primitives | |
| CN112949233A (en) | Automatic development method and device of FPGA chip and electronic equipment | |
| US7380228B2 (en) | Method of associating timing violations with critical structures in an integrated circuit design | |
| CN113919256A (en) | Boolean satisfiability verification method, system, CNF generation method and storage device | |
| CN107784185B (en) | Method and device for extracting pseudo path in gate-level netlist and terminal equipment | |
| US8943457B2 (en) | Simulating scan tests with reduced resources | |
| US8150672B2 (en) | Structure for improved logic simulation using a negative unknown boolean state | |
| US7428712B1 (en) | Design optimization using approximate reachability analysis | |
| CN106650136B (en) | Method for checking standard unit function consistency of time sequence library and netlist library | |
| US20220327269A1 (en) | Computing device and method for detecting clock domain crossing violation in design of memory device | |
| US7216321B2 (en) | Pattern recognition in an integrated circuit design | |
| US11270052B2 (en) | System and method of timing characterization for semiconductor circuit | |
| US6877140B1 (en) | Method and system for generating a schematic representing bus structures | |
| CN111353264A (en) | Method for constructing forward circuit diagram of XDL circuit netlist | |
| Kanase et al. | Physical implementation of shift register with respect to timing and dynamic drop | |
| JP4899927B2 (en) | Test pattern automatic generation method and test pattern automatic generation program | |
| US20110191739A1 (en) | Circuit design method, circuit design system, and recording medium | |
| US7350162B2 (en) | Structure analytic program | |
| TWI759817B (en) | Simulation system for soc-level power integrity and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |