CN104424991A - NAND flash memory unit with serial interfaces - Google Patents
NAND flash memory unit with serial interfaces Download PDFInfo
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- CN104424991A CN104424991A CN201310389387.XA CN201310389387A CN104424991A CN 104424991 A CN104424991 A CN 104424991A CN 201310389387 A CN201310389387 A CN 201310389387A CN 104424991 A CN104424991 A CN 104424991A
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Abstract
The invention discloses an NAND flash memory unit with serial interfaces. The unit comprises an IO control module, a data cache module, an NAND control logic module and an NAND memory array module. The unit also comprises a management module used for receiving data and a command of the data cache module under the control of the IO control module, managing the data and the command and then sending the data and the command to the NAND memory array module via the NAND control logic module. The protocol overhead is saved and the encapsulation cost is also reduced by integrating the management module into the NAND flash memory unit with serial interfaces.
Description
Technical field
The present invention relates to flash memory technology field, particularly relate to a kind of serial interface NAND flash cell.
Background technology
Nand flash memory is mainly used to data on file, the flash memory products that we commonly use, if flash disk, digital memory card are all use NAND flash memory.Nand flash memory is a kind of storage scheme more better than hard disk drive, and this shows be still obvious in the low capacity application being no more than 4GB.Along with people continue to pursue the product that power consumption is lower, weight is lighter and performance is better, nand flash memory becomes the product of very attractive.
Fig. 1 is the structural representation of the serial interface NAND flash cell of prior art.As shown in Figure 1, serial interface NAND flash cell 11 comprises: input and output (IO) control module 111, data cache module 112, NAND steering logic module 114 and NAND storage array module 115.
Wherein, master control set 12 sends data and instruction, by the data cached and instruction of input and output (IO) control module 111 control data cache module 112, then after NAND steering logic module 114, instruction and data is resolved to NAND storage array module 114 and store required control information, send to NAND storage array module 115, thus complete storage operation.
If will manage data and instruction, nand flash memory needs independent administration module, have the protocol overhead of more complicated, and packaging cost is higher between independent administration module and nand flash memory.
Summary of the invention
In view of this, the present invention proposes a kind of serial interface NAND flash cell, serial interface NAND flash cell can be made both to save protocol overhead, also reduce packaging cost.
The invention discloses a kind of serial interface NAND flash cell, comprise input/output control module, data cache module, NAND steering logic module and NAND storage array module, also comprise:
Administration module, for receiving data and the instruction of described data buffering module under the control of described input/output control module, and described data and described instruction are managed, then sends to described NAND storage array module via described NAND steering logic module.
Preferably, described administration module is flash memory transport layer management module.
Preferably, described flash memory transport layer management module comprises:
Abrasion equilibrium unit, for the wearing and tearing between the different storage block of equilibrium;
Garbage reclamation unit, for reclaiming discarding data;
Bad-block managing unit, for rejecting the bad block produced in use procedure;
Error control unit, for correcting data error.
Preferably, described serial interface NAND flash cell has 8 pins.
Preferably, described serial interface NAND flash cell has 1,2 or 4 data channel.
Preferably, described serial interface NAND flash cell adopts the mode of contact array or thin type small-sized package to encapsulate.
The present invention, by administration module is integrated in serial interface NAND flash cell, both saved protocol overhead, also reduced packaging cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of the serial interface NAND flash cell of prior art;
Fig. 2 is the structural representation of the serial interface NAND flash cell of the embodiment of the present invention.
Embodiment
Technical scheme of the present invention is further illustrated by embodiment below in conjunction with accompanying drawing.Be understandable that, specific embodiment described herein is only for explaining the present invention, but not limitation of the invention.It also should be noted that, for convenience of description, illustrate only part related to the present invention in accompanying drawing but not full content.
Fig. 2 is the structural representation of the serial interface NAND flash cell of the embodiment of the present invention.As shown in Figure 2, embodiments provide a kind of serial interface NAND flash cell 21, comprise input and output (IO) control module 211, data cache module 212, NAND steering logic module 214 and NAND storage array module 215, also comprise administration module 213, administration module 213 for receiving data and the instruction of described data buffering module 212 under the control of described input/output control module 211, and described data and described instruction are managed, then sends to described NAND storage array module 215 via described NAND steering logic module 214.
The embodiment of the present invention is by being integrated in serial interface NAND flash cell by administration module, and do not adopt independent administration module, this avoid the protocol overhead of the complexity between independent administration module and nand flash memory cell, therefore protocol overhead is saved, simultaneously owing to adopting integrated mode, also reduce packaging cost.
In fig. 2, signal " CSB " is chip enable signal input port; " SCLK " signal input port is reference strings row clock; " IN " is serial primary input signal; " OUT " is the main output signal of serial.In concrete use, do not limit various forms of input and output, input signal wherein and output signal can be data or instruction.
Master control set 22 sends data and instruction, by the data cached and instruction of IO control module 211 control data cache module 212.Data and instruction need data by inputting in administration module modules such as () bad-block managing unit, abrasion equilibrium unit, garbage reclamation unit and error control unit 213 management nand flash memory cells and instruction.After NAND steering logic module 214, data become with instructions parse NAND storage array module 215 to store required control information, thus complete the storage operation of NAND storage array module 215.
Preferably, described administration module is flash memory transport layer (Flash Translation Layer, FTL) administration module.Wherein, described flash memory transport layer management module can comprise bad-block managing unit, abrasion equilibrium unit, garbage reclamation unit and error control unit.Wherein, abrasion equilibrium unit is used for wearing and tearing between balanced different storage block (block) namely for the wearing and tearing between balanced nand flash memory different masses, namely by certain algorithm, the write cycle time number of times of all block is adjusted to equilibrium state, prevents difference excessive, cause damage; Garbage reclamation unit is for reclaiming discarding data, and usual and abrasion equilibrium unit matching realizes final equilibrium; The bad block that bad-block managing unit in use produces for rejecting nand flash memory cell; Error control unit is used for correcting data error, corrects the bit-errors produced owing to reading crosstalk.
Bad-block managing unit, abrasion equilibrium unit, garbage reclamation unit and error control unit are integrated into nand flash memory cell inside by the embodiment of the present invention.After data and instruction enter inside, unified management is carried out to address and data.Only need when master control set write operation to send instruction, address and data.Do not need to be concerned about bad block, do not need be concerned about erasable number of times and read number of times, do not need to be concerned about whether data make mistakes.Serial ports NAND flash of the present invention will process data.
Described serial interface NAND flash cell is Serial Peripheral Interface (SPI) (SPI) nand flash memory.Described serial interface NAND flash cell has 8 pins, and described serial interface NAND flash cell can have 1,2 or 4 data channel, can the number of configuration pin and the number of data channel according to actual needs.Described serial interface NAND flash memory can adopt the mode of contact array (LGA) or thin type small-sized package (TSOP) to encapsulate.The embodiment of the present invention can the lower encapsulation of alternative costs, greatly reduces packaging cost and testing cost, reduces making sheet difficulty simultaneously, improve yield rate.Table 1 is the port list of the embodiment of the present invention.
Table 1 is the port list of the embodiment of the present invention.
| Pin subscript | Function |
| CS# | I |
| SO/SIO1 | I/O |
| WP#/SIO2 | I/O |
| VSS | Ground |
| SI/SIO0 | I/O |
| SCLK | I |
| HOLD#/SIO3 | I/O |
| VCC | Supply |
The embodiment of the present invention is by being integrated in serial interface NAND flash cell by administration module, and do not adopt independent administration module, this avoid the protocol overhead of the complexity between independent administration module and nand flash memory cell, therefore protocol overhead is saved, simultaneously owing to adopting integrated mode, also reduce packaging cost.
These are only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. a serial interface NAND flash cell, comprises input/output control module, data cache module, and NAND steering logic module and NAND storage array module, is characterized in that, also comprise:
Administration module, for receiving data and the instruction of described data buffering module under the control of described input/output control module, and described data and described instruction are managed, then sends to described NAND storage array module via described NAND steering logic module.
2. serial interface NAND flash cell according to claim 1, is characterized in that, described administration module is flash memory transport layer management module.
3. serial interface NAND flash cell according to claim 2, is characterized in that, described flash memory transport layer management module comprises:
Abrasion equilibrium unit, for the wearing and tearing between the different storage block of equilibrium;
Garbage reclamation unit, for reclaiming discarding data;
Bad-block managing unit, for rejecting the bad block produced in use procedure;
Error control unit, for correcting data error.
4. serial interface NAND flash cell according to claim 1, is characterized in that, described serial interface NAND flash cell has 8 pins.
5. serial interface NAND flash cell according to claim 1, is characterized in that, described serial interface NAND flash cell has 1,2 or 4 data channel.
6. serial interface NAND flash cell according to claim 1, is characterized in that, described serial interface NAND flash cell adopts the mode of contact array or thin type small-sized package to encapsulate.
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| CN201310389387.XA CN104424991A (en) | 2013-08-30 | 2013-08-30 | NAND flash memory unit with serial interfaces |
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| CN201310389387.XA CN104424991A (en) | 2013-08-30 | 2013-08-30 | NAND flash memory unit with serial interfaces |
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| CN101800071A (en) * | 2009-02-10 | 2010-08-11 | 三星电子株式会社 | Solid state disk device and program fail processing method thereof |
| CN101916228A (en) * | 2010-08-17 | 2010-12-15 | 中国人民解放军国防科学技术大学 | Flash translation layer (FTL) with data compression function and implementation method |
| US8010770B2 (en) * | 2006-12-27 | 2011-08-30 | Genesys Logic, Inc. | Caching device for NAND flash translation layer |
| CN102279712A (en) * | 2011-08-10 | 2011-12-14 | 北京百度网讯科技有限公司 | Storage control method, system and device applied to network storage system |
| CN102467455A (en) * | 2010-10-29 | 2012-05-23 | 三星电子株式会社 | Memory system, data storage device, user device and data management method thereof |
| CN102930902A (en) * | 2012-07-27 | 2013-02-13 | 北京航空航天大学 | Error correction code algorithm simultaneously correcting fixed errors and random errors |
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2013
- 2013-08-30 CN CN201310389387.XA patent/CN104424991A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8010770B2 (en) * | 2006-12-27 | 2011-08-30 | Genesys Logic, Inc. | Caching device for NAND flash translation layer |
| US20080183955A1 (en) * | 2007-01-25 | 2008-07-31 | Genesys Logic, Inc. | Flash translation layer apparatus |
| CN101800071A (en) * | 2009-02-10 | 2010-08-11 | 三星电子株式会社 | Solid state disk device and program fail processing method thereof |
| CN101916228A (en) * | 2010-08-17 | 2010-12-15 | 中国人民解放军国防科学技术大学 | Flash translation layer (FTL) with data compression function and implementation method |
| CN102467455A (en) * | 2010-10-29 | 2012-05-23 | 三星电子株式会社 | Memory system, data storage device, user device and data management method thereof |
| CN102279712A (en) * | 2011-08-10 | 2011-12-14 | 北京百度网讯科技有限公司 | Storage control method, system and device applied to network storage system |
| CN102930902A (en) * | 2012-07-27 | 2013-02-13 | 北京航空航天大学 | Error correction code algorithm simultaneously correcting fixed errors and random errors |
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Application publication date: 20150318 |