CN103870408B

CN103870408B - Data processing method, Memory Controller and memorizer memory devices

Info

Publication number: CN103870408B
Application number: CN201210551764.0A
Authority: CN
Inventors: 江旭志
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2012-12-18
Filing date: 2012-12-18
Publication date: 2017-06-06
Anticipated expiration: 2032-12-18
Also published as: CN103870408A

Abstract

A kind of data processing method, Memory Controller and memorizer memory devices.The method includes receiving write instruction from host computer system, write-in data corresponding to this write instruction include multiple subdatas, and each subdata is installed in the application program of host computer system additional data directories mark individually, wherein application program is preset function according to the first rule reached an agreement in advance with memorizer memory devices included by, initial parameter value selection mode and the newly-increased mode of parameter value to be marked determining the data directory for being attached to each subdata.The method also include according to and the first regular and each subdata data directory mark for reaching an agreement in advance of application program, all of subdata of resequencing.The method also includes for the subdata after rearrangement being sent to intelligent card chip.

Description

Data processing method, Memory Controller and memorizer memory devices

Technical field

It is the invention relates to a kind of data processing method and non-easily for having duplicative in particular to one kind The data processing method of the memorizer memory devices of the property lost memory module and intelligent card chip, with the memory using the method Storage device and Memory Controller.

Background technology

Gradually receive to use stored value card and prepayment Stored Value with user so that the use of smart card becomes increasingly popular.Intelligence It is the integrated electricity with such as component of microprocessor, card operation system, security module and memory that (Smart Card) can be blocked Road chip (IC chip), to allow holder to perform scheduled operation.Smart card provides calculating, encryption, two-way communication and safe work( Can so that this card can also reach the function being protected by the data stored by it in addition to storing the function of data.Make Subscriber identification module (the Subscriber used in cellular phone with global system for mobile communications (GSM) mechanism Identification Module, SIM) card for smart card one of exemplary applications.In general, smart card is originally experienced It is limited to the specification of its integrated circuit, therefore storage volume is limited.

Storage card is a kind of Data Holding Equipment, and it is usually using nand flash memory as store media.Nand flash memory has It is writable, can erase and power off after can still preserve the advantage of data, additionally, with the improvement of manufacturing technology, nand flash memory tool There are small volume, access speed fast and the low advantage of power consumption.

For there is storage device of the smart card with storage card simultaneously, refer to the access from host computer system is received When making, need to first differentiate access action pair as if smart card or storage card.And be used to store and user mostly due to smart card Information related significant data or digital cash, therefore how to ensure the security of access smartcard and lift reliability, just It is target that those skilled in the art are endeavoured.

The content of the invention

In view of this, the present invention provides a kind of memorizer memory devices, Memory Controller and data processing method, can be just Really process the data of host computer system intelligent card chip to be write.

The present invention proposes a kind of data processing method, for reproducible nonvolatile memorizer module and smart card The memorizer memory devices of chip, wherein reproducible nonvolatile memorizer module have several physics erased cells, and respectively Physics erased cell has several physics programming units, and the method includes receiving write instruction, this write instruction from host computer system Corresponding write-in data include multiple subdatas, and each subdata is installed in the application program indivedual additional of host computer system Data directory is marked.Above-mentioned write-in data are the initial data of correspondence application program memorizer memory devices to be sent to, and deposit Reservoir storage device has the first rule with application program agreement in advance, and the first rule includes that preset function, initial parameter value are selected Mode and the newly-increased mode of parameter value.And application program selectes an initial parameter value according to initial parameter value selection mode, and will just Beginning parameter value substitutes into preset function and is marked with obtaining the data directory of the first stroke subdata being attached in initial data, and foundation Parameter value increases order of the data directory mark of mode, the first stroke subdata with above-mentioned subdata in initial data newly, determines The data directory mark of remaining subdata is attached to individually.The method is also included according to the first rule reached an agreement in advance with application program Then and each subdata data directory mark, all of subdata of resequencing, and the subdata after rearrangement is passed Deliver to intelligent card chip.

From the point of view of another viewpoint, the present invention proposes a kind of Memory Controller, for depositing with duplicative is non-volatile In the memorizer memory devices of memory modules and intelligent card chip, this Memory Controller includes HPI, memory interface And memory management circuitry.HPI is electrically connected to host computer system.Memory interface is electrically connected to can Manifolding formula non-volatile memory module, wherein reproducible nonvolatile memorizer module have several physics erased cells, And each physics erased cell has several physics programming units.Memory management circuitry is electrically connected with HPI and is connect with memory Mouthful, memory management circuitry is used to receive write instruction from host computer system, and the write-in data wherein corresponding to write instruction include Multiple subdatas, and each subdata is installed in the indivedual additional data directory marks of application program of host computer system.It is above-mentioned to write It is the initial data for corresponding to application program memorizer memory devices to be sent to enter data, and memorizer memory devices and application journey Sequence agreement in advance has the first rule, and the first rule includes that preset function, initial parameter value selection mode and parameter value increase mode newly. And application program according to initial parameter value selection mode select an initial parameter value, and by initial parameter value substitute into preset function with Acquisition is attached to the data directory mark of the first stroke subdata in initial data, and increases mode, the first stroke newly according to parameter value The data directory of subdata marks the order with above-mentioned subdata in initial data, and decision is attached to individually remaining subdata Data directory is marked.Memory management circuitry is also to according to the first regular and each subdata reached an agreement in advance with application program Data directory mark come subdata of resequencing.Memory management circuitry is also used to be sent to the subdata after rearrangement Intelligent card chip.

From the point of view of another viewpoint, a kind of memorizer memory devices of present invention proposition, including connector, duplicative are non-volatile Property memory module, intelligent card chip and Memory Controller.Wherein, connector is electrically connected to host computer system.Can Manifolding formula non-volatile memory module has multiple physics erased cells, and each physics erased cell has multiple physics programmings Unit.Memory Controller is electrically connected to connector, reproducible nonvolatile memorizer module and intelligent card chip.Storage Device controller is used to receive write instruction from host computer system, and the write-in data wherein corresponding to write instruction include multiple subnumbers According to, and each subdata is installed in the indivedual additional data directory marks of application program of host computer system.Above-mentioned write-in data are The initial data of correspondence application program memorizer memory devices to be sent to, and memorizer memory devices are assisted in advance with application program Surely there is the first rule, the first rule includes that preset function, initial parameter value selection mode and parameter value increase mode newly.And apply journey Sequence selectes an initial parameter value according to initial parameter value selection mode, and it is additional to obtain that initial parameter value is substituted into preset function The data directory mark of the first stroke subdata into initial data, and the newly-increased mode of foundation parameter value, the first stroke subdata Data directory marks the order with above-mentioned subdata in initial data, and decision is attached to individually the data directory of remaining subdata Mark.Memory Controller also to according to and the first regular and each subdata data directory for reaching an agreement in advance of application program Mark is come subdata of resequencing.Memory Controller is also used to for the subdata after rearrangement to be sent to intelligent card chip.

It is of the invention when the write-in data that the application program for being installed on host computer system is transmitted are received based on above-mentioned, according to It is attached to after the data directory mark of write-in data is rearranged and is resent to intelligent card chip.Also, host computer system with Memorizer memory devices can transmit data according to the rule of agreement in advance from communication document.Accordingly, intelligent the core of the card is being ensured While piece can receive correct data, the situation for reducing malicious application interference data transmission is produced.

It is that features described above of the invention and advantage can be become apparent, special embodiment below, and coordinate institute's accompanying drawings It is described in detail below.

Brief description of the drawings

Figure 1A is the signal of the host computer system of the use memorizer memory devices illustrated according to an exemplary embodiment of the invention Figure.

Figure 1B is computer according to depicted in exemplary embodiment of the present invention, input/output device and memory storage dress The schematic diagram put.

Fig. 1 C are the signals of the host computer system according to depicted in another exemplary embodiment of the invention and memorizer memory devices Figure.

Fig. 2 is the schematic block diagram for illustrating the memorizer memory devices shown in Figure 1A.

Fig. 3 is the schematic block diagram of the Memory Controller illustrated according to an exemplary embodiment of the invention.

Fig. 4,5 are to manage manifolding formula non-volatile memory module depicted in an exemplary embodiment of the invention Schematic diagram.

Fig. 6 is non-volatile with file system format duplicative depicted in an exemplary embodiment of the invention The example of the logic erased cell of memory module.

Fig. 7 is the schematic diagram of the write instruction that the operating system depicted in an exemplary embodiment of the invention is assigned.

Fig. 8 A to 8D are the schematic diagrames of the data processing depicted in an exemplary embodiment of the invention.

The write instruction that intelligent card chip is reached under depicted in Fig. 9 A exemplary embodiments of the invention is shown It is intended to.

Fig. 9 B are the schematic diagrames of the response message of the corresponding write instruction depicted in an exemplary embodiment of the invention.

Figure 10 is the flow chart of the data processing method depicted in an exemplary embodiment of the invention.

[main element label declaration]

1000：Host computer system 1100：Computer

1102：Microprocessor 1104：Random access memory

1110：Operating system 1120：Application program

1106：Input/output device 1108：System bus

1115：Data transmission interface 1202：Mouse

1204：Keyboard 1206：Display

1208：Printer 1212：Portable disk

1214：Storage card 1216：Solid state hard disc

1310：Digital camera 1312：SD card

1314：Mmc card 1316：Memory stick

1318：CF cards 1320：Embedded storage device

100：Memorizer memory devices 102：Connector

104：Memory Controller 106：Reproducible nonvolatile memorizer module

108：Intelligent card chip 1041：Host system interface

1043：Memory management circuitry 1045：Memory interface

3002：Error checking and correcting circuit 3004：Buffer storage

3006：Electric power management circuit 410 (0)~410 (N)：Physics erased cell

502：Data field 504：Idle area

506：System area 508：Substitution area

610 (0)~610 (L)：Logic erased cell 600：Cut section

602：MBS 604：File configuration table area

606：Root directory area 608：File area

A、T、D、D₁、D_m、I₁、I_m、P、S、L、F：Field

SD₁、SD₂、SD₃、SD₄：Subdata P₁、P₂、P₃、P₄：Data directory is marked

OSX₁、OSX₂：Assistance data X₁、X₂：Malicious data

S1010~S1060：Each step of the data processing method described in one embodiment of the invention

Specific embodiment

In general, memorizer memory devices (also known as, memory storage system) include duplicative non-volatile memories Device module and controller (also known as, controlling circuit).Being commonly stored device storage device is used together with host computer system, so that main frame System can write data into memorizer memory devices or be read from memorizer memory devices data.

Figure 1A is showing for the host computer system of the use memorizer memory devices according to depicted in an exemplary embodiment of the invention It is intended to.

Host computer system 1000 includes computer 1100 and input/output (Input/Output, I/O) device 1106.Calculate Machine 1100 includes microprocessor 1102, random access memory (Random Access Memory, RAM) 1104, system bus 1108 and data transmission interface 1115.Microprocessor 1102 can perform the operation system being installed in random access memory 1104 System 1110 and application program 1120, so that host computer system 1000 provides corresponding function according to the operation of user.Input/defeated Going out device 1106 includes mouse 1202 as shown in Figure 1B, keyboard 1204, display 1206 and printer 1208.Have to be understood that It is, the unrestricted input/output device 1106 of the device shown in Figure 1B that input/output device 1106 can also include other devices.

In exemplary embodiment of the present invention, memorizer memory devices 100 are by data transmission interface 1115 and main frame system Other elements of system 1000 are electrically connected with.By microprocessor 1102, random access memory 1104 and input/output device 1106 running, host computer system 1000 can be write data into memorizer memory devices 100, or from memorizer memory devices 100 Middle reading data.For example, memorizer memory devices 100 can be storage card 1214, portable disk 1212 or solid as shown in Figure 1B State hard disk (SolidState Drive, SSD) 1216.

In general, host computer system 1000 is any system that can store data.Although the main frame in this exemplary embodiment System 1000 is explained with computer system, however, in another exemplary embodiment of the invention, host computer system 1000 also may be used Being the systems such as mobile phone, digital camera, video camera, communication device, audio player or video player.For example, in main frame system Unite during for digital camera 1310, memorizer memory devices are then for its secure digital (Secure Digital, SD) for being used blocks 1312nd, multimedia storage (Multimedia Card, MMC) card 1314, memory stick (Memory Stick) 1316, compact flash (Compact Flash, CF) blocks 1318 or embedded storage devices 1320 (as shown in Figure 1 C).Embedded storage device 1320 is wrapped Include embedded multi-media card (Embedded MMC, eMMC).It is noted that embedded multi-media card is directly to be electrically connected with In on the substrate of host computer system.

Fig. 2 is the block diagram for illustrating the memorizer memory devices 100 shown in Figure 1A.Refer to Fig. 2, memorizer memory devices 100 include connector 102, Memory Controller 104, reproducible nonvolatile memorizer module 106 and intelligent card chip 108。

Connector 102 is electrically connected to Memory Controller 104, and is for electrically connecting to host computer system 1000.At this In exemplary embodiment, the coffret species that connector 102 is supported is secure digital (Secure Digital, SD) interface. But in other exemplary embodiments, the coffret species of connector 102 can also be the advanced annex (Serial of sequence Advanced Technology Attachment, SATA) interface, Multi Media Card (Multimedia Card, MMC) connect Mouth, parallel advanced annex (ParallelAdvanced Technology Attachment, PATA) interface, Electrical and Electronic work SCTE (Instituteof Electrical and Electronic Engineers, IEEE) 1394 interfaces, high speed are outer Enclose component connecting interface (Peripheral Component Interconnect Express, PCI Express) interface, lead to With serial bus (Universal Serial Bus, USB) interface, a ultrahigh speed generation (Ultra High Speed-I, UHS-I) Interface, the generation of ultrahigh speed two (Ultra High Speed-II, UHS-II) interface, memory stick (Memory Stick, MS) interface, Built-in multimedia memory card (Embedded Multimedia Card, eMMC) interface, Common Flash Memory (Universal Flash Storage, UFS) interface, compact flash (Compact Flash, CF) interface, or integrated driving electronics Any applicable interfaces such as (Integrated Drive Electronics, IDE) interface, are not any limitation as herein.

Memory Controller 104 can perform the multiple gates or control instruction with hardware pattern or firmware pattern implementation, And the write-in of data is carried out in reproducible nonvolatile memorizer module 106 according to the instruction of host computer system 1000, is read With the running such as erase.Wherein, Memory Controller 104 is also especially used to be located according to the data processing method of this exemplary embodiment Manage the data of the intelligent card chip 108 to be write of host computer system 1000.The data processing method of this exemplary embodiment will be in rear cooperation Diagram is explained again.

Reproducible nonvolatile memorizer module 106 is electrically connected to Memory Controller 104.Duplicative is non-volatile Property memory module 106 be multi-level cell memory (Multi Level Cell, MLC) NAND flash memory module, but the present invention do not limit In this, reproducible nonvolatile memorizer module 106 can also be single-order memory cell (Single Level Cell, SLC) NAND flash memory module, other flash memory modules or any memory module with identical characteristics.Furthermore, it is understood that duplicative is non- Volatile 106 includes multiple physics erased cells, and each physics erased cell has multiple physics programmings single Unit.Belonging to the physics programming unit of same physics erased cell can be written independently and simultaneously be erased.That is, Physics erased cell is the least unit erased.That is, each physics erased cell contains being erased in the lump for minimal amount Memory cell.Physics programming unit is the minimum unit of programming.That is, physics programming unit is the minimum unit for writing data. In this exemplary embodiment, physics erased cell is physical blocks, and physics programming unit is physical page, but the present invention is not with this It is limited.

Fig. 3 is the schematic block diagram of the Memory Controller according to depicted in an exemplary embodiment of the invention.Refer to figure 3, Memory Controller 104 includes host system interface 1041, memory management circuitry 1043, and memory interface 1045.

Host system interface 1041 is electrically connected to memory management circuitry 1043, and by connector 102 electrically connecting Connect host computer system 1000.Host system interface 1041 is used to receive instruction and the data transmitted with identification host computer system 1000. Accordingly, the instruction that host computer system 1000 is transmitted can be sent to memory management electricity with data by host system interface 1041 Road 1043.In this exemplary embodiment, host system interface 1041 corresponds to connector 102 and is SD interface, and in other examples In embodiment, host system interface 1041 can also be SATA interface, MMC interfaces, PATA interfaces, the interfaces of IEEE 1394, PCI Express interfaces, USB interface, UHS-I interfaces, UHS-II interfaces, eMMC interfaces, UFS interfaces, MS interfaces, CF interfaces, IDE connect Mouthful or meet the interface of other interface standards.

Memory management circuitry 1043 is used to the overall operation of control memory controller 104.Specifically, memory pipe Reason circuit 1043 has multiple control instructions, when memorizer memory devices 100 are operated (power on), above-mentioned control instruction Can be performed to realize the data processing method of this exemplary embodiment.

In an exemplary embodiment, the control instruction of memory management circuitry 1043 is to carry out implementation with firmware pattern.For example, Memory management circuitry 1043 has microprocessor unit (not illustrating) and read-only storage (not illustrating), and above-mentioned control instruction It is to be programmed in read-only storage.When memorizer memory devices 100 are operated, above-mentioned control instruction can be by microprocessor unit To perform the data processing method to complete this exemplary embodiment.

In another exemplary embodiment of the invention, the control instruction of memory management circuitry 1043 can also procedure code pattern The specific region of reproducible nonvolatile memorizer module 106 is stored in (for example, reproducible nonvolatile memorizer module The system area of storage system data is exclusively used in 106) in.Additionally, memory management circuitry 1043 has microprocessor unit (not Illustrate), read-only storage (not illustrating) and random access memory (not illustrating).Wherein, read-only storage has driving code section, And when Memory Controller 104 is enabled, microprocessor unit can first carry out this driving code section and will be stored in and can make carbon copies Control instruction in formula non-volatile memory module 106 is loaded onto the random access memory of memory management circuitry 1043 In.Afterwards, microprocessor unit can operate above-mentioned control instruction to perform the data processing method of this exemplary embodiment.

Additionally, in another exemplary embodiment of the invention, the control instruction of memory management circuitry 1043 can also be one hard Part pattern carrys out implementation.For example, memory management circuitry 1043 includes that microcontroller, MMU, memory are write Enter unit, memory reading unit, memory erased cell and data processing unit.MMU, memory write Unit, memory reading unit, memory erased cell and data processing unit are electrically connected to microcontroller.Wherein, deposit Reservoir administrative unit is used to manage the physics erased cell in reproducible nonvolatile memorizer module 106.Memory write Unit is used to assign write instruction to reproducible nonvolatile memorizer module 106 non-easily to duplicative to write data into In the property lost memory module 106.Memory reading unit is used to assign reading to reproducible nonvolatile memorizer module 106 Instruction reads data with from reproducible nonvolatile memorizer module 106.Memory erased cell is used to duplicative Non-volatile memory module 106 is assigned instruction of erasing and is smeared from reproducible nonvolatile memorizer module 106 with by data Remove.And data processing unit is used to process and is intended to write to the data of reproducible nonvolatile memorizer module 106 and from can The data read in manifolding formula non-volatile memory module 106.

Memory interface 1045 is electrically connected to memory management circuitry 1043 so that Memory Controller 104 with can answer Formula non-volatile memory module 106 is write to be electrically connected with each other.Accordingly, Memory Controller 104 can be non-volatile to duplicative Property memory module 106 carries out related running.That is, being intended to write to reproducible nonvolatile memorizer module 106 Data can be converted to the receptible form of the institute of reproducible nonvolatile memorizer module 106 via memory interface 1045.

In another example of the present invention embodiment, Memory Controller 104 also includes error checking and correcting circuit 3002.Error checking is electrically connected to memory management circuitry 1043 with correcting circuit 3002, is used to perform error checking and school Positive program is ensuring the correctness of data.Specifically, when memory management circuitry 1043 is received from host computer system 1000 Write instruction when, error checking and correcting circuit 3002 can be the corresponding error checking of data generation of corresponding this write instruction With correcting code (ErrorChecking and Correcting Code, ECC Code), and memory management circuitry 1043 can be by The data of corresponding this write instruction are write to reproducible nonvolatile memorizer module with corresponding error checking and correcting code 106.Afterwards when memory management circuitry 1043 reads data from reproducible nonvolatile memorizer module 106, can be same When read the corresponding error checking of this data and correcting code, and error checking and correcting circuit 3002 can according to this error checking with Correcting code performs error checking and correction program to the data for being read, to recognize that the pen data whether there is error bit.

In another example of the present invention embodiment, Memory Controller 104 also includes buffer storage 3004.Buffering is deposited Reservoir 3004 can be static RAM (Static Random AccessMemory, SRAM) or dynamic random Access memory (Dynamic Random Access Memory, DRAM) etc., the present invention is not any limitation as.Buffer storage 3004 are electrically connected to memory management circuitry 1043, are configured to temporarily store the instruction and data for coming from host computer system 1000, or temporarily Deposit the data for coming from reproducible nonvolatile memorizer module 106.

In another exemplary embodiment of the invention, Memory Controller 104 also includes electric power management circuit 3006.Power supply pipe Reason circuit 3006 is electrically connected to memory management circuitry 1043, to the power supply of control memory storage device 100.

Fig. 4,5 are management reproducible nonvolatile memorizer modules depicted in an exemplary embodiment of the invention 106 schematic diagram.

When being described below the running of physics erased cell of reproducible nonvolatile memorizer module 106, " to carry Take ", " exchange ", " packet ", the word such as " rotating " carrys out operating physical erased cell is concept in logic.That is, can make carbon copies The physical location of the physics erased cell of formula non-volatile memory module 106 is not changed, but in logic to duplicative The physics erased cell of non-volatile memory module 106 carries out aforesaid operations.

Fig. 4 is refer to, the reproducible nonvolatile memorizer module 106 of this exemplary embodiment includes physics erased cell 410 (0)~410 (N).Memory management circuitry 1043 in Memory Controller 104 can by physics erased cell 410 (0)~ 410 (N) are logically grouped into data field 502, idle area 504, system area 506 and substitution area 508.F that wherein, Fig. 4 is indicated, S, R and N are positive integer, represent the physics erased cell quantity of each area's configuration, and it can be by the manufacturer of memorizer memory devices 100 Set according to the capacity of the reproducible nonvolatile memorizer module 106 for being used.

It is to store to come from host computer system that data field 502 is logically belonged to the physics erased cell in idle area 504 1000 data.For example, the physics erased cell of data field 502 is regarded as having stored the physics erased cell of data, And the physics erased cell in idle area 504 is the physics erased cell for writing new data.In other words, leave unused area 504 Physics erased cell is empty or usable physics erased cell (no record data or labeled as invalid data useless).When When receiving write instruction with the data to be write from host computer system 1000, memory management circuitry 1043 can be from idle area 504 Middle extracts physical erased cell, and write data into the physics erased cell for being extracted, with the thing in replacement data area 502 Reason erased cell.Or, when needing to perform data consolidation procedure to a logic erased cell, the meeting of memory management circuitry 1043 From the extracts physical erased cell of idle area 504 and write data into the thing that this logic erased cell is wherein originally mapped to replace Reason erased cell.

The physics erased cell for logically belonging to system area 506 is to record system data.For example, system data Including the manufacturer on reproducible nonvolatile memorizer module 106 and model, type nonvolatile mould The physics erased cell number of block 106, physics programming unit number of each physics erased cell etc..

The physics erased cell for logically belonging to replace area 508 is used in data field 502, idle area 504 or system area When physics erased cell in 506 is damaged, replacing damaged physics erased cell.Specifically, in memorizer memory devices 100 During running, if the physics erased cell for still having normal physics erased cell and data field 502 in substitution area 508 is damaged When, memory management circuitry 1043 can extract normal physics erased cell and damage changing in data field 502 from substitution area 508 Bad physics erased cell.If without normal physics erased cell and when physics erased cell occurring damaging in substitution area 508, Then whole memory storage device 100 can be declared as write protection (writeprotect) shape by memory management circuitry 1043 State, and cannot again write data.

Also therefore, in the operation of memorizer memory devices 100, data field 502, idle area 504, system area 506 Physics erased cell with substitution area 508 can dynamically change.For example, the physics erased cell of the storage data that are used to rotate can become Belong to data field 502 or idle area 504 dynamicly.

Fig. 5 is refer to, in order to reproducible nonvolatile memorizer module 106 can be deposited for host computer system 1000 Take, memory management circuitry 1043 (or Memory Controller 104) can configure several logic erased cells 610 (0)~610 (L) To map the physics erased cell 410 (0)~410 (F-1) in data field 502.Wherein, each logic erased cell includes multiple Programming in logic unit, and the programming in logic unit in logic erased cell 610 (0)~610 (L) can map physics erased cell Physics programming unit in 410 (0)~410 (F-1).

In detail, the logic erased cell 610 that memory management circuitry 1043 (or Memory Controller 104) will be configured (0)~610 (L) is supplied to host computer system 1000, and service logic address-physical address mapping table to record logic erased cell The mapping relations of 610 (0)~610 (L) and physics erased cell 410 (0)~410 (F-1).Therefore, when host computer system 1000 is intended to When accessing a logical address, memory management circuitry 1043 (or Memory Controller 104) can be confirmed corresponding to this logical address Logic erased cell and programming in logic unit, then its physics for being mapped is found by logical address-physical address mapping table Programming unit enters line access.

In this exemplary embodiment, the operating system 1110 of host computer system 1000 uses file system by logic erased cell 610 (0)~610 (L) are formatted into a cut section (partition) 600 as shown in Figure 6, and wherein cut section 600 includes master Boot sector 602, file configuration table area 604, root directory area 606 and file area 608.

The programming in logic unit for belonging to MBS 602 is the stored sky for storing memorizer memory devices 100 Between system information.

The programming in logic unit for belonging to file configuration table area 604 is to store files allocation list.File configuration table is to use To record gathering together corresponding to the logical address of store files.For example, two file configuration tables can be stored in file configuration table area, One of file configuration table is used by normal access, and another file configuration table is backup file configuration table.

The programming in logic unit for belonging to root directory area 606 is to store files description block (FileDescription Block, FDB), its attribute information for being used to record the file and catalogue being stored at present in memorizer memory devices 100.Especially It is that file description block can record to store the initial storage address (that is, starting is gathered together) of this little file.

Belonging to the programming in logic unit of file area 608 can be divided into multiple gathering together and to practically store files Content.In detail, disc storage least unit is sector, and each sector contains the information content of 512 bytes (byte).So And, using sector when unit is to store, the efficiency of host computer system 1000 can be very poor.In general, the behaviour of host computer system 1000 Make system 1110 will not with a sector as accessing file unit, but to gather together as a basic access unit.It is each Individual gathering together is framework on 2 power multiples of sector.It is assumed that continuous 8 sectors constitute one gather together, then the size that this gathers together It is just 4096 bytes.Base this, can continuously be read with 8 sectors when data are accessed in operating system 1110 and improve relative effect Rate.

Fig. 2 is refer to back, in this exemplary embodiment, memorizer memory devices 100 also include intelligent card chip 108.Intelligence Energy the core of the card piece 108 is to be electrically connected to Memory Controller 104 by interface 108a, and wherein interface 108a is to be specifically intended for and intelligence The interface that energy the core of the card piece 108 is communicated.

Intelligent card chip 108 have microprocessor, security module, read-only storage (Read OnlyMemory, ROM), with Machine accesses memory (Random Access Memory, RAM), electronics and erases formula programmable read only memory The element such as (Electrically Erasable Programmable Read-Only Memory, EEPROM), oscillator.It is micro- Processor is used to control the overall operation of intelligent card chip 108.Security module is used to storing the number into intelligent card chip 108 According to carrying out encryption and decryption.Oscillator clock signal required when being used to produce intelligent card chip 108 to operate.Random access memory is used To keep in the data or firmware program of computing.Electronics formula programmable read only memory of erasing is used to store user's data.It is read-only Memory is used to store the firmware program of intelligent card chip 108.Specifically, when intelligent card chip 108 is operated, intelligent the core of the card The microprocessor of piece 108 can perform the firmware program in read-only storage to perform related running.

Particularly, the security module of intelligent card chip 108 can perform a security mechanism to prevent from being intended to steal being stored in intelligence The attack of stored data in the core of the card piece 108.For example, this attack includes timing attack (timing attack), single electric power Analytical attack (single-power-analysis attack) or difference electric power analysis attack (differential-power- analysis).Additionally, the security mechanism performed by intelligent card chip 108 is to meet Federal Information Processing Standards (Federal Information Processing Standards, FIPS) 140-2 the tertiary gradient or greater degree or meet EMV EL The tertiary gradient or more high of (American Express, JCB, MasterCard and Visa Evaluation Level) Level.That is, intelligent card chip 108 is more than the fourth stage by FIPS 140-2 certification or pass through EMV EL Certification more than level Four.Here, FIPS is Federal Government formulating to the government organs and government except all military establishment The Open Standard that is used of contractor, wherein FIPS 140-2 have formulated the grade on data safety.Additionally, EMV is state Border financial circles bound pair is in point of sale (point-of-sale, POS) terminating machine of smart card and usable chip card, and bank Specialty transaction and the standard criterion of certification that ATM that mechanism is set extensively etc. is formulated.This specification is directed to chip Credit card and the standard set by the related software and hardware of the branch payment system (Payment System) of cash card.In this example reality Apply in example, by the running of intelligent card chip 108, memorizer memory devices 100 can provide the service with authentication, example Such as, micropayment service, ticket service etc..

It is noted that intelligent card chip 108 is to receive to come from by the connector 102 of memorizer memory devices 100 Instruction and data in host computer system 1000, or host computer system 1000 is transferred data to, and it is non-immediate by intelligent card interface (that is, interface 108a) is communicated with host computer system 1000.Base this, in this exemplary embodiment, application program 1120 can be installed in In host computer system 1000, and director data unit is transmitted using specific communication document to intelligent card chip 108, instruct number According to unit be, for example, instruction-Application Protocol Data Unit (Command-Application Protocol Data Unit, C-APDU) and receive intelligent card chip 108 ResponseAPDU, such as response-Application Protocol Data Unit (Response-Application Protocol Data Unit, R-APDU).

Further, Memory Controller 104 can produce one or more communication documents in memorizer memory devices 100, and And the information transmission of the logical address for storing this one or more communication document will be used to application program 1120.For example, work as should When assigning the instruction of one communication document of storage in memorizer memory devices 100 with program 1120, operating system 1110 can root This communication document is write using the logical address of part according to the file system (not illustrating) of memorizer memory devices 100.Here, Be used to store the logical address of this communication document is referred to as specific logic address.Afterwards, for the operation of intelligent card chip 108 Can enter line access to communication document by application program 1120 to complete.For example, application program 1120 can be by communication document Write instruction C-APDU is sent to memorizer memory devices 100 and is instructed from memory by reading to communication document R-APDU is read in storage device 100.It is noted that in other operating systems, application program 1120 also can be directly right The specific logic address for being used to store communication document enters line access to perform the operation to intelligent card chip 108.

In this exemplary embodiment, the agreement one first in advance each other of host computer system 1000 and memorizer memory devices 100 Rule, and the write operation to intelligent card chip 108 is performed accordingly.First rule includes that preset function, initial parameter value are selected Mode and the newly-increased mode of parameter value.Wherein, initial parameter value selection mode is on how to select initial parameter value, for example originally When beginning parameter value selection mode is the date, application program 1120 is by using the date on the same day as initial parameter value.Parameter value is increased newly Mode is then on producing the increasing or decreasing rule between two parameter values of two pen data index markers, citing to priority For, it is assumed that it is 1 that parameter value increases mode newly to be incremented by and is incremented by amplitude, if being used to produce the initial of the first stroke data directory mark Parameter value is 1, then the parameter value for being used to produce the second pen data index marker is then 2.

When application program 1120 is intended to for an initial data to write intelligent card chip 108, application program 1120 is according to minimum basis Initial data is divided into multiple subdatas, such as one size of sector (512 byte), but the present invention by the capacity of this access unit It is not limited thereto.Also, application program 1120 selectes an initial parameter value according to initial parameter value selection mode, then will be initial Parameter value substitutes into preset function to obtain the first data directory mark.This first data directory mark can be attached to by initial data The first stroke subdata for being marked off.Next, application program 1120 is according to the newly-increased mode of parameter value, the number of the first stroke subdata Order according to index marker with all subdatas in initial data, decision is attached to individually the data directory mark of remaining subdata Note.

Because the initial data to be write of application program 1120 must be sent to memory storage via operating system 1110 Device 100, but operating system 1110 is in order to accelerate overall access speed, can be to the order gathered together in accessing file area 608 Carry out optimization treatment.Base this, operating system 1110 goes the sequencing for accessing each subdata can after optimization treatment is carried out Energy is identical or is different from order of these subdatas in initial data.Even if that is, operating system 1110 be in response to should Memorizer memory devices 100 are sent with write instruction with the write-in demand of program 1120, but memory management circuitry 1043 (or Memory Controller 104) received by write-in data and the initial data actually to be write of application program 1120 may be It is different.

But in this exemplary embodiment, because application program 1120 all addition of individually expression in every subdata The data directory mark of its order in initial data, therefore memory management circuitry 1043 (or Memory Controller 104) After write-in data are received, can be marked come all of son of resequencing according to the first regular and each subdata data directory Data, make it restore to its in initial data identical sequentially, and by rearrangement after above-mentioned subdata be sent to Intelligent card chip 108.Specifically, memory management circuitry 1043 (or Memory Controller 104) is selected according to initial parameter value The mode of selecting determines the initial parameter value that application program 1120 is selected, and then substitutes into preset function to obtain one by initial parameter value Functional value, further in accordance with functional value, the newly-increased mode of parameter value just can be by all subdata weights with the data directory mark of each subdata Newly it is arranged as meeting its order in initial data.

As an example it is assumed that preset function is following formula (1)：

F(X)=X² (1)

Wherein, X is parameter value.And assume memory management circuitry 1043 (or Memory Controller 104) according to initial ginseng Numerical value selection mode determines that the initial parameter value that application program 1120 is selected is 3, and the newly-increased mode of parameter value is to be incremented by and passs Amplification degree is 1.If receiving the data directory of a subdata Y labeled as 9, memory management circuitry 1043 (or memory control Device 104) after numerical value 3 is obtained after corresponding (1) carries out inverse square computing to 9, you can in judging that subdata Y is initial data The first stroke subdata.And can determine that to produce what second data directory of subdata was marked based on the newly-increased mode of parameter value Parameter is 4, as long as therefore searched in received all subdatas corresponding data directory labeled as 4 square (i.e., 16) subdata, that is, find out second subdata in initial data.All subdatas just can be obtained by that analogy to exist originally Order in initial data, can rearrange subdata accordingly.

In other exemplary embodiments, preset function can be following formula (2)：

F(X)=X³ (2)

Wherein, X is parameter value, but be should be noted that, formula (1) is with formula (2) merely to illustrating the example enumerated, this hair It is bright to be not limited thereto.

Fig. 7 is the signal of the write instruction that the operating system 1110 depicted in an exemplary embodiment of the invention is assigned Figure.Fig. 7 is referred to, field A is used to record the logical address to be write.Field T is used to record a special marking, represents that this pen is write Entering data is write to intelligent card chip 108.Field D is used to record the data content to be write, wherein, D₁To D_mUse respectively To record each content of subdata, and I₁To I_mThen it is used to record the content of corresponding data directory mark respectively, and m is for just Integer.Field P is then used to record the information to the testing mechanism for avoiding write error related.

To below be illustrated with Fig. 8 A to Fig. 8 D when 1120 initial data to be write of application program, host computer system 1000 with How memorizer memory devices 100 are properly completed the write operation to intelligent card chip 108 according to the first rule.

Refer to Fig. 8 A, it is assumed that application program 1120 will be original according to the capacity of the basic access unit of host computer system 1000 Data are sequentially divided into subdata SD₁To SD₄.For the first stroke subdata SD₁, application program 1120 is according to initial parameter value selection Mode selectes initial parameter value, and initial parameter value substitution preset function is attached into the first stroke subdata SD to obtain₁Number According to index marker P₁.Assuming that initial parameter value is numerical value 1 and preset function is above-mentioned formula (1), then data directory marks P₁It is numerical value 1.For its excess-three subdata SD₂To SD₄, application program 1120 is according to the newly-increased mode of parameter value, the first stroke for previously producing Data SD₁Data directory mark P₁To produce three data index marker P₂To P₄.Continue above-mentioned example, if parameter value is newly-increased Mode is 1 for incremental and incremental amplitude, then be used to produce subdata SD₂To SD₄Data directory mark P₂To P₄Three ginseng Numerical value is respectively numerical value 2,3,4.Above-mentioned parameter value is substituted into formula (1) just can be respectively attached to subdata SD₂To SD₄Number According to index marker P₂To P₄It is then numerical value 4,9,16.But it must be stressed that above-mentioned preset function, initial parameter value selection mode With the newly-increased mode of parameter value merely to explanation and the example enumerated, the present invention is not limited thereto.

In this exemplary embodiment, operating system 1110 for seek the overall access speed of lifting and and not according to subdata SD₁ To SD₄Order in initial data enters line access, and needs during file system is inquired about additionally to access some auxiliary Data are helped, as shown in Figure 8 B, it is assumed that the order of the actual access of operating system 1110 is subdata SD₄, assistance data OSX₁, auxiliary Data OSX₂, subdata SD₁, subdata SD₂, and subdata SD₃, then memory management circuitry 1043 (or memory control Device 104) received by the corresponding write-in data of write instruction can then include with the subdata that sequentially occurs shown in Fig. 8 B and auxiliary Help data.

Memory management circuitry 1043 (or Memory Controller 104) can't directly according to each son after receiving write instruction Data orders in the fig. 8b is sent to intelligent card chip 108, and can determine application program according to the first rule 1120 data directory mark (that is, the data directory mark P that the first stroke subdata can be attached in this write operation₁), and Whichever is found out accordingly for the first stroke subdata (that is, subdata SD₁).Also, memory management circuitry 1043 (or memory control Device 104) mark P according to data directory₁With the newly-increased mode of parameter value determine that subdata SD can be attached to₂To SD₄Data directory Mark P₂To P₄As long as, and can interpretation data index marker P according to the newly-increased mode of parameter value₁To P₄Order, just can accordingly by Subdata SD₁To SD₄Order be rearranged for meeting its order in initial data.In addition, due to memory management Circuit 1043 (or Memory Controller 104) is identified in field T receiving the write instruction that operating system 1110 sends It is first to assume that all data in field D are all intelligent card chips to be write 108 after special marking, but when memory pipe Reason circuit 1043 (or Memory Controller 104) watches out assistance data OSX₁、OSX₂Any data directory mark is not attached Note, then can judge assistance data OSX₁、OSX₂It is not belonging to the initial data to be write of application program 1120.Base this, memory management Circuit 1043 (or Memory Controller 104) is getting rid of assistance data OSX₁、OSX₂And rearrange subdata SD₁To SD₄Afterwards, Data content as shown in Figure 8 C can be sent to intelligent card chip 108.

In another exemplary embodiment, as in fig. 8d, it is assumed that operating system 1110 does not change each subdata of access Sequentially, however host computer system 1000 there is malicious application so that operating system 1110 is between write-in subdata SD2 and SD3 Also two malicious data X to be write₁、X₂.Due to malicious data X₁、X₂Also the additional data directory mark of application program 1120 is lacked Note, therefore memory management circuitry 1043 (or Memory Controller 104) will be sent to the data of intelligent card chip 108 in preparation When, also can be by malicious data X₁、X₂Reject, can so avoid the write operation of intelligent card chip 108 from being disturbed by rogue program.

In another example of the present invention embodiment, except depositing between host computer system 1000 and memorizer memory devices 100 Outside above-mentioned first rule, the Second Rule also reached an agreement in advance each other, and come right with Second Rule according to the first rule Intelligent card chip 108 carries out write operation and can further reduce the probability disturbed by rogue program.

In detail, all communication documents of the record in file area 608 are between host computer system 1000 and intelligent card chip 108 Communication interface, when application program 1120 needs to write data into intelligent card chip 108, it is necessary to selection use a certain communication File transmits data, and Second Rule is on how to select this in all communication documents of file area 608 from record The secondary communication document for using.In this exemplary embodiment, application program 1120 can be by corresponding to selected communication document In the middle of the additional subdata wherein of file identification mark.For example, application program 1120 be file identification is marked it is attached It is added in finishing touch subdata.

After memory management circuitry 1043 (or Memory Controller 104) receives write instruction, first according to Two rules determine the selected communication text in this secondary data write operation of application program 1120 from all of communication document Part (hereinafter referred to as target communication file), then checks in all subdatas included by write-in data, if there is a son File identification mark of the data attached by it corresponds to target communication file.If so, memory management circuitry 1043 (or storage Device controller 104) subdata of resequencing just is gone according to the first regular and each subdata data directory mark.

That is, having only when the communication document selected by this secondary write-in data meets host computer system 1000 and memory The Second Rule that storage device 100 has been reached an agreement in advance, memory management circuitry 1043 (or Memory Controller 104) just carries out son The restructuring of data, and then the subdata that will be arranged is sent to intelligent card chip 108.Even if consequently, it is possible to malicious application The malicious data of interference is sent during application program 1120 will write data or is intended to be beaten by arbitrary access communication document The order of trouble data, then lack the information of Second Rule, therefore select and the identical of application program 1120 because of malicious application The probability of communication document is not high, base this can reduce interference occur probability.Application program 1120 is needing to write data next time When entering intelligent card chip 108, another communication document can be selected according to Second Rule.Memory management circuitry 1043 (or storage Device controller 104) then confirm whether the write-in data for receiving are sent by application program 1120 according to aforementioned manner, reduce dislike accordingly The interference effect that meaning application program is caused.

Fig. 9 A are to reach writing for intelligent card chip 108 by under memory management circuitry 1043 (or Memory Controller 104) Enter the schematic diagram of instruction.Fig. 9 A are referred to, field T is used to record special marking.Field L records the length of the data to be write. The data directory mark of field S records such as the first stroke subdata, the preset function information related to data safety.Field D is used To record the content (that is, the subdata after rearrangement) of the data to be write.And field F is then used to records application program 1120 The file identification mark of selected communication document in this secondary data write operation.

Memory management circuitry 1043 (or Memory Controller 104) will resequence using the write instruction such as Fig. 9 A Subdata afterwards is sent to after intelligent card chip 108, and the running result according to intelligent card chip 108 is simultaneously advised by according to second Response message is sent to host computer system 1000 by the communication document then determined, response message as shown in Figure 9 B, wherein field T It is used to record special marking.The length of the data that field L records are previously written.Field D is used to recording smart card chip 108 The content of response message is produced according to the content of previously written data.And field F is then to records application program 1120 at this The file identification mark of selected communication document in data write operation.

Figure 10 is referred to, in step S1010, memory management circuitry 1043 (or Memory Controller 104) is received to be come From the write instruction of host computer system 1000, the write-in data corresponding to this write instruction include multiple subdatas, and each subdata The application program 1120 for being installed in host computer system 1000 Fu Jia not data directory mark.Above-mentioned write-in data are that correspondence should With the initial data of the memorizer memory devices 100 to be sent to of program 1120, and memorizer memory devices 100 and application program 1120 agreements in advance have the first rule, and the first rule includes the newly-increased side of preset function, initial parameter value selection mode and parameter value Formula.Application program 1120 is to select an initial parameter value according to initial parameter value selection mode, and initial parameter value is substituted into pre- If function is marked with obtaining the data directory of the first stroke subdata being attached in initial data, and according to the newly-increased side of parameter value Formula, the data directory of the first stroke subdata mark the order with above-mentioned subdata in initial data, and decision is attached to individually it The data directory mark of minor data.

Then in step S1020, memory management circuitry 1043 (or Memory Controller 104) according to and host computer system 1000 Second Rules reached an agreement in advance, application program is determined from record in all of communication document of file area 608 1120 selected communication documents.

As shown in step S1030, memory management circuitry 1043 (or Memory Controller 104) judges to be additional to write-in number According to file identification mark whether the determined communication document of correspondence.

If it is not, then terminating the flow of the data processing method depicted in this exemplary embodiment.If so, then such as step S1040 Shown, memory management circuitry 1043 (or Memory Controller 104) is according to first reached an agreement in advance with host computer system 1000 The data directory mark of regular and each subdata, all of subdata of resequencing.

In step S1050, memory management circuitry 1043 (or Memory Controller 104) is by the subnumber after rearrangement According to being sent to intelligent card chip 108.

Finally as shown in step S1060, memory management circuitry 1043 (or Memory Controller 104) is by according to second Response message is sent to host computer system 1000 by the communication document that rule is determined.

In sum, data processing method of the present invention, Memory Controller and memorizer memory devices can ensure that The correctness of write operation is carried out to intelligent card chip, and malicious application can be reduced that interference is made during write operation Probability.

Although the present invention is disclosed above with embodiment, so it is not limited to the present invention, any art Middle tool usually intellectual, it is without departing from the spirit and scope of the present invention, therefore of the invention when a little change and retouching can be made Protection domain when being defined depending on the scope of the appended claims person of defining.

Claims

1. a kind of data processing method, for a reproducible nonvolatile memorizer module and an intelligent card chip Memorizer memory devices, the wherein reproducible nonvolatile memorizer module have multiple physics erased cells, and respectively this is more Individual physics erased cell has multiple physics programming units, and the method includes：

A write instruction is received from a host computer system, the write-in data corresponding to the write instruction include multiple subdatas, and The application program that each the plurality of subdata is installed in the host computer system adds individually data directory mark, the wherein write-in Data be to should application program be intended to be sent to an initial data of the memorizer memory devices, and the memorizer memory devices with Application program agreement in advance has one first rule, and first rule includes a preset function, an initial parameter value selection mode And the newly-increased mode of parameter value, and the application program selectes an initial parameter value according to the initial parameter value selection mode, and will The initial parameter value substitutes into the preset function to obtain the data rope for the first stroke subdata being attached in the initial data Tendering remembers, and data directory mark according to the newly-increased mode of the parameter value, the first stroke subdata exists with the plurality of subdata Order in the initial data, decision is attached to individually the data directory mark of remaining subdata in the plurality of subdata；

According to first regular and each the plurality of subdata the data directory mark, weight with application program agreement in advance It is suitable in the initial data that the plurality of subdata of new sort causes that the order of the plurality of subdata is same as the plurality of subdata Sequence；And

The plurality of subdata after by rearrangement is sent to the intelligent card chip.

2. data processing method according to claim 1, the wherein host computer system are provided with an operating system, and the application Program is that the initial data is sent into the memorizer memory devices by the operating system, and the application program is deposited substantially according to one The initial data is divided into the plurality of subdata, and order phase of the plurality of subdata in the write-in data by the capacity for taking unit With or be different from order of the plurality of subdata in the initial data.

3. data processing method according to claim 1, wherein according to first rule with application program agreement in advance Then and each the plurality of subdata the data directory mark, resequence the plurality of subdata the step of include：

The initial parameter value that the application program is selected is determined according to the initial parameter value selection mode；

The initial parameter value is substituted into the preset function to obtain a functional value；And

Marked with the data directory of each the plurality of subdata according to the functional value, the newly-increased mode of the parameter value, by the plurality of son Data permutation is to be consistent with the initial data.

4. data processing method according to claim 1, the wherein reproducible nonvolatile memorizer module have reflects Multiple logic erased cells of the plurality of physics erased cell of part are penetrated, the plurality of logic erased cell is at least formatted into One file configuration table area, a root directory area and a file area, and this document area stores multiple communication documents, the application program root According to the Second Rule with memorizer memory devices agreement in advance, one of the plurality of communication document is selected, and will be selected File identification mark corresponding to the communication document selected is additional to one of the plurality of subdata.

5. data processing method according to claim 4, wherein the step of the write instruction is received from the host computer system Afterwards, also include：

The selected communication document of the application program is determined from the plurality of communication document according to the Second Rule；And

When this document for being additional to the write-in data recognizes the determined communication document of mark correspondence, basis and this are just performed First regular and each the plurality of subdata the data directory mark of host computer system agreement in advance, resequences the plurality of The step of subdata.

6. data processing method according to claim 5, wherein the plurality of subdata after by rearrangement is sent to After the step of intelligent card chip, also include：

One response message to the host computer system, the wherein response is transmitted by the communication document determined according to the Second Rule Message includes the corresponding this document identification mark of determined communication document.

7. a kind of Memory Controller, for a reproducible nonvolatile memorizer module and an intelligent card chip In memorizer memory devices, the Memory Controller includes：

One HPI, is electrically connected to a host computer system；

One memory interface, is electrically connected to the reproducible nonvolatile memorizer module, and wherein the duplicative is non- Volatile has multiple physics erased cells, and each the plurality of physics erased cell has multiple physics programmings single Unit；And

One memory management circuitry, is electrically connected with the HPI and the memory interface, the memory management circuitry be used to from The host computer system receives a write instruction, and the write-in data wherein corresponding to the write instruction include multiple subdatas, and respectively The application program that the plurality of subdata is installed in the host computer system adds individually data directory mark, wherein the write-in number According to be to should application program be intended to be sent to an initial data of the memorizer memory devices, and the memorizer memory devices with should Application program in advance agreement have one first rule, this first rule include a preset function, an initial parameter value selection mode and One parameter value increases mode newly, and the application program selectes an initial parameter value according to the initial parameter value selection mode, and should Initial parameter value substitutes into the preset function to obtain the data directory for the first stroke subdata being attached in the initial data Mark, and the data directory according to the newly-increased mode of the parameter value, the first stroke subdata marked with the plurality of subdata at this Order in initial data, decision is attached to individually the data directory mark of remaining subdata in the plurality of subdata,

The memory management circuitry is also to according to the first regular and each the plurality of son with application program agreement in advance The data directory mark of data, the plurality of subdata of resequencing causes that the order of the plurality of subdata is same as the plurality of son Order of the data in the initial data,

The plurality of subdata after the memory management circuitry is also used to rearrangement is sent to the intelligent card chip.

8. Memory Controller according to claim 7, the wherein host computer system are provided with an operating system, and the application Program is that the initial data is sent into the memorizer memory devices by the operating system, and the application program is deposited substantially according to one The initial data is divided into the plurality of subdata, and order phase of the plurality of subdata in the write-in data by the capacity for taking unit With or be different from order of the plurality of subdata in the initial data.

9. Memory Controller according to claim 7, wherein the memory management circuitry is in basis and the application program First regular and each the plurality of subdata the data directory mark, the plurality of subdata of resequencing of agreement in advance When, be the initial parameter value that the application program selectes is determined according to the initial parameter value selection mode, by the initial parameter Value substitutes into the preset function to obtain a functional value, and according to the functional value, the newly-increased mode of the parameter value and each the plurality of subnumber According to the data directory mark, the plurality of subdata is rearranged for be consistent with the initial data.

10. the multiple logics of Memory Controller according to claim 7, the wherein memory management circuitry configuration are erased list Unit is with the plurality of physics erased cell of demapping section, and the memory management circuitry is by the plurality of logic erased cell at least lattice Formula is melted into a file configuration table area, a root directory area and a file area, and the multiple communication documents of storage to this document area,

The application program according to the Second Rule with memorizer memory devices agreement in advance, select the plurality of communication document its One of, and the file identification mark corresponding to selected communication document is additional to one of the plurality of subdata.

11. Memory Controllers according to claim 10, the wherein memory management circuitry are also used to from the main frame System is received after the write instruction, according to selected by the Second Rule determines the application program from the plurality of communication document Communication document, and when this document for being additional to the write-in data recognizes the determined communication document of mark correspondence, According to first regular and each the plurality of subdata the data directory mark with host computer system agreement in advance, arrange again The plurality of subdata of sequence.

12. Memory Controllers according to claim 11, wherein the memory management circuitry is after by rearrangement The plurality of subdata is sent to after the intelligent card chip, is also used to the communication document by being determined according to the Second Rule A response message to the host computer system is transmitted, the wherein response message includes that the corresponding this document of determined communication document is known Do not mark.

A kind of 13. memorizer memory devices, including：

A connector, is electrically connected to a host computer system；

One reproducible nonvolatile memorizer module, with multiple physics erased cells, and each the plurality of physics erased cell With multiple physics programming units；

One intelligent card chip；And

One Memory Controller, is electrically connected to the connector, the reproducible nonvolatile memorizer module and the smart card Chip,

The Memory Controller is used to receive a write instruction, the write-in wherein corresponding to the write instruction from the host computer system Data include multiple subdatas, and each the plurality of subdata is installed in the indivedual additional numbers of an application program of the host computer system According to index marker, wherein the write-in data be to should application program be intended to be sent to an original number of the memorizer memory devices According to, and the memorizer memory devices have one first rule with application program agreement in advance, first rule includes a default letter The newly-increased mode of number, an initial parameter value selection mode and a parameter value, and the application program is according to the initial parameter value selecting party Formula selectes an initial parameter value, and the initial parameter value is substituted into the preset function to obtain be attached in the initial data one The data directory mark of the first stroke subdata, and according to the newly-increased mode of the parameter value, the data rope of the first stroke subdata The order with the plurality of subdata in the initial data is remembered in tendering, and decision is attached to individually its minor in the plurality of subdata The data directory mark of data,

The Memory Controller is also to according to the first regular and each the plurality of subnumber with application program agreement in advance According to the data directory mark, the plurality of subdata of resequencing causes that the order of the plurality of subdata is same as the plurality of subnumber According to the order in the initial data,

The plurality of subdata after the Memory Controller is also used to rearrangement is sent to the intelligent card chip.

14. memorizer memory devices according to claim 13, wherein the host computer system is provided with an operating system, and is somebody's turn to do Application program is that the initial data is sent into the memorizer memory devices by the operating system, and the application program is according to a base The initial data is divided into the plurality of subdata by the capacity of this access unit, and the plurality of subdata is suitable in the write-in data Sequence is identical or is different from order of the plurality of subdata in the initial data.

15. memorizer memory devices according to claim 13, the wherein Memory Controller apply journey in basis with this First regular and each the plurality of subdata the data directory mark, the plurality of subdata of resequencing of sequence agreement in advance When, be the initial parameter value that the application program selectes is determined according to the initial parameter value selection mode, by the initial parameter Value substitutes into the preset function to obtain a functional value, and according to the functional value, the newly-increased mode of the parameter value and each the plurality of subnumber According to the data directory mark, the plurality of subdata is rearranged for be consistent with the initial data.

The multiple logics of 16. memorizer memory devices according to claim 13, the wherein Memory Controller configuration are erased Unit is with the plurality of physics erased cell of demapping section, and the Memory Controller is by the plurality of logic erased cell at least lattice Formula is melted into a file configuration table area, a root directory area and a file area, and the multiple communication documents of storage to this document area,

17. memorizer memory devices according to claim 16, the wherein Memory Controller are also used to from the main frame System is received after the write instruction, according to selected by the Second Rule determines the application program from the plurality of communication document Communication document, and when this document for being additional to the write-in data recognizes the determined communication document of mark correspondence, According to first regular and each the plurality of subdata the data directory mark with host computer system agreement in advance, arrange again The plurality of subdata of sequence.

18. memorizer memory devices according to claim 17, wherein the Memory Controller is after by rearrangement The plurality of subdata is sent to after the intelligent card chip, is also used to the communication document by being determined according to the Second Rule A response message to the host computer system is transmitted, the wherein response message includes that the corresponding this document of determined communication document is known Do not mark.