CN103870408A - Data processing method, memory controller and memory storage device - Google Patents
Data processing method, memory controller and memory storage device Download PDFInfo
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- CN103870408A CN103870408A CN201210551764.0A CN201210551764A CN103870408A CN 103870408 A CN103870408 A CN 103870408A CN 201210551764 A CN201210551764 A CN 201210551764A CN 103870408 A CN103870408 A CN 103870408A
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Abstract
The invention relates to a data processing method, a memory controller and a memory storage device. The method comprises receiving a write instruction from a host system, wherein write data corresponding to the write instruction comprise a plurality of subdata, each subdata is installed at an application program of the host system and a data index marker is added individually, and the application program determines the data index markers added to the each subdata according to a preset function, an initial parameter value selection mode and a parameter value newly increased mode included in a first rule concerted with the memory storage device in advance. The method also comprises reordering all subdata according to the first rule concerted with the application program in advance and the data index markers of the subdata. The method also comprises transmitting the reordered subdata to a smart card chip.
Description
Technical field
The invention relates to a kind of data processing method, and relate to especially a kind of for thering is the data processing method of memorizer memory devices of duplicative non-volatile memory module and intelligent card chip, with the memorizer memory devices and the Memory Controller that use the method.
Background technology
Along with user accepts to use stored value card and prepayment Stored Value gradually, make the use of smart card day by day universal.Smart card (Smart Card) is to have for example integrated circuit (IC) chip of the assembly of microprocessor, card operation system, security module and storer (IC chip), to allow holder to carry out scheduled operation.Smart card provides calculating, encryption, two-way communication and security function, makes this card except the function of storage data, can also reach the function that its stored data are protected.Use the subscriber identification module (Subscriber Identification Module, SIM) using in the cellular phone of global system for mobile communications (GSM) mechanism to block one of them exemplary applications for smart card.In general, smart card itself is limited to the specification of its integrated circuit, and therefore storage volume is limited.
Storage card is a kind of Data Holding Equipment, and it is generally using nand flash memory as Storage Media.Nand flash memory have advantages of can write, can erase and power-off after still can save data, in addition, along with the improvement of manufacturing technology, nand flash memory has that volume is little, access speed fast, with the advantage such as power consumption is low.
For the storage device simultaneously with smart card and storage card, in the time of the access instruction receiving from host computer system, need first differentiate access action to as if smart card or storage card.And because smart card is mostly in order to store significant data or the digital cash relevant to user's information, therefore how guarantees the security of access smartcard and promote fiduciary level, be the target that those skilled in the art endeavour.
Summary of the invention
In view of this, the invention provides a kind of memorizer memory devices, Memory Controller and data processing method, correctly processing host system wants to write the data of intelligent card chip.
The present invention proposes a kind of data processing method, for thering is the memorizer memory devices of duplicative non-volatile memory module and intelligent card chip, wherein duplicative non-volatile memory module has several physics unit of erasing, and each physics unit of erasing has several physics programming units, the method comprises from host computer system and receives and write instruction, this writes the corresponding data writing of instruction and comprises multiple subdatas, and each subdata is installed in the individually additional data directory mark of application program of host computer system.Above-mentioned data writing is the raw data that memorizer memory devices is delivered in corresponding application program tendency to develop, and memorizer memory devices and application program prearrange have the first rule, the first rule comprises that preset function, initial parameter value selection mode and parameter value increase mode newly.And application program is according to the selected initial parameter value of initial parameter value selection mode, and initial parameter value substitution preset function is attached to the data directory mark of the first stroke subdata in raw data to obtain, and according to data directory mark and the order of above-mentioned subdata in raw data of the newly-increased mode of parameter value, the first stroke subdata, decision is attached to individually the data directory mark of all the other subdatas.The method also comprises basis and the first rule of application program prearrange and the data directory mark of each subdata, all subdatas of resequencing, and the subdata after rearrangement is sent to intelligent card chip.
From another viewpoint, the present invention proposes a kind of Memory Controller, for having the memorizer memory devices of duplicative non-volatile memory module and intelligent card chip, this Memory Controller comprises host interface, memory interface and memory management circuitry.Host interface is in order to be electrically connected to host computer system.Memory interface is in order to be electrically connected to duplicative non-volatile memory module, and wherein duplicative non-volatile memory module has several physics unit of erasing, and each physics unit of erasing has several physics programming units.Memory management circuitry is electrically connected host interface and memory interface, memory management circuitry is in order to receive and to write instruction from host computer system, wherein write the corresponding data writing of instruction and comprise multiple subdatas, and each subdata is installed in the individually additional data directory mark of application program of host computer system.Above-mentioned data writing is the raw data that memorizer memory devices is delivered in corresponding application program tendency to develop, and memorizer memory devices and application program prearrange have the first rule, the first rule comprises that preset function, initial parameter value selection mode and parameter value increase mode newly.And application program is according to the selected initial parameter value of initial parameter value selection mode, and initial parameter value substitution preset function is attached to the data directory mark of the first stroke subdata in raw data to obtain, and according to data directory mark and the order of above-mentioned subdata in raw data of the newly-increased mode of parameter value, the first stroke subdata, decision is attached to individually the data directory mark of all the other subdatas.Memory management circuitry also in order to according to and the first rule of application program prearrange and the data directory mark of the each subdata subdata of resequencing.Memory management circuitry is also in order to be sent to intelligent card chip by the subdata after rearrangement.
From another viewpoint, the present invention proposes a kind of memorizer memory devices, comprises connector, duplicative non-volatile memory module, intelligent card chip and Memory Controller.Wherein, connector is in order to be electrically connected to host computer system.Duplicative non-volatile memory module has multiple physics unit of erasing, and each physics unit of erasing has multiple physics programming units.Memory Controller is electrically connected to connector, duplicative non-volatile memory module and intelligent card chip.Memory Controller, in order to receive and to write instruction from host computer system, wherein writes the corresponding data writing of instruction and comprises multiple subdatas, and each subdata is installed in the individually additional data directory mark of application program of host computer system.Above-mentioned data writing is the raw data that memorizer memory devices is delivered in corresponding application program tendency to develop, and memorizer memory devices and application program prearrange have the first rule, the first rule comprises that preset function, initial parameter value selection mode and parameter value increase mode newly.And application program is according to the selected initial parameter value of initial parameter value selection mode, and initial parameter value substitution preset function is attached to the data directory mark of the first stroke subdata in raw data to obtain, and according to data directory mark and the order of above-mentioned subdata in raw data of the newly-increased mode of parameter value, the first stroke subdata, decision is attached to individually the data directory mark of all the other subdatas.Memory Controller also in order to according to and the first rule of application program prearrange and the data directory mark of the each subdata subdata of resequencing.Memory Controller is also in order to be sent to intelligent card chip by the subdata after rearrangement.
Based on above-mentioned, the present invention, in the time that reception is installed on the data writing that the application program of host computer system transmits, is resent to intelligent card chip after being rearranged according to the data directory mark that is attached to data writing.And host computer system and memorizer memory devices can select communication document to transmit data according to the rule of prearrange.Accordingly, in guaranteeing that intelligent card chip can be received correct data, reduce the situation generation that malicious application interfering data transmits.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Brief description of the drawings
Figure 1A is the schematic diagram of the host computer system of the use memorizer memory devices that one exemplary embodiment illustrates according to the present invention.
Figure 1B is the schematic diagram of exemplary embodiment illustrates according to the present invention computing machine, input/output device and memorizer memory devices.
Fig. 1 C is another exemplary embodiment illustrates according to the present invention host computer system and the schematic diagram of memorizer memory devices.
Fig. 2 is the summary calcspar that illustrates the memorizer memory devices shown in Figure 1A.
Fig. 3 is the summary calcspar of the Memory Controller that one exemplary embodiment illustrates according to the present invention.
Fig. 4, the 5th, the schematic diagram of the management illustrating according to one example of the present invention embodiment manifolding formula non-volatile memory module.
Fig. 6 is the erase example of unit of the logic with file system format duplicative non-volatile memory module that illustrates according to one example of the present invention embodiment.
Fig. 7 is the schematic diagram that writes instruction that the operating system that illustrates according to one example of the present invention embodiment is assigned.
Fig. 8 A to 8D is the schematic diagram of the data processing that illustrates according to one example of the present invention embodiment.
Fig. 9 A is the schematic diagram that writes instruction to intelligent card chip of assigning illustrating according to one example of the present invention embodiment.
Fig. 9 B is the schematic diagram that the correspondence that illustrates according to one example of the present invention embodiment writes the response message of instruction.
Figure 10 is the process flow diagram of the data processing method that illustrates according to one example of the present invention embodiment.
[main element label declaration]
1000: host computer system 1100: computing machine
1102: microprocessor 1104: random access memory
1110: operating system 1120: application program
1106: input/output device 1108: system bus
1115: data transmission interface 1202: mouse
1204: keyboard 1206: display
1208: printer 1212: portable disk
1214: storage card 1216: solid state hard disc
1310: digital camera 1312:SD card
1314:MMC card 1316: memory stick
1318:CF card 1320: embedded storage device
100: memorizer memory devices 102: connector
104: Memory Controller 106: duplicative non-volatile memory module
108: intelligent card chip 1041: host system interface
1043: memory management circuitry 1045: memory interface
3002: bug check and correcting circuit 3004: memory buffer
3006: electric power management circuit 410 (0)～410 (N): the physics unit of erasing
502: data field 504: idle district
506: system region 508: replace district
610 (0)～610 (L): the logic unit 600 of erasing: cut section
602: Master boot sector 604: file configuration table district
606: root directory area 608: file area
A, T, D, D
1, D
m, I
1, I
m, P, S, L, F: field
SD
1, SD
2, SD
3, SD
4: subdata P
1, P
2, P
3, P
4: data directory mark
OSX
1, OSX
2: auxiliary data X
1, X
2: malicious data
S1010～S1060: each step of the data processing method described in one embodiment of the invention
Embodiment
Generally speaking, memorizer memory devices (also claiming memory storage system) comprises duplicative non-volatile memory module and controller (also claiming control circuit).Conventionally memorizer memory devices is to use together with host computer system, so that host computer system can write to data memorizer memory devices or reading out data from memorizer memory devices.
Figure 1A is the schematic diagram of the host computer system of the use memorizer memory devices that one exemplary embodiment illustrates according to the present invention.
In exemplary embodiment of the present invention, memorizer memory devices 100 is to be electrically connected by data transmission interface 1115 and other element of host computer system 1000.By the running of microprocessor 1102, random access memory 1104 and input/output device 1106, host computer system 1000 can write to data memorizer memory devices 100, or from memorizer memory devices 100 reading out data.For example, memorizer memory devices 100 can be storage card 1214, portable disk 1212 or solid state hard disc (SolidState Drive, SSD) 1216 as shown in Figure 1B.
Generally speaking, host computer system 1000 be can storage data any system.Although host computer system 1000 is to explain with computer system in this exemplary embodiment, but, in another exemplary embodiment of the present invention, host computer system 1000 can also be the systems such as mobile phone, digital camera, video camera, communication device, audio player or video player.For example, in the time that host computer system is digital camera 1310, memorizer memory devices is its secure digital using (Secure Digital, SD) card 1312, multimedia storage (Multimedia Card, MMC) card 1314, memory stick (Memory Stick) 1316, compact flash (Compact Flash, CF) card 1318 or embedded storage device 1320 (as shown in Figure 1 C).Embedded storage device 1320 comprises embedded multi-media card (Embedded MMC, eMMC).It is worth mentioning that, embedded multi-media card is to be directly electrically connected on the substrate of host computer system.
Fig. 2 is the calcspar that illustrates the memorizer memory devices 100 shown in Figure 1A.Please refer to Fig. 2, memorizer memory devices 100 comprises connector 102, Memory Controller 104, duplicative non-volatile memory module 106 and intelligent card chip 108.
Duplicative non-volatile memory module 106 is electrically connected to Memory Controller 104.Duplicative non-volatile memory module 106 is multi-level cell memory (Multi Level Cell, MLC) nand flash memory module, but the invention is not restricted to this, duplicative non-volatile memory module 106 can be also single-order storage unit (Single Level Cell, SLC) nand flash memory module, other flash memory module or any memory module with identical characteristics.Furthermore, duplicative non-volatile memory module 106 comprises multiple physics unit of erasing, and each physics is erased, unit has multiple physics programming units.Belonging to the erase physics programming unit of unit of same physics can be write independently and side by side be erased.That is to say, the physics unit of erasing is the least unit of erasing.That is, each physics storage unit of being erased in the lump that unit contains minimal amount of erasing.Physics programming unit is the minimum unit of programming.The minimum unit that, physics programming unit is data writing.In this exemplary embodiment, the physics unit of erasing is physical blocks, and physics programming unit is physical page, but the present invention is not as limit.
Fig. 3 is the summary calcspar of the Memory Controller that one exemplary embodiment illustrates according to the present invention.Please refer to Fig. 3, Memory Controller 104 comprises host system interface 1041, memory management circuitry 1043, and memory interface 1045.
In an exemplary embodiment, the steering order of memory management circuitry 1043 is to carry out implementation with firmware pattern.For example, memory management circuitry 1043 has microprocessor unit (not illustrating) and ROM (read-only memory) (not illustrating), and above-mentioned steering order by burning in ROM (read-only memory).In the time that memorizer memory devices 100 operates, above-mentioned steering order can have been carried out by microprocessor unit the data processing method of this exemplary embodiment.
In another exemplary embodiment of the present invention, the steering order of memory management circuitry 1043 can also procedure code pattern for example be stored in, in the specific region (, being exclusively used in the system region of storage system data in duplicative non-volatile memory module 106) of duplicative non-volatile memory module 106.In addition, memory management circuitry 1043 has microprocessor unit (not illustrating), ROM (read-only memory) (not illustrating) and random access memory (not illustrating).Wherein, ROM (read-only memory) has the code of driving section, and in the time that Memory Controller 104 is enabled, microprocessor unit can first be carried out this and drive code section that the steering order being stored in duplicative non-volatile memory module 106 is loaded in the random access memory of memory management circuitry 1043.Afterwards, microprocessor unit can turn round above-mentioned steering order to carry out the data processing method of this exemplary embodiment.
In addition,, in another exemplary embodiment of the present invention, the steering order of memory management circuitry 1043 can also a hardware pattern be carried out implementation.For instance, memory management circuitry 1043 comprises microcontroller, Memory Management Unit, storer writing unit, storer reading unit, storer erase unit and data processing unit.Erase unit and data processing unit of Memory Management Unit, storer writing unit, storer reading unit, storer is to be electrically connected to microcontroller.Wherein, Memory Management Unit is in order to manage physics in duplicative non-volatile memory module 106 unit of erasing.Storer writing unit writes instruction so that data are write in duplicative non-volatile memory module 106 in order to duplicative non-volatile memory module 106 is assigned.Storer reading unit is in order to assign reading command with reading out data from duplicative non-volatile memory module 106 to duplicative non-volatile memory module 106.Storer is erased unit in order to duplicative non-volatile memory module 106 is assigned to the instruction of erasing so that data are erased from duplicative non-volatile memory module 106.And data processing unit is wanted the data that write to the data of duplicative non-volatile memory module 106 and read from duplicative non-volatile memory module 106 in order to processing.
In another example of the present invention embodiment, Memory Controller 104 also comprises bug check and correcting circuit 3002.Bug check and correcting circuit 3002 are electrically connected to memory management circuitry 1043, in order to execution error inspection and correction program to guarantee the correctness of data.Particularly, when memory management circuitry 1043 receive from host computer system 1000 write instruction time, bug check can produce corresponding bug check and correcting code (ErrorChecking and Correcting Code for the corresponding data that this writes instruction with correcting circuit 3002, ECC Code), and memory management circuitry 1043 can write to duplicative non-volatile memory module 106 with corresponding bug check and correcting code by corresponding these data that write instruction.Afterwards when memory management circuitry 1043 is from duplicative non-volatile memory module 106 when reading out data, can read bug check corresponding to these data and correcting code simultaneously, and whether bug check and correcting circuit 3002 can, according to this bug check and correcting code to read data execution error inspection and correction program, there is error bit to identify these data.
In another example of the present invention embodiment, Memory Controller 104 also comprises memory buffer 3004.Memory buffer 3004 can be static RAM (Static Random AccessMemory, or dynamic RAM (Dynamic Random Access Memory SRAM), DRAM) etc., the present invention is not limited.Memory buffer 3004 is electrically connected to memory management circuitry 1043, in order to temporary instruction and the data that come from host computer system 1000, or the temporary data that come from duplicative non-volatile memory module 106.
In the another exemplary embodiment of the present invention, Memory Controller 104 also comprises electric power management circuit 3006.Electric power management circuit 3006 is electrically connected to memory management circuitry 1043, in order to the power supply of control store storage device 100.
Fig. 4, the 5th, the schematic diagram of the management duplicative non-volatile memory module 106 illustrating according to one example of the present invention embodiment.
In the time that the following physics of describing duplicative non-volatile memory module 106 is erased the running of unit, coming the operating physical unit of erasing with words such as " extraction ", " exchange ", " grouping ", " rotating " is concept in logic.That is to say, the erase physical location of unit of the physics of duplicative non-volatile memory module 106 is not changed, but in logic the physics of duplicative non-volatile memory module 106 unit of erasing is carried out to aforesaid operations.
Please refer to Fig. 4, the duplicative non-volatile memory module 106 of this exemplary embodiment comprises the physics unit 410 (0)～410 (N) of erasing.Memory management circuitry in Memory Controller 104 1043 unit 410 (0)～410 (N) of physics can being erased is logically grouped into data field 502, idle district 504, system region 506 and replaces district 508.Wherein, F, S, R and N that Fig. 4 indicates are positive integer, the physics that represents the configuration of the each district element number of erasing, and it can be set according to the capacity of the duplicative non-volatile memory module 106 that use by the manufacturer of memorizer memory devices 100.
Belonging in logic data field 502 and the physics in idle district 504 unit of erasing is the data that come from host computer system 1000 in order to store.For instance, the physics of data field 502 unit of erasing is to be regarded as the physics of the storage data unit of erasing, and the physics in idle district 504 unit of erasing is the physics that the writes new data unit of erasing.In other words, the physics in idle district 504 is erased unit for empty or the spendable physics unit (no record data or be labeled as invalid data useless) of erasing.When receive the data that write instruction and want to write from host computer system 1000, memory management circuitry 1043 can be from idle district 504 the extracts physical unit of erasing, and data are write to extracted physics and erase in unit, with the physics in replacement data district 502 unit of erasing.Or when needs are erased unit executing data consolidation procedure to a logic, memory management circuitry 1043 can be from erase unit data are write wherein of idle district 504 extracts physical, to replace this logic of the original mapping physics of unit unit of erasing of erasing.
The physics that belongs in logic system region 506 unit of erasing is in order to register system data.For instance, system data comprises about the physics of the manufacturer of duplicative non-volatile memory module 106 and model, duplicative non-volatile memory module 106 unit number, each physics physics programming unit number of unit etc. of erasing of erasing.
Belonging in logic the physics that replaces district 508 unit of erasing is while erasing unit damage in order to the physics in data field 502, idle district 504 or system region 506, the replacing damaged physics unit of erasing.Particularly, during memorizer memory devices 100 runnings, still have the erase physics of unit and data field 502 of normal physics in district 508 and erase unit while damaging if replace, memory management circuitry 1043 can be extracted the normal physics unit of erasing and change the physics damaging in data field 502 unit of erasing from replace district 508.If replace in district 508 without erase unit and when physics occurs erasing unit damage of normal physics; memory management circuitry 1043 can be declared as write protection (writeprotect) state by whole memorizer memory devices 100, and data writing again.
Also therefore,, in the operation of memorizer memory devices 100, data field 502, idle district 504, system region 506 and the physics that replaces district 508 unit of erasing can dynamically change.For example, can belong to data field 502 or idle district 504 in order to the physics of the storage data of the rotating unit of erasing with changing.
Please refer to Fig. 5, in order to allow host computer system 1000 carry out access to duplicative non-volatile memory module 106, memory management circuitry 1043 (or Memory Controller 104) can the several logics of configuration be erased unit 610 (0)～610 (L) with the unit 410 (0)～410 (F-1) of erasing of the physics in mapping (enum) data district 502.Wherein, each logic unit of erasing comprises multiple programmings in logic unit, and the physics programming unit of can mapping physical erasing in unit 410 (0)～410 (F-1) in the programming in logic unit that logic is erased in unit 610 (0)～610 (L).
In detail, the configured logic unit 610 (0)～610 (L) of erasing is offered host computer system 1000 by memory management circuitry 1043 (or Memory Controller 104), and service logic address-physical address mapping table is to record logic the erase mapping relations of unit 410 (0)～410 (F-1) of unit 610 (0)～610 (L) and physics of erasing.Therefore, in the time that host computer system 1000 is wanted access one logical address, memory management circuitry 1043 (or Memory Controller 104) can be confirmed this logical address corresponding logic erase unit and programming in logic unit, then finds its physics programming unit shining upon to carry out access by logical address-physical address mapping table.
In this exemplary embodiment, the operating system 1110 of host computer system 1000 is used file system that the logic unit 610 (0)～610 (L) of erasing is formatted into a cut section (partition) 600 as shown in Figure 6, and wherein cut section 600 comprises Master boot sector 602, file configuration table district 604, root directory area 606 and file area 608.
The programming in logic unit that belongs to Master boot sector 602 be in order to storing memory storage device 100 can storage area system information.
The programming in logic unit that belongs to file configuration table district 604 is in order to store files allocation list.File configuration table is corresponding the gathering together of logical address of recording store files.For example, in file configuration table district, can store two file configuration table, one of them file configuration table is used by normal access, and another file configuration table is backup file allocation list.
The programming in logic unit that belongs to root directory area 606 is in order to store files description block (FileDescription Block, FDB), and it is in order to record the file that is stored at present in memorizer memory devices 100 and the attribute information of catalogue.Particularly, file description block can record to store the initial storage address (, initial gathering together) of these a little files.
The programming in logic unit that belongs to file area 608 can be divided into multiple gather together and in order to the content of store files practically.In detail, disc storage least unit is sector, the information content that each sector has comprised 512 bytes (byte).But in the time that unit stores, the efficiency of host computer system 1000 can be very poor with sector.In general, the operating system 1110 of host computer system 1000 can be used as with a sector unit of accessing file, but to gather together as a basic access unit.Each is gathered together is that framework is on 2 power multiples of sector.Suppose that 8 continuous sectors form one and gather together, this size of gathering together is just 4096 bytes.Base this, can read continuously and promote relative efficiency with 8 sectors during at access data in operating system 1110.
Please refer to back Fig. 2, in this exemplary embodiment, memorizer memory devices 100 also comprises intelligent card chip 108.Intelligent card chip 108 is to be electrically connected to Memory Controller 104 by interface 108a, and wherein interface 108a is the special interface in order to carry out communication with intelligent card chip 108.
Particularly, the security module of intelligent card chip 108 can be carried out a security mechanism to prevent from wanting to steal the attack that is stored in data stored in intelligent card chip 108.For example, this attack comprises that timing attack (timing attack), single electric power analysis are attacked (single-power-analysis attack) or difference electric power analysis is attacked (differential-power-analysis).In addition, the performed security mechanism of intelligent card chip 108 is to meet Federal Information Processing Standards (Federal Information Processing Standards, FIPS) tertiary gradient of 140-2 or more high-grade or meet EMV EL (American Express, JCB, MasterCard and Visa Evaluation Level) the tertiary gradient or more high-grade.That is to say, intelligent card chip 108 is by the certification more than fourth stage of FIPS 140-2 or by the certification more than fourth stage of EMV EL.At this, FIPS is that Federal Government is formulated the Open Standard using to the contractor of the government organs except all military establishment and government, and wherein FIPS 140-2 has formulated the grade about data security.In addition, EMV is international finance industry for smart card and point of sale (point-of-sale, the POS) terminating machine that can use chip card, and the specialty transaction of formulating such as the ATM (Automatic Teller Machine) that extensively arranges of banking institution and the standard criterion authenticating.This specification is the standard set to the relevant software and hardware of the geld system (Payment System) of cash card for chip credit card.In this exemplary embodiment, by the running of intelligent card chip 108, memorizer memory devices 100 can provide the service with authentication, for example, and micropayment service, ticket service etc.
It is worth mentioning that, intelligent card chip 108 is to receive by the connector 102 of memorizer memory devices 100 instruction and the data that come from host computer system 1000, or transmit data to host computer system 1000, but not directly by intelligent card interface (, interface 108a) and host computer system 1000 communications.Base this, in this exemplary embodiment, application program 1120 can be installed in host computer system 1000, and carry out move instruction data cell to intelligent card chip 108 with specific communication document, director data unit is for example instruction-Application Protocol Data Unit (Command-Application Protocol Data Unit, and receive the ResponseAPDU of intelligent card chip 108 C-APDU), for example response-Application Protocol Data Unit (Response-Application Protocol Data Unit, R-APDU).
Further, Memory Controller 104 can produce one or more communication documents at memorizer memory devices 100, and sends the information of the logical address in order to store these one or more communication documents to application program 1120.For example, in the time that application program 1120 is assigned the instruction that stores a communication document in memorizer memory devices 100, operating system 1110 can write this communication document by the logical address of part according to the file system of memorizer memory devices 100 (not illustrating).At this, in order to store this communication document logical address be called as specific logic address.Afterwards, by application program 1120, communication document being carried out to access for the operation meeting of intelligent card chip 108 completes.For example, application program 1120 can by communication document write that C-APDU is sent to memorizer memory devices 100 by instruction and by the reading command of communication document is read to R-APDU from memorizer memory devices 100.It is worth mentioning that, in other operating system, application program 1120 also can directly be carried out access to the specific logic address in order to store communication document, carries out the operation to intelligent card chip 108.
In this exemplary embodiment, host computer system 1000 and memorizer memory devices 100 prearrange one first rule each other, and carry out accordingly the write operation to intelligent card chip 108.The first rule comprises that preset function, initial parameter value selection mode and parameter value increase mode newly.Wherein, initial parameter value selection mode is about How to choose initial parameter value, for example, in the time that initial parameter value selection mode is the date, application program 1120 by the date using the same day as initial parameter value.The newly-increased mode of parameter value is about the increasing or decreasing rule between two parameter values in order to successively to produce two data index markers, for instance, suppose that the newly-increased mode of parameter value is 1 for increasing progressively and increase progressively amplitude, if be 1 in order to produce the initial parameter value of the first stroke data directory mark, be 2 in order to produce the parameter value of second data index marker.
When a raw data is write intelligent card chip 108 by application program 1120 wishs, application program 1120 is divided into multiple subdatas according to the capacity of minimum basic access unit by raw data, the for example size of a sector (512 byte), but the present invention is not as limit.And application program 1120 is according to the selected initial parameter value of initial parameter value selection mode, then by initial parameter value substitution preset function to obtain the first data directory mark.This first data directory mark can be attached to the first stroke subdata being marked off by raw data.Next, application program 1120, according to data directory mark and the order of all subdatas in raw data of the newly-increased mode of parameter value, the first stroke subdata, determines to be attached to individually the data directory mark of all the other subdatas.
The raw data of wanting to write due to application program 1120 must be sent to memorizer memory devices 100 via operating system 1110, but operating system 1110 is in order to accelerate overall access speed, can carry out optimization processing to the order of gathering together in accessing file district 608.Base this, operating system 1110 may be identical or be different from the order of these subdatas in raw data at the sequencing that carries out going after optimization processing the each subdata of access.That is to say, even if operating system 1110 is memorizer memory devices 100 to be sent and write instruction in response to the writing demand of application program 1120, but received data writing and the actual raw data of wanting to write of application program 1120 of memory management circuitry 1043 (or Memory Controller 104) may be different.
But in this exemplary embodiment, because application program 1120 has all been added individually the data directory mark that represents its order in raw data in every subdata, therefore memory management circuitry 1043 (or Memory Controller 104) is receiving after data writing, can be according to the first rule and the data directory mark of each subdata all subdatas of resequencing, make it restore to the order identical in raw data with it, and the above-mentioned subdata after rearrangement is sent to intelligent card chip 108.Specifically, memory management circuitry 1043 (or Memory Controller 104) determines according to initial parameter value selection mode the initial parameter value that application program 1120 is selected, then by initial parameter value substitution preset function to obtain a functional value, more just all subdatas can be rearranged for and meet its order in raw data according to the data directory mark of functional value, the newly-increased mode of parameter value and each subdata.
For instance, suppose that preset function is following formula (1):
F(X)=X
2 (1)
Wherein, X is parameter value.And suppose that memory management circuitry 1043 (or Memory Controller 104) determines that according to initial parameter value selection mode the selected initial parameter value of application program 1120 is 3, and the newly-increased mode of parameter value is 1 for increasing progressively and increase progressively amplitude.Be labeled as 9 if receive the data directory of a subdata Y, memory management circuitry 1043 (or Memory Controller 104) obtains after numerical value 3 after carrying out anti-square operation to 9 at corresponding (1), can judge that subdata Y is the first stroke subdata in raw data.And the parameter that can judge the data directory mark that produces second subdata based on the newly-increased mode of parameter value is 4, therefore if in received all subdatas, search corresponding data directory be labeled as 4 square (, 16) subdata, finds out second subdata in raw data.Just all subdatas order in raw data originally can be obtained by that analogy, subdata can be rearranged accordingly.
In other exemplary embodiment, preset function can be following formula (2):
F(X)=X
3 (2)
Wherein, X is parameter value, but should be noted that, formula (1) is only the example of enumerating in order to illustrate with formula (2), and the present invention is not as limit.
Fig. 7 is the schematic diagram that writes instruction that the operating system 1110 that illustrates according to one example of the present invention embodiment is assigned.Refer to Fig. 7, the logical address that field A wants to write in order to record.Field T, in order to record a special marking, represents that this data writing is to write to intelligent card chip 108.The data content that field D wants to write in order to record, wherein, D
1to D
mrespectively in order to record the content of each subdata, and I
1to I
mrespectively in order to record the content of corresponding data directory mark, and m is positive integer.Field P is in order to record the information of the testing mechanism relevant to avoiding write error.
Below will illustrate in the time that application program 1120 is wanted to write raw data with Fig. 8 A to Fig. 8 D, how host computer system 1000 correctly completes the write operation to intelligent card chip 108 according to the first rule with memorizer memory devices 100.
Refer to Fig. 8 A, suppose that application program 1120 is sequentially divided into subdata SD according to the capacity of the basic access unit of host computer system 1000 by raw data
1to SD
4.For the first stroke subdata SD
1, application program 1120 is selected initial parameter value according to initial parameter value selection mode, and initial parameter value substitution preset function is attached to the first stroke subdata SD to obtain
1data directory mark P
1.Suppose that initial parameter value is that numerical value 1 and preset function are above-mentioned formula (1), data directory mark P
1for numerical value 1.For its excess-three subdata SD
2to SD
4, the first stroke subdata SD that application program 1120 according to the newly-increased mode of parameter value, had previously produced
1data directory mark P
1produce three data index marker P
2to P
4.Continue above-mentioned example, if the newly-increased mode of parameter value is 1 for increasing progressively and increase progressively amplitude, so in order to produce subdata SD
2to SD
4data directory mark P
2to P
4three parameter values be respectively numerical value 2,3,4.Above-mentioned parameter value substitution formula (1) just can be attached to respectively to subdata SD
2to SD
4data directory mark P
2to P
4be numerical value 4,9,16.But it must be emphasized that, the newly-increased mode of above-mentioned preset function, initial parameter value selection mode and parameter value is only the example of enumerating in order to illustrate, the present invention is not as limit.
In this exemplary embodiment, operating system 1110 promotes overall access speed not according to subdata SD for asking
1to SD
4order in raw data is carried out access, and in the process of inquiry file system, needs some auxiliary data of extra access, and as shown in Figure 8 B, the order of supposing operating system 1110 actual accesses is subdata SD
4, auxiliary data OSX
1, auxiliary data OSX
2, subdata SD
1, subdata SD
2, and subdata SD
3, what memory management circuitry 1043 (or Memory Controller 104) was received so write, and data writing corresponding to instruction can comprise subdata and the auxiliary data so that order occurs shown in Fig. 8 B.
Memory management circuitry 1043 (or Memory Controller 104) receives that write after instruction can't directly the order in Fig. 8 B be sent to intelligent card chip 108 according to each subdata, and can determine data directory mark (, the data directory mark P that application program 1120 can be attached to the first stroke subdata in this write operation according to the first rule
1), and to find out accordingly whichever be the first stroke subdata (, subdata SD
1).And, memory management circuitry 1043 (or Memory Controller 104) data-driven index marker P
1determine and can be attached to subdata SD with the newly-increased mode of parameter value
2to SD
4data directory mark P
2to P
4, and as long as can interpretation data index marker P according to the newly-increased mode of parameter value
1to P
4order, just can be accordingly by subdata SD
1to SD
4order be rearranged for and meet its order in raw data.In addition, because memory management circuitry 1043 (or Memory Controller 104) is receiving the instruction that writes that operating system 1110 sends, and after field T identifies special marking, system first supposes that all data in field D are all to write intelligent card chip 108, watches out auxiliary data OSX but work as memory management circuitry 1043 (or Memory Controller 104)
1, OSX
2, by additional any data directory mark, can not judge auxiliary data OSX
1, OSX
2do not belong to the raw data that application program 1120 is wanted to write.Base this, memory management circuitry 1043 (or Memory Controller 104) is being got rid of auxiliary data OSX
1, OSX
2and rearrange subdata SD
1to SD
4after, data content as shown in Figure 8 C can be sent to intelligent card chip 108.
In another exemplary embodiment, as shown in Fig. 8 D, suppose that operating system 1110 do not change the order of the each subdata of access, but host computer system 1000 exists malicious application to make operating system 1110 between subdata SD2 and SD3, also will write two malicious data X writing
1, X
2.Due to malicious data X
1, X
2also lack the additional data directory mark of application program 1120, therefore memory management circuitry 1043 (or Memory Controller 104), also can be by malicious data X in the time preparing to be sent to the data of intelligent card chip 108
1, X
2reject, so can avoid the write operation of intelligent card chip 108 to be subject to rogue program interference.
In another example of the present invention embodiment, between host computer system 1000 and memorizer memory devices 100 except there is above-mentioned the first rule, also have the good Second Rule of prearrange each other, can further reduce and intelligent card chip 108 is carried out to write operation according to the first rule with Second Rule the probability of being disturbed by rogue program.
In detail, the all communication documents that are recorded in file area 608 are the communication interfaces between host computer system 1000 and intelligent card chip 108, in the time that application program 1120 need to write intelligent card chip 108 by data, must transmit data by a certain communication document of choice for use, and Second Rule is the communication document of selecting this less important use about how from be recorded in all communication documents of file area 608.In this exemplary embodiment, application program 1120 can be attached to corresponding selected communication document file identification mark wherein in the middle of a subdata.For instance, application program 1120 is that file identification mark is attached in finishing touch subdata.
After memory management circuitry 1043 (or Memory Controller 104) receives and writes instruction, first from all communication documents, determine application program 1120 selected communication document (hereinafter referred to as target communication document) in this data write operation according to Second Rule, then check in the included all subdatas of data writing, whether having its additional file identification mark of a subdata is corresponding to target communication document.If so, memory management circuitry 1043 (or Memory Controller 104) is just according to the data directory mark duplicate removal new sort subdata of the first rule and each subdata.
That is to say, have only and meet the Second Rule that host computer system 1000 and memorizer memory devices 100 have been reached an agreement in advance when the selected communication document of this less important data writing, memory management circuitry 1043 (or Memory Controller 104) is just carried out the restructuring of subdata, and then the subdata arranging is sent to intelligent card chip 108.Thus, even if malicious application is sent the malicious data of interference or wish are upset subdata order by random access communication document during application program 1120 is wanted data writing, lack the information of Second Rule because of malicious application, therefore select the probability of the communication document identical with application program 1120 not high, this can reduce the probability of disturbing generation base.Application program 1120 while once needing data to write intelligent card chip 108, can be selected another communication document upper according to Second Rule.Memory management circuitry 1043 (or Memory Controller 104) confirms that according to aforementioned manner whether the data writing receiving is sent by application program 1120, reduces the disturbing effect that malicious application causes accordingly.
Fig. 9 A assigns the schematic diagram that writes instruction to intelligent card chip 108 by memory management circuitry 1043 (or Memory Controller 104).Refer to Fig. 9 A, field T is in order to record special marking.Field L records the length of the data of wanting to write.Field S records as the information relevant to data security such as data directory mark, preset function of the first stroke subdata.The content (, the subdata after rearrangement) of the data that field D wants to write in order to record.Field F is in order to the file identification mark of records application program 1120 selected communication document in this data write operation.
Memory management circuitry 1043 (or Memory Controller 104) utilize as Fig. 9 A write instruction by resequence after subdata be sent to intelligent card chip 108 after, according to the running result of intelligent card chip 108 and by the communication document of determining according to Second Rule, response message is sent to host computer system 1000, as shown in Figure 9 B, wherein field T is in order to record special marking for response message.Field L records the length of previous write data.Field D produces the content of response message according to the content of the data that previously write in order to recording smart card chip 108.Field F is in order to the file identification mark of records application program 1120 selected communication document in this data write operation.
Figure 10 is the process flow diagram of the data processing method that illustrates according to one example of the present invention embodiment.
Refer to Figure 10, in step S1010, memory management circuitry 1043 (or Memory Controller 104) receives the instruction that writes from host computer system 1000, this writes the corresponding data writing of instruction and comprises multiple subdatas, and each subdata be installed in 1120 of the application programs of host computer system 1000 Fu Jia a data directory mark.Above-mentioned data writing is the raw data that memorizer memory devices 100 is delivered in corresponding application program 1120 tendencies to develop, and memorizer memory devices 100 has the first rule with application program 1120 prearranges, the first rule comprises that preset function, initial parameter value selection mode and parameter value increase mode newly.Application program 1120 is according to the selected initial parameter value of initial parameter value selection mode, and initial parameter value substitution preset function is attached to the data directory mark of the first stroke subdata in raw data to obtain, and according to data directory mark and the order of above-mentioned subdata in raw data of the newly-increased mode of parameter value, the first stroke subdata, decision is attached to individually the data directory mark of all the other subdatas.
Then in step S1020, memory management circuitry 1043 (or Memory Controller 104) is according to the Second Rule good with host computer system 1000 prearranges, from be recorded in all communication documents of file area 608, determines the selected communication document of application program 1120.
As shown in step S1030, the file identification that memory management circuitry 1043 (or Memory Controller 104) judgement is additional to data writing marks whether the corresponding communication document of determining.
If not, finish the flow process of the data processing method that this exemplary embodiment illustrates.If so, as shown in step S1040, memory management circuitry 1043 (or Memory Controller 104) according to good the first rule of host computer system 1000 prearranges and the data directory mark of each subdata, all subdatas of resequencing.
In step S1050, the subdata after rearrangement is sent to intelligent card chip 108 by memory management circuitry 1043 (or Memory Controller 104).
Finally, as shown in step S1060, memory management circuitry 1043 (or Memory Controller 104) is sent to host computer system 1000 by the communication document of determining according to Second Rule by response message.
In sum, data processing method of the present invention, Memory Controller and memorizer memory devices can guarantee intelligent card chip to carry out the correctness of write operation, and can reduce malicious application and make during write operation the probability of interference.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claim scope person of defining.
Claims (18)
1. a data processing method, for thering is a memorizer memory devices of a duplicative non-volatile memory module and an intelligent card chip, wherein this duplicative non-volatile memory module has multiple physics unit of erasing, and each the plurality of physics unit of erasing has multiple physics programming units, and the method comprises:
Receive one from a host computer system and write instruction, this writes the corresponding data writing of instruction and comprises multiple subdatas, and each the plurality of subdata is installed in the individually additional data directory mark of an application program of this host computer system, wherein this data writing is the raw data to should application program tendency to develop delivering to this memorizer memory devices, and this memorizer memory devices and this application program prearrange have one first rule, this first rule comprises a preset function, one initial parameter value selection mode and a parameter value increase mode newly, and this application program is according to the selected initial parameter value of this initial parameter value selection mode, and this this preset function of initial parameter value substitution is attached to this data directory mark of the first stroke subdata in this raw data to obtain, and according to the newly-increased mode of this parameter value, this data directory mark of this first stroke subdata and the order of the plurality of subdata in this raw data, determine to be attached to individually this data directory mark of all the other subdatas in the plurality of subdata,
According to this first rule and this data directory mark of each the plurality of subdata of this application program prearrange, the plurality of subdata of resequencing; And
The plurality of subdata after rearrangement is sent to this intelligent card chip.
2. data processing method according to claim 1, wherein this host computer system is provided with an operating system, and this application program is, by this operating system, this raw data is sent to this memorizer memory devices, this application program is divided into the plurality of subdata according to the capacity of a basic access unit by this raw data, and the order of the plurality of subdata in this data writing is identical or be different from the order of the plurality of subdata in this raw data.
3. data processing method according to claim 1, wherein basis and this first rule of this application program prearrange and this data directory mark of each the plurality of subdata, the step of the plurality of subdata of resequencing comprises:
Determine according to this initial parameter value selection mode this initial parameter value that this application program is selected;
By this this preset function of initial parameter value substitution to obtain a functional value; And
According to this data directory mark of this functional value, the newly-increased mode of this parameter value and each the plurality of subdata, the plurality of subdata is rearranged for this raw data and is conformed to.
4. data processing method according to claim 1, the plurality of physics that wherein this duplicative non-volatile memory module has a mapping part multiple logics of unit unit of erasing of erasing, the plurality of logic unit of erasing is at least formatted into a file configuration table district, one root directory area and a file area, and this file area stores multiple communication documents, this application program according to a Second Rule of this memorizer memory devices prearrange, select the plurality of communication document one of them, and by a corresponding selected communication document file identification mark be additional to the plurality of subdata one of them.
5. data processing method according to claim 4, wherein, after receiving this step that writes instruction from this host computer system, also comprises:
From the plurality of communication document, determine the selected communication document of this application program according to this Second Rule; And
In the time being additional to the communication document that this file identification marking correspondence of this data writing determines, just carry out basis and this first rule of this host computer system prearrange and this data directory mark of each the plurality of subdata, the step of the plurality of subdata of resequencing.
6. data processing method according to claim 5, wherein, after the plurality of subdata after rearrangement is sent to the step of this intelligent card chip, also comprises:
Transmit a response message to this host computer system by the communication document of determining according to this Second Rule, wherein this response message comprises this file identification marking that determined communication document is corresponding.
7. a Memory Controller, for having a memorizer memory devices of a duplicative non-volatile memory module and an intelligent card chip, this Memory Controller comprises:
One host interface, in order to be electrically connected to a host computer system;
One memory interface, in order to be electrically connected to this duplicative non-volatile memory module, wherein this duplicative non-volatile memory module has multiple physics unit of erasing, and each the plurality of physics unit of erasing has multiple physics programming units; And
One memory management circuitry, be electrically connected this host interface and this memory interface, this memory management circuitry writes instruction in order to receive one from this host computer system, wherein this writes the corresponding data writing of instruction and comprises multiple subdatas, and each the plurality of subdata is installed in the individually additional data directory mark of an application program of this host computer system, wherein this data writing is the raw data to should application program tendency to develop delivering to this memorizer memory devices, and this memorizer memory devices and this application program prearrange have one first rule, this first rule comprises a preset function, one initial parameter value selection mode and a parameter value increase mode newly, and this application program is according to the selected initial parameter value of this initial parameter value selection mode, and this this preset function of initial parameter value substitution is attached to this data directory mark of the first stroke subdata in this raw data to obtain, and according to the newly-increased mode of this parameter value, this data directory mark of this first stroke subdata and the order of the plurality of subdata in this raw data, determine to be attached to individually this data directory mark of all the other subdatas in the plurality of subdata,
This memory management circuitry also in order to according to and this first rule and this data directory mark of each the plurality of subdata of this application program prearrange, the plurality of subdata of resequencing,
This memory management circuitry is also in order to be sent to this intelligent card chip by the plurality of subdata after rearrangement.
8. Memory Controller according to claim 7, wherein this host computer system is provided with an operating system, and this application program is, by this operating system, this raw data is sent to this memorizer memory devices, this application program is divided into the plurality of subdata according to the capacity of a basic access unit by this raw data, and the order of the plurality of subdata in this data writing is identical or be different from the order of the plurality of subdata in this raw data.
9. Memory Controller according to claim 7, wherein this memory management circuitry is at basis and this first rule of this application program prearrange and this data directory mark of each the plurality of subdata, while resequencing the plurality of subdata, to determine according to this initial parameter value selection mode this initial parameter value that this application program is selected, by this this preset function of initial parameter value substitution to obtain a functional value, and according to this functional value, this data directory mark of the newly-increased mode of this parameter value and each the plurality of subdata, the plurality of subdata is rearranged for this raw data and is conformed to.
10. Memory Controller according to claim 7, wherein this memory management circuitry configures multiple logics and erases unit with the plurality of physics of the mapping part unit of erasing, and the plurality of logic unit of erasing is at least formatted into a file configuration table district, a root directory area and a file area by this memory management circuitry, and store multiple communication documents to this file area
This application program according to a Second Rule of this memorizer memory devices prearrange, select the plurality of communication document one of them, and by a corresponding selected communication document file identification mark be additional to the plurality of subdata one of them.
11. Memory Controllers according to claim 10, wherein this memory management circuitry is also in order to receive from this host computer system after this writes instruction, from the plurality of communication document, determine the selected communication document of this application program according to this Second Rule, and in the time being additional to the communication document that this file identification marking correspondence of this data writing determines, just basis and this first rule of this host computer system prearrange and this data directory mark of each the plurality of subdata, the plurality of subdata of resequencing.
12. Memory Controllers according to claim 11, wherein this memory management circuitry is after being sent to this intelligent card chip by the plurality of subdata after rearrangement, also, in order to transmit a response message to this host computer system by the communication document of determining according to this Second Rule, wherein this response message comprises this file identification marking that determined communication document is corresponding.
13. 1 kinds of memorizer memory devices, comprising:
A connector, in order to be electrically connected to a host computer system;
One duplicative non-volatile memory module, has multiple physics unit of erasing, and each the plurality of physics unit of erasing has multiple physics programming units;
One intelligent card chip; And
One Memory Controller, is electrically connected to this connector, this duplicative non-volatile memory module and this intelligent card chip,
This Memory Controller writes instruction in order to receive one from this host computer system, wherein this writes the corresponding data writing of instruction and comprises multiple subdatas, and each the plurality of subdata is installed in the individually additional data directory mark of an application program of this host computer system, wherein this data writing is the raw data to should application program tendency to develop delivering to this memorizer memory devices, and this memorizer memory devices and this application program prearrange have one first rule, this first rule comprises a preset function, one initial parameter value selection mode and a parameter value increase mode newly, and this application program is according to the selected initial parameter value of this initial parameter value selection mode, and this this preset function of initial parameter value substitution is attached to this data directory mark of the first stroke subdata in this raw data to obtain, and according to the newly-increased mode of this parameter value, this data directory mark of this first stroke subdata and the order of the plurality of subdata in this raw data, determine to be attached to individually this data directory mark of all the other subdatas in the plurality of subdata,
This Memory Controller also in order to according to and this first rule and this data directory mark of each the plurality of subdata of this application program prearrange, the plurality of subdata of resequencing,
This Memory Controller is also in order to be sent to this intelligent card chip by the plurality of subdata after rearrangement.
14. memorizer memory devices according to claim 13, wherein this host computer system is provided with an operating system, and this application program is, by this operating system, this raw data is sent to this memorizer memory devices, this application program is divided into the plurality of subdata according to the capacity of a basic access unit by this raw data, and the order of the plurality of subdata in this data writing is identical or be different from the order of the plurality of subdata in this raw data.
15. memorizer memory devices according to claim 13, wherein this Memory Controller is at basis and this first rule of this application program prearrange and this data directory mark of each the plurality of subdata, while resequencing the plurality of subdata, to determine according to this initial parameter value selection mode this initial parameter value that this application program is selected, by this this preset function of initial parameter value substitution to obtain a functional value, and according to this functional value, this data directory mark of the newly-increased mode of this parameter value and each the plurality of subdata, the plurality of subdata is rearranged for this raw data and is conformed to.
16. memorizer memory devices according to claim 13, wherein this Memory Controller configures multiple logics and erases unit with the plurality of physics of the mapping part unit of erasing, and the plurality of logic unit of erasing is at least formatted into a file configuration table district, a root directory area and a file area by this Memory Controller, and store multiple communication documents to this file area
This application program according to a Second Rule of this memorizer memory devices prearrange, select the plurality of communication document one of them, and by a corresponding selected communication document file identification mark be additional to the plurality of subdata one of them.
17. memorizer memory devices according to claim 16, wherein this Memory Controller is also in order to receive from this host computer system after this writes instruction, from the plurality of communication document, determine the selected communication document of this application program according to this Second Rule, and in the time being additional to the communication document that this file identification marking correspondence of this data writing determines, just basis and this first rule of this host computer system prearrange and this data directory mark of each the plurality of subdata, the plurality of subdata of resequencing.
18. memorizer memory devices according to claim 17, wherein this Memory Controller is after being sent to this intelligent card chip by the plurality of subdata after rearrangement, also, in order to transmit a response message to this host computer system by the communication document of determining according to this Second Rule, wherein this response message comprises this file identification marking that determined communication document is corresponding.
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