CN103617138A - Multi-mainframe arbitration method and multi-mainframe communication system - Google Patents
Multi-mainframe arbitration method and multi-mainframe communication system Download PDFInfo
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Abstract
The invention discloses a multi-mainframe arbitration method and a multi-mainframe communication system. The method comprises the following steps that a mainframe detects whether a handshaking signal line is at a high electrical level when needing to seize a data line; if the handshaking signal line is at a low electrical level, the mainframe waits; if the handshaking signal line is at the high electrical level, the handshaking signal line is set at the low electrical level by the mainframe through the handshaking signal end, and then the mainframe starts to detect whether the data line has starting signals of data transition; if the starting signals are detected within a corresponding time slice, the mainframe does not compete for seizing the data line, and if the starting signals are not detected within the corresponding time slice, the mainframe seizes the data line. According to the multi-mainframe arbitration method and the multi-mainframe communication system, mainframes which do not have I2C buses can achieve the I2C bus function, and the mainframes achieving higher priority seize the I2C buses preferentially.
Description
[technical field]
The present invention relates to the communications field, relate in particular to many main frames referee method and multi-host communication system.
[background technology]
I2C(Inter-Integrated Circuit) two wire bus that bus is developed by PHLIPS company, by serial data line SDA and serial time clock line SCL, formed, main frame can carry out the transmitting-receiving of data with the device with I2C interface by I2C by I2C bus, transfer rate can reach 100kbps under mode standard, under quick mode, can reach 400kbps, I2C can prevent that data are destroyed by the mode of collision detection and data arbitration, real many host buses, it allows a plurality of main frames to communicate, the arbitration of I2C bus comprises SCL(serial time clock line) synchronous and SDA(serial data line) arbitration:
1 is synchronous
The clock that All hosts produces oneself on scl line transmits the message in I2C bus, and data are only effective in the high level period of clock.All hosts shows on scl line be a line and logic, therefore, scl line is kept low level by the device of long low-level period, now, the short device of low-level period enters high level waiting status, the low-level period of the synchronous SCL clock producing is determined by the longest device of low level clock period, and high level period is determined by the shortest device of high level clock period.
1 arbitration
The arbitration of sda line is to be also based upon in the principle that bus has wired AND logic function.Node is after sending 1 bit data, and whether the data that relatively present in bus send with oneself consistent.To continue to send; Otherwise, exit competition.Like this, when other main frames send low level, the main frame of the high level of transmission will disconnect its data output, and arbitration can continue multidigit comparison.
And in Embedded Application, a lot of main frames are generally MCU, and therefore a lot of MCU without I2C bus interface between many main frames, main frame and slave, can not realize reliable communication.
[summary of the invention]
In order to overcome the deficiencies in the prior art, the invention provides a kind of many main frames referee method, thereby make the common main frame without I2C bus, can Simulation with I 2C bus, realize the arbitration of fast and reliable.The present invention also provides a kind of multi-host communication system, makes the communication system can Simulation with I 2C bus, realizes the arbitration of fast and reliable, thereby completes communication.
Many main frames referee method, the data line interface of each main frame is connected with data line respectively, and the handshake end of each main frame is connected with handshake line respectively; The timeslice of different durations is assigned to each main frame;
Described many main frames referee method comprises the steps:
When if main frame need to take data line, whether handshake line is in high level described in Host Detection;
If described handshake line is in low level, described main frame is waited for;
If described handshake line is in high level, described main frame is placed in low level by handshake end by described handshake line, and starts immediately to detect the enabling signal whether described data line exists data transmission;
If enabling signal detected in corresponding timeslice, described main frame exits the competition that takies described data line,
If can't detect enabling signal in corresponding timeslice, described main frame takies described data line.
In one embodiment, when described main frame takies and use described data line, described main frame is placed in high level by described handshake line.
In one embodiment, according to the priority level of each main frame, distribute the timeslice of different durations, the shorter timeslice of host assignment that priority is lower, the longer timeslice of host assignment that priority is higher.
In one embodiment, described main frame detects the enabling signal whether described data line exists data transmission by the following method:
If described Host Detection of the previous moment is to described data line in high level, then a described data line of the moment is in low level, and described main frame judges that described data line exists enabling signal.
The present invention also provides a kind of multi-host communication system, comprise data line, handshake line, clock cable, a plurality of main frame and at least one slave, the data line interface of each main frame is connected with data line respectively, it is characterized in that: the handshake end of each main frame is connected with handshake line respectively, the clock signal terminal of each main frame is connected with described clock cable respectively; The serial data line of the I2C bus of described slave is connected with clock cable with described data line respectively with serial time clock line;
The timeslice of different durations is assigned to each main frame;
When if main frame need to take data line, described in Host Detection handshake line whether in high level,
If described handshake line is in low level, described main frame waits for,
If described handshake line is in high level, described main frame is placed in low level by handshake end by described handshake line, and starts immediately to detect the enabling signal whether described data line exists data transmission,
If enabling signal detected in corresponding timeslice, described main frame exits the competition that takies described data line,
If can't detect enabling signal in corresponding timeslice, described main frame takies described data line.
In one embodiment, when described main frame takies and use described data line, described main frame is placed in high level by described handshake line.
In one embodiment, according to the priority level of each main frame, distribute the timeslice of different durations, the shorter timeslice of host assignment that priority is lower, the longer timeslice of host assignment that priority is higher.
In one embodiment, described main frame detects the enabling signal whether described data line exists data transmission by the following method:
If described Host Detection of the previous moment is to described data line in high level, then a described data line of the moment is in low level, and described main frame judges that described data line exists enabling signal.
The invention has the beneficial effects as follows: by adopting technique scheme, make not have in a lot of embedded systems between the main frame of I2C bus and can realize I2C bus functionality, thereby the slave with I2C bus can be directly connected to data line and receive data; According to different priority, the timeslice of different length is distributed to different main frames, thereby the main frame of also having realized higher priority more preferably takies I2C bus.
[accompanying drawing explanation]
Fig. 1 is the system schematic of the multi-host communication system of an embodiment of the present invention;
Fig. 2 is the sequential chart of many main frames referee method of an embodiment of the present invention;
Fig. 3 is an embodiment of the present invention.
[embodiment]
Below with reference to accompanying drawing, specific embodiments of the invention are described in further detail.
As shown in Figure 1, a kind of multi-host communication system, comprise the first main frame, the second main frame, slave, data line SDA, handshake line busy and clock cable SCL, wherein, the first main frame and the second main frame all do not have I2C bus, for example adopt a 8 single-chip microcomputers of microcontroller (MCU) STC12C5A60S2 ，Qi Shi macrocrystalline company; And slave has I2C bus, for example, adopt the real-time clock of SD2405API ，Qi Shi Xing Weifan company, with the I2C interface of standard.
The data line interface SDA1 of the first main frame is connected with data line SDA respectively with the data line interface SDA2 of the second main frame, the handshake end busy1 of the first main frame and the handshake end busy2 of the second main frame are connected with handshake line busy respectively, and the clock signal terminal SCL1 of the first main frame is connected with clock cable SCL respectively with the clock signal terminal SCL2 of the second main frame; The serial data line SDA3 of the I2C bus of slave is connected with clock cable SCL with data line SDA respectively with serial time clock line SCL3; Handshake end busy1, data line interface SDA1 and the clock signal terminal SCL1 of the first main frame all adopt common I/O mouth, and handshake end busy2, the data line interface SDA2 of same the first main frame and clock signal terminal SCL2 are also common I/O mouths.For example, the P2^0 of the first main frame is as SCL1, and P2^1 is as SDA1, and P2^2, as busy2, is used the P2^0 of the second main frame as SCL2, and P2^1 is as SDA2, and P2^2 is as busy2.
Suppose that the priority of the first main frame is higher than the priority of the second main frame, therefore give the first host assignment timeslice t1, and give the second host assignment timeslice (t1+t2).For example t1 can be 20us, (t1+t2) is 40us.
When two main frames all do not take while maybe needing to take data line SDA, handshake line busy is in high level state (being that busy is in not busy state), and data line SDA is also in high level state, and clock cable is also in high level state; When data line SDA is taken by certain main frame, handshake line busy is in low level, i.e. busy condition.
If the first main frame need to take data line SDA (in I2C bus, when certain main frame takies data line SDA, also needing simultaneously to clock cable tranmitting data register signal), whether the first Host Detection handshake line busy is in high level:
If handshake line busy, in low level, illustrates that now data line SDA is being taken by the second main frame, therefore the first main frame continues to wait for that handshake line busy becomes not busy state;
If handshake line busy is in high level, illustrate that now data line SDA is not yet being taken by the second main frame, therefore now the first main frame is set to low level by handshake end busy1, because handshake end busy1 and handshake end busy2 are line and annexation, therefore, handshake line busy becomes low level, and now the first main frame starts to detect the enabling signal whether data line SDA exists data transmission immediately; When arriving the state of handshake line busy in high level at the first Host Detection, very possible the second main frame also is just wanting to take SDA, and handshake line busy detected in high level simultaneously, and the second main frame is also placed in low level by handshake end busy2 by handshake line busy simultaneously, and start immediately to detect the enabling signal whether data line SDA exists data transmission, therefore, the first main frame and the second main frame start the enabling signal whether data line SDA exists data transmission simultaneously.
Because the priority of the first main frame is higher, in corresponding timeslice t1, data line SDA all being detected is high level, the enabling signal of data transmission do not detected, therefore, in the moment finishing at timeslice t1, the first main frame takies data line SDA by data line interface SDA1 immediately, and enabling signal appears in data line SDA immediately, and because the priority of the second main frame is lower, after past timeslice t1 duration, it still continues whether to occur enabling signal at detection data line SDA, therefore, the second main frame will detect this enabling signal, in the timeslice t1 stage, data line SDA detected in high level, then SDA low level after the moment of timeslice t1, detected, therefore, the second main frame exits the competition that takies data line SDA, and handshake end busy2 is placed in to high level, but, because the handshake end busy1 of the first main frame is now also in low level, handshake line busy is still in low level, remaining main frame (if also having other main frames) detects handshake line busy after low level, still can be in waiting status.
After the first main frame sends enabling signal (the first main frame passes through clock signal terminal SCL1 to clock cable tranmitting data register signal simultaneously), the slave with I2C bus detects this enabling signal, starts to receive to send to the data data line SDA from the first main frame by data line interface SDA3.
After the first main frame takies I2C bus (data line SDA and clock cable SCL) and completes, putting SDA1 and SCL1 is high level, putting handshake end busy1 is high level, because the handshake end busy2 of the second main frame is now also high level, therefore handshake line change busy is high level, comes back to not busy state; Also clock cable SCL is retracted to high level simultaneously.
The quantity of main frame can be any number of, and it is identical with the connected mode of data line SDA, handshake line and clock cable and above-mentioned the first main frame.And that the slave with I2C bus also can have is a plurality of, it is also identical with above-mentioned slave with the connected mode of data line SDA and clock cable.
Claims (8)
1. the referee method of main frame more than, is characterized in that: the data line interface of each main frame is connected with data line respectively, and the handshake end of each main frame is connected with handshake line respectively; The timeslice of different durations is assigned to each main frame;
Described many main frames referee method comprises the steps:
When if main frame need to take data line, whether handshake line is in high level described in Host Detection;
If described handshake line is in low level, described main frame is waited for;
If described handshake line is in high level, described main frame is placed in low level by handshake end by described handshake line, and starts immediately to detect the enabling signal whether described data line exists data transmission;
If enabling signal detected in corresponding timeslice, described main frame exits the competition that takies described data line,
If can't detect enabling signal in corresponding timeslice, described main frame takies described data line.
2. many main frames referee method as claimed in claim 1, is characterized in that: when described main frame takies and use described data line, described main frame is placed in high level by described handshake line.
3. many main frames referee method as claimed in claim 1, is characterized in that: according to the priority level of each main frame, distribute the timeslice of different durations, the shorter timeslice of host assignment that priority is lower, the longer timeslice of host assignment that priority is higher.
4. many main frames referee method as claimed in claim 1, is characterized in that, described main frame detects the enabling signal whether described data line exists data transmission by the following method:
If described Host Detection of the previous moment is to described data line in high level, then a described data line of the moment is in low level, and described main frame judges that described data line exists enabling signal.
5. a multi-host communication system, comprise data line, handshake line, clock cable, a plurality of main frame and at least one slave, the data line interface of each main frame is connected with data line respectively, it is characterized in that: the handshake end of each main frame is connected with handshake line respectively, the clock signal terminal of each main frame is connected with described clock cable respectively; The serial data line of the I2C bus of described slave is connected with clock cable with described data line respectively with serial time clock line;
The timeslice of different durations is assigned to each main frame;
When if main frame need to take data line, described in Host Detection handshake line whether in high level,
If described handshake line is in low level, described main frame waits for,
If described handshake line is in high level, described main frame is placed in low level by handshake end by described handshake line, and starts immediately to detect the enabling signal whether described data line exists data transmission,
If enabling signal detected in corresponding timeslice, described main frame exits the competition that takies described data line,
If can't detect enabling signal in corresponding timeslice, described main frame takies described data line.
6. multi-host communication system as claimed in claim 5, is characterized in that: when described main frame takies and use described data line, described main frame is placed in high level by described handshake line.
7. multi-host communication system as claimed in claim 5, is characterized in that: according to the priority level of each main frame, distribute the timeslice of different durations, the shorter timeslice of host assignment that priority is lower, the longer timeslice of host assignment that priority is higher.
8. multi-host communication system as claimed in claim 5, is characterized in that, described main frame detects the enabling signal whether described data line exists data transmission by the following method:
If described Host Detection of the previous moment is to described data line in high level, then a described data line of the moment is in low level, and described main frame judges that described data line exists enabling signal.
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Cited By (13)
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| CN104408000A (en) * | 2014-12-05 | 2015-03-11 | 浪潮集团有限公司 | Method for preventing conflict in health information read of BIOS (Basic Input Output System) and BMC (Baseboard Management Controller) on Feiteng server |
| CN106953787A (en) * | 2017-03-28 | 2017-07-14 | 华南理工大学 | A kind of battery management system multi-host communication method and device based on electrical level transfer |
| CN108280041A (en) * | 2017-12-29 | 2018-07-13 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | A kind of communication means and device of internal integrated circuit host |
| CN108521854A (en) * | 2017-05-17 | 2018-09-11 | 深圳市大疆创新科技有限公司 | Communication control method, communication master device and communication system |
| CN108920401A (en) * | 2018-06-04 | 2018-11-30 | 深圳柴火创客教育服务有限公司 | It is more main mostly from I2C communication means, system and node device |
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| CN112069114A (en) * | 2020-09-07 | 2020-12-11 | 北京同有飞骥科技股份有限公司 | I2C arbitration method and device |
| CN112765082A (en) * | 2021-01-27 | 2021-05-07 | 维沃移动通信有限公司 | Multi-host arbitration method and device and readable storage medium |
| CN116566761A (en) * | 2023-03-28 | 2023-08-08 | 成都电科星拓科技有限公司 | SPI dual-host sharing arbitration system and method |
| CN117076373A (en) * | 2023-10-16 | 2023-11-17 | 北京紫光芯能科技有限公司 | Communication method, SPI controller and singlechip |
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| CN104408000A (en) * | 2014-12-05 | 2015-03-11 | 浪潮集团有限公司 | Method for preventing conflict in health information read of BIOS (Basic Input Output System) and BMC (Baseboard Management Controller) on Feiteng server |
| CN106953787A (en) * | 2017-03-28 | 2017-07-14 | 华南理工大学 | A kind of battery management system multi-host communication method and device based on electrical level transfer |
| CN106953787B (en) * | 2017-03-28 | 2022-09-20 | 华南理工大学 | Battery management system multi-host communication method and device based on level migration |
| CN108521854A (en) * | 2017-05-17 | 2018-09-11 | 深圳市大疆创新科技有限公司 | Communication control method, communication master device and communication system |
| CN108280041B (en) * | 2017-12-29 | 2020-03-10 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | Communication method and device for internal integrated circuit host |
| CN108280041A (en) * | 2017-12-29 | 2018-07-13 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | A kind of communication means and device of internal integrated circuit host |
| CN108920401A (en) * | 2018-06-04 | 2018-11-30 | 深圳柴火创客教育服务有限公司 | It is more main mostly from I2C communication means, system and node device |
| CN108920401B (en) * | 2018-06-04 | 2020-07-28 | 深圳柴火创客教育服务有限公司 | Multi-master multi-slave I2C communication method, system and node equipment |
| CN109634532A (en) * | 2018-12-19 | 2019-04-16 | 湖南源科创新科技有限公司 | The method of more VxWorks host share and access storage mediums |
| CN110850770A (en) * | 2019-11-08 | 2020-02-28 | 航天柏克(广东)科技有限公司 | Multi-host quick judgment and quitting method |
| CN110850770B (en) * | 2019-11-08 | 2021-05-11 | 航天柏克(广东)科技有限公司 | Multi-host quick judgment and quitting method |
| CN110780589A (en) * | 2019-11-08 | 2020-02-11 | 航天柏克(广东)科技有限公司 | Contention generation method of host |
| CN111444124A (en) * | 2020-03-25 | 2020-07-24 | 苏州琅润达检测科技有限公司 | Serial port shunting device with high-frequency autonomous request |
| CN112069114A (en) * | 2020-09-07 | 2020-12-11 | 北京同有飞骥科技股份有限公司 | I2C arbitration method and device |
| CN112765082A (en) * | 2021-01-27 | 2021-05-07 | 维沃移动通信有限公司 | Multi-host arbitration method and device and readable storage medium |
| CN112765082B (en) * | 2021-01-27 | 2024-04-26 | 维沃移动通信有限公司 | Multi-host arbitration method, device and readable storage medium |
| CN116566761A (en) * | 2023-03-28 | 2023-08-08 | 成都电科星拓科技有限公司 | SPI dual-host sharing arbitration system and method |
| CN116566761B (en) * | 2023-03-28 | 2024-02-02 | 成都电科星拓科技有限公司 | SPI dual-host sharing arbitration system and method |
| CN117076373A (en) * | 2023-10-16 | 2023-11-17 | 北京紫光芯能科技有限公司 | Communication method, SPI controller and singlechip |
| CN117076373B (en) * | 2023-10-16 | 2024-02-27 | 北京紫光芯能科技有限公司 | Communication method, SPI controller and singlechip |
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Application publication date: 20140305 |