CN110780589A - Contention generation method of host - Google Patents
Contention generation method of host Download PDFInfo
- Publication number
- CN110780589A CN110780589A CN201911085959.9A CN201911085959A CN110780589A CN 110780589 A CN110780589 A CN 110780589A CN 201911085959 A CN201911085959 A CN 201911085959A CN 110780589 A CN110780589 A CN 110780589A
- Authority
- CN
- China
- Prior art keywords
- machine
- competition
- host
- bus
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Bus Control (AREA)
Abstract
The invention discloses a competition generating method of a host, which comprises the following steps: adding an MS BUS, configuring a host competition circuit, connecting an MS-BUS, setting a mechanism and a serial number address, monitoring in real time, setting a competition success standard of the local machine and setting a competition protection mechanism; the invention sets that the status of each device in the system is equal, and the device can be a host through a competition mechanism, the system does not designate the host, the host is automatically generated by the competition mechanism, when the host breaks down, a new host can be quickly generated to ensure the normal and continuous operation of the whole system, and meanwhile, the competition time of each machine is staggered by correlating the competition time of each machine with the address of the device, thereby avoiding the phenomenon that a plurality of hosts compete successfully at the same time and rationalizing the competition.
Description
Technical Field
The invention relates to the technical field of automatic control, in particular to a competition generation method of a host.
Background
In some parallel applications of power electronics, there are many different control methods, such as: distributed control, master-slave control, etc., wherein the master-slave control is a widely used one, the master-slave control is to produce one as the master in many same devices, the other is used as the slave, the master sends out various synchronization and control signals, the slave adjusts the working state of the slave to be consistent with that of the master following the synchronization and control signals of the master, for example, the inverters are parallel connected, the input direct current voltage, circuit parameters, etc. of each inverter have differences, therefore, when the slave is parallel connected, the slave adjusts the parameters of the output voltage amplitude, frequency, phase, output current, etc. of the slave to make the slave follow the master to change;
the master-slave control method has the characteristics that only one host can be generated in the whole system, if a plurality of hosts are generated, the whole system can make mistakes, the host has a very important position as the core of the whole system, how the system generates the hosts becomes a very important technical point in the master-slave control system, some applications are that a specific machine is simply appointed to be fixed as the host, if the host fails, a new host cannot be generated, the whole system is stopped, and the method is simple but cannot achieve the redundancy effect, so the invention provides the competition generation method of the hosts to solve the problems in the prior art.
Disclosure of Invention
The invention provides a method for generating host computer competition, which sets the equal status of each device in the system, and can be used as the host computer through the competition mechanism, the system does not appoint the host computer, the host computer is generated by the competition mechanism, when the host computer is in fault, a new host computer can be generated quickly, the normal and continuous operation of the whole system is ensured, meanwhile, the competition time of each machine is staggered by correlating the competition time of each machine with the address of the device, the phenomenon that a plurality of host computers compete successfully at the same time is avoided, and the competition is rationalized.
In order to solve the above problem, the present invention provides a contention generation method for a host, comprising the following steps:
the method comprises the following steps: adding MS bus
The parallel machine state and data transmission between each machine in the system are carried out through a parallel machine interface, and then an MS bus is added in the parallel machine interface for competition of the host;
step two: configuring host race circuits
A host competition circuit is arranged in each machine, the output end of the circuit is connected with an MS BUS, then a control DSP in each machine is connected with the host competition circuit by using 2 IO pins, wherein IO-1 is set as the output pin of the host competition circuit, when the IO-1 pin of the DSP outputs high level '1', an MOS (metal oxide semiconductor) tube Q is cut off through an inverter and an isolation chip ISO7221B, the MS-BUS point outputs high level 10V, when the IO-1 pin of the DSP outputs low level '0', the MOS tube Q is switched on through the inverter and the isolation chip ISO7221B, and the MS-BUS point outputs low level 0V;
step three: connecting MS-BUS
The output point MS-BUS of each machine competition circuit is connected with the MS-BUS points of other machines through a parallel machine communication cable, so that the line and function is realized, as long as one machine in the system outputs low level 0, the MS BUS of the parallel machine interface is pulled down to be low level 0, meanwhile, the final state of the line and the line of the MS BUS is returned to the IO-2 pin of each DSP through the circuit, and the DSP obtains the current state of the MS BUS by reading the state of the IO-2 pin;
step four: setting mechanism and numbering address
Setting the status of each device in the system to be equal, and enabling each device to be a host through a competition mechanism, meanwhile, coding a unique address for each device in the parallel system, wherein the address starts from 1 to n ends, the value of n is limited according to specific application, and the address is used as a device identification code and also used as a weight when the host competes;
step five: real-time monitoring
The DSP of each slave machine monitors the state of the MS bus of the parallel machine interface in real time through an IO-2 input pin, and when the monitoring bus is high, the system does not have a host machine, so that the local machine starts host machine competition;
step six: setting the competition success standard of the computer
In the competition process, setting the holding time of the DSP of the local computer for detecting that the high state of the MS bus exceeds a specified value, namely considering that the local computer successfully competes to become a host computer, simultaneously outputting low by an IO-1 pin of the DSP, synchronously changing the MS bus of the parallel interface into a low state, informing other slave computers of generating a new host computer and stopping competition;
step seven: setting contention protection mechanism
The competition time of each machine is related to the address of the equipment, if the competition time of the machine No. 1 is t, the competition time of the machine No. 2 is 2t, the competition time of the machine No. 3 is 3t, and so on, the competition time of the machine No. n is nt, so that the competition time of each machine is staggered.
The further improvement lies in that: in the third step, the host competition circuit is output by OC, so that the function of 'wired AND' is realized among each machine competition circuit.
The further improvement lies in that: in the fourth step, the judgment standard that the machine is a master machine and a slave machine is set: when the local machine is a master machine, IO-1 outputs low level, and when the local machine is a slave machine, IO-1 outputs high level.
The further improvement lies in that: in the fourth step, the address is also used as the priority of the host in contention.
The further improvement lies in that: in the fifth step, when the monitoring bus is "low", it indicates that the system already has the master, and then the local machine keeps the slave state and stops the master competition.
The further improvement lies in that: in the sixth step, the holding time of the local DSP detecting the high state of the MS bus is the competition time.
The further improvement lies in that: in the seventh step, the purpose of staggering the competition time of each machine is as follows: the phenomenon that a plurality of hosts compete successfully at the same time is avoided.
The invention has the beneficial effects that: the invention sets that the status of each device in the system is equal, and can be used as a master machine through a competition mechanism, the DSP of each slave machine monitors the state of the MS bus of the parallel machine interface in real time through an IO-2 input pin, when the monitoring bus is high, the system does not have the master machine, the local machine starts the master machine competition, in the competition process, the DSP of the local machine detects that the holding time of the high state of the MS bus exceeds a specified value, and the local machine is considered to be successful in competition, and becomes the master machine, in conclusion, the system does not appoint the master machine, the master machine is automatically generated by the competition mechanism, when the master machine has a fault, a new master machine can be quickly generated, the normal and continuous operation of the whole system is ensured, meanwhile, the competition time of each machine is staggered by correlating the competition time of each machine with the device address, and the phenomenon that a plurality of master machines, rationalizing competition.
Drawings
FIG. 1 is a schematic diagram of an MS bus according to the present invention;
FIG. 2 is a schematic diagram of a host contention circuit according to the present invention;
FIG. 3 is a schematic view of a verification example 1 of the present invention;
FIG. 4 is a schematic diagram of verification example 2 of the present invention.
Detailed Description
In order to make the technical means, objectives and functions of the invention easy to understand, the invention will be further described with reference to the following embodiments.
As shown in fig. 1 and 2, the present embodiment provides a contention generating method for a host, which includes the following specific steps:
the method comprises the following steps: adding MS bus
Performing parallel operation state and data transmission between each machine in the system through a parallel operation interface, and then adding an MS bus in the parallel operation interface for competition of the host, as shown in fig. 1;
step two: configuring host race circuits
Setting a host competition circuit in each machine, connecting the output end of the circuit with an MS BUS, as shown in fig. 2, then connecting a control DSP in each machine with the host competition circuit by using 2 IO pins, wherein IO-1 is set as the output pin of the host competition circuit, when the IO-1 pin of the DSP outputs high level '1', an MOS tube Q is cut off through a phase inverter and an isolation chip ISO7221B, the MS-BUS point outputs high level 10V, when the IO-1 pin of the DSP outputs low level '0', the MOS tube Q is switched on through the phase inverter and the isolation chip ISO7221B, and the MS-BUS point outputs low level 0V;
step three: connecting MS-BUS
The output point MS-BUS of each machine competition circuit is connected with the MS-BUS points of other machines through a parallel machine communication cable, the host competition circuit is OC output, the line and function is realized among the host competition circuits, as long as one machine in the system outputs low level 0, the MS BUS of the parallel machine interface is pulled down to be low level 0, meanwhile, the final state of line and of the MS BUS is returned to the IO-2 pin of each DSP through the circuit, and the DSP obtains the current state of the MS BUS by reading the state of the IO-2 pin;
step four: setting mechanism and numbering address
Setting the status of each device in the system to be equal, and setting the judgment standard that the device is a master and a slave through a competition mechanism: when the local machine is a host machine, IO-1 outputs low level, when the local machine is a slave machine, IO-1 outputs high level, and simultaneously, each device in the parallel machine system is coded with a unique address, the address starts from 1 to n ends, the numerical value of n is limited according to specific application, and the address is used as a device identification code and also used as the weight and priority when the host machine competes;
step five: real-time monitoring
The DSP of each slave machine monitors the MS bus state of the parallel machine interface in real time through an IO-2 input pin, when the monitoring bus is low, the system is in the state of the master machine, the local machine keeps the slave machine state, the host machine competition is stopped, and when the monitoring bus is high, the system is not in the state of the master machine, the local machine starts the host machine competition;
step six: setting the competition success standard of the computer
In the competition process, setting the holding time of the DSP of the local machine for detecting that the high state of the MS bus exceeds a specified value, wherein the holding time is the competition time, namely the local machine is considered to compete successfully and becomes a main machine, meanwhile, the IO-1 pin of the DSP outputs low, the MS bus of the parallel machine interface synchronously becomes a low state, and informing other slave machines that a new main machine is generated and the competition is stopped;
step seven: setting contention protection mechanism
The competition time of each machine is related to the equipment address, if the competition time of the machine No. 1 is t, the competition time of the machine No. 2 is 2t, the competition time of the machine No. 3 is 3t, and so on, the competition time of the machine No. n is nt, so that the competition time of each machine is staggered, and the aim is to: the phenomenon that a plurality of hosts compete successfully at the same time is avoided.
Verification example 1:
assume that there are 4 hosts in the system with addresses from 1 to 4. As shown in fig. 3.
a) At start 0, 4# is the master and the others are slaves. The IO-1 pin of the 4# machine outputs 'low'; other machines remain in the slave state with the IO-1 pin output "high". The state of the MS bus at this time is "low".
b) At time 2t, the 4# machine exits due to a fault, the IO-1 pin of the 4# machine is changed to output 'high', and the state of the MS bus is also changed from 'low' to 'high'. The other machines detect the change of the MS bus and start to enter a host competition state. The competition time of the machine # 1 is t, the competition time of the machine # 2 is 2t, and the competition time of the machine # 3 is 3 t.
c) And at the moment of 3t, the competition time of the 1# machine is ended first, the competition is successfully used as the host, and the IO-1 pin of the 1# machine outputs 'low'. The state of the MS bus is also changed from "high" to "low". The # 2 and # 3 machines which have entered the contention state exit the contention after detecting the change of the MS bus, and continue to maintain the slave state.
Verification example 2:
assume that there are 4 hosts in the system with addresses from 1 to 4. As shown in fig. 4.
a) At time 0 of start, 1# is the master and the others are slaves. IO-1 pin output of 1# machine is low; other machines remain in the slave state with the IO-1 pin output "high". The state of the MS bus at this time is "low".
b) At time 2t, the 1# machine exits due to a fault, the IO-1 pin of the 1# machine is changed to output 'high', and the state of the MS bus is also changed from 'low' to 'high'. The other machines detect the change of the MS bus and start to enter a host competition state. The competition time of the 2# machine is 2t, the 3# machine is 3t, and the 4# machine is 4 t.
c) And at the moment of 4t, the competition time of the 2# machine is ended first, the competition is successfully changed into the host, and the IO-1 pin of the 2# machine outputs 'low'. The state of the MS bus is also changed from "high" to "low". The # 3, 4 machine that has entered the contention state exits the contention after detecting the change of the MS bus, and continues to maintain the slave state.
The invention sets that the status of each device in the system is equal, and can be used as a master machine through a competition mechanism, the DSP of each slave machine monitors the state of the MS bus of the parallel machine interface in real time through an IO-2 input pin, when the monitoring bus is high, the system does not have the master machine, the local machine starts the master machine competition, in the competition process, the DSP of the local machine detects that the holding time of the high state of the MS bus exceeds a specified value, and the local machine is considered to be successful in competition, and becomes the master machine, in conclusion, the system does not appoint the master machine, the master machine is automatically generated by the competition mechanism, when the master machine has a fault, a new master machine can be quickly generated, the normal and continuous operation of the whole system is ensured, meanwhile, the competition time of each machine is staggered by correlating the competition time of each machine with the device address, and the phenomenon that a plurality of master machines, rationalizing competition.
The foregoing illustrates and describes the principles, general features, and advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (7)
1. A contention generating method for a host, comprising: the method comprises the following steps:
the method comprises the following steps: adding MS bus
The parallel machine state and data transmission between each machine in the system are carried out through a parallel machine interface, and then an MS bus is added in the parallel machine interface for competition of the host;
step two: configuring host race circuits
A host competition circuit is arranged in each machine, the output end of the circuit is connected with an MS BUS, then a control DSP in each machine is connected with the host competition circuit by using 2 IO pins, wherein IO-1 is set as the output pin of the host competition circuit, when the IO-1 pin of the DSP outputs high level '1', an MOS (metal oxide semiconductor) tube Q is cut off through an inverter and an isolation chip ISO7221B, the MS-BUS point outputs high level 10V, when the IO-1 pin of the DSP outputs low level '0', the MOS tube Q is switched on through the inverter and the isolation chip ISO7221B, and the MS-BUS point outputs low level 0V;
step three: connecting MS-BUS
The output point MS-BUS of each machine competition circuit is connected with the MS-BUS points of other machines through a parallel machine communication cable, so that the line and function is realized, as long as one machine in the system outputs low level 0, the MS BUS of the parallel machine interface is pulled down to be low level 0, meanwhile, the final state of the line and the line of the MS BUS is returned to the IO-2 pin of each DSP through the circuit, and the DSP obtains the current state of the MS BUS by reading the state of the IO-2 pin;
step four: setting mechanism and numbering address
Setting the status of each device in the system to be equal, and enabling each device to be a host through a competition mechanism, meanwhile, coding a unique address for each device in the parallel system, wherein the address starts from 1 to n ends, the value of n is limited according to specific application, and the address is used as a device identification code and also used as a weight when the host competes;
step five: real-time monitoring
The DSP of each slave machine monitors the state of the MS bus of the parallel machine interface in real time through an IO-2 input pin, and when the monitoring bus is high, the system does not have a host machine, so that the local machine starts host machine competition;
step six: setting the competition success standard of the computer
In the competition process, setting the holding time of the DSP of the local computer for detecting that the high state of the MS bus exceeds a specified value, namely considering that the local computer successfully competes to become a host computer, simultaneously outputting low by an IO-1 pin of the DSP, synchronously changing the MS bus of the parallel interface into a low state, informing other slave computers of generating a new host computer and stopping competition;
step seven: setting contention protection mechanism
The competition time of each machine is related to the address of the equipment, if the competition time of the machine No. 1 is t, the competition time of the machine No. 2 is 2t, the competition time of the machine No. 3 is 3t, and so on, the competition time of the machine No. n is nt, so that the competition time of each machine is staggered.
2. The method of claim 1, wherein: in the third step, the host competition circuit is output by OC, so that the function of 'wired AND' is realized among each machine competition circuit.
3. The method of claim 1, wherein: in the fourth step, the judgment standard that the machine is a master machine and a slave machine is set: when the local machine is a master machine, IO-1 outputs low level, and when the local machine is a slave machine, IO-1 outputs high level.
4. The method of claim 1, wherein: in the fourth step, the address is also used as the priority of the host in contention.
5. The method of claim 1, wherein: in the fifth step, when the monitoring bus is "low", it indicates that the system already has the master, and then the local machine keeps the slave state and stops the master competition.
6. The method of claim 1, wherein: in the sixth step, the holding time of the local DSP detecting the high state of the MS bus is the competition time.
7. The method of claim 1, wherein: in the seventh step, the purpose of staggering the competition time of each machine is as follows: the phenomenon that a plurality of hosts compete successfully at the same time is avoided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911085959.9A CN110780589A (en) | 2019-11-08 | 2019-11-08 | Contention generation method of host |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911085959.9A CN110780589A (en) | 2019-11-08 | 2019-11-08 | Contention generation method of host |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110780589A true CN110780589A (en) | 2020-02-11 |
Family
ID=69389691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911085959.9A Pending CN110780589A (en) | 2019-11-08 | 2019-11-08 | Contention generation method of host |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110780589A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116047887A (en) * | 2022-12-29 | 2023-05-02 | 孚瑞肯电气(深圳)有限公司 | Method and device for multi-host variable-frequency constant-pressure water supply |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814984A (en) * | 1986-05-30 | 1989-03-21 | International Computers Limited | Computer network system with contention mode for selecting master |
| JPH05120214A (en) * | 1991-03-30 | 1993-05-18 | Deutsche Itt Ind Gmbh | Bus arbitration method for multiple-master system |
| CN1430324A (en) * | 2001-12-31 | 2003-07-16 | 艾默生网络能源有限公司 | Method of establishing host machine in multi-module parallel system |
| CN1479542A (en) * | 2002-08-30 | 2004-03-03 | 深圳市中兴通讯股份有限公司上海第二 | Fair bus arbitration method and arbitration device |
| CN101154093A (en) * | 2006-09-26 | 2008-04-02 | 力博特公司 | Method and apparatus for competing for host computer position in parallel system |
| CN103617138A (en) * | 2013-12-16 | 2014-03-05 | 深圳市兴威帆电子技术有限公司 | Multi-mainframe arbitration method and multi-mainframe communication system |
| CN106773862A (en) * | 2016-12-30 | 2017-05-31 | 深圳市英威腾电气股份有限公司 | A kind of rectifier combining system and its control method |
| CN107547281A (en) * | 2017-09-18 | 2018-01-05 | 通鼎互联信息股份有限公司 | A kind of main and standby competition method, apparatus and application apparatus |
-
2019
- 2019-11-08 CN CN201911085959.9A patent/CN110780589A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814984A (en) * | 1986-05-30 | 1989-03-21 | International Computers Limited | Computer network system with contention mode for selecting master |
| JPH05120214A (en) * | 1991-03-30 | 1993-05-18 | Deutsche Itt Ind Gmbh | Bus arbitration method for multiple-master system |
| CN1430324A (en) * | 2001-12-31 | 2003-07-16 | 艾默生网络能源有限公司 | Method of establishing host machine in multi-module parallel system |
| CN1479542A (en) * | 2002-08-30 | 2004-03-03 | 深圳市中兴通讯股份有限公司上海第二 | Fair bus arbitration method and arbitration device |
| CN101154093A (en) * | 2006-09-26 | 2008-04-02 | 力博特公司 | Method and apparatus for competing for host computer position in parallel system |
| CN103617138A (en) * | 2013-12-16 | 2014-03-05 | 深圳市兴威帆电子技术有限公司 | Multi-mainframe arbitration method and multi-mainframe communication system |
| CN106773862A (en) * | 2016-12-30 | 2017-05-31 | 深圳市英威腾电气股份有限公司 | A kind of rectifier combining system and its control method |
| CN107547281A (en) * | 2017-09-18 | 2018-01-05 | 通鼎互联信息股份有限公司 | A kind of main and standby competition method, apparatus and application apparatus |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116047887A (en) * | 2022-12-29 | 2023-05-02 | 孚瑞肯电气(深圳)有限公司 | Method and device for multi-host variable-frequency constant-pressure water supply |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105677420B (en) | interface pin configuration method and device | |
| CN105204600B (en) | A kind of I2C bus-sharings realize integrated chip repositioning method, system and electronic equipment | |
| CN103324546B (en) | A kind of method and device of watchdog service delay | |
| CN104516306B (en) | The automated system of redundancy | |
| CN103376400A (en) | Chip testing method and chip | |
| EP0131658A1 (en) | A synchronisation mechanism for a multiprocessing system | |
| CN103106113A (en) | Interrupt event processing method and processing equipment | |
| EP2688258A1 (en) | Single board communication method, system and single board | |
| CN102033502B (en) | Programmable controller | |
| CN110780589A (en) | Contention generation method of host | |
| CN103092310B (en) | Power supply control device and processing system | |
| CN106249687A (en) | A kind of method of backboard communication | |
| CN102611600B (en) | Method and device for locating short circuit position of CAN (Controller Area Network) network | |
| CN107480090B (en) | Circuit and method for realizing GPIO function on serial peripheral interface device | |
| US9792193B2 (en) | Method and system for processing data conflict | |
| CN106656711B (en) | A kind of predefined method of token bus time slot | |
| CN106338938B (en) | A kind of backplane bus communication addressing system and method | |
| CN109557453B (en) | Multi-master-control-chip identification processing method and system | |
| CN110850770B (en) | Multi-host quick judgment and quitting method | |
| CN112859660B (en) | Equipment synchronization control method, device, terminal and system | |
| CN107797046A (en) | The method of testing of one input/output interface of integrated circuit and integrated circuit | |
| JP2012068907A (en) | Bus connection circuit and bus connection method | |
| CN212324117U (en) | RS485 bus multi-host competition switching system | |
| KR102104967B1 (en) | Duplicated board setting method and the board thereof | |
| CN107017802A (en) | The supervising device and method of a kind of high-voltage solid-state soft starter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200211 |