CN103530215B

CN103530215B - A kind of self checking method of internal integrated circuit main frame, device and main frame

Info

Publication number: CN103530215B
Application number: CN201310462874.4A
Authority: CN
Inventors: 郭中天; 种锋生; 黄平
Original assignee: Hangzhou Huawei Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2013-09-30
Filing date: 2013-09-30
Publication date: 2015-12-02
Anticipated expiration: 2033-09-30
Also published as: CN103530215A

Abstract

The invention discloses a kind of self checking method of internal integrated circuit main frame, device and main frame, belong to communication technical field.Described method comprises: whether I2C Host Detection I2C bus is busy; When described I2C bus busy, receive the packet that described I2C bus is transmitted, and whether detect the link of described I2C main frame according to described packet normal.The present invention is by when I2C bus busy, receive the packet that I2C bus is transmitted, and the link of I2C main frame is detected according to this packet, therefore do not need just can carry out the self-inspection of I2C main frame when waiting until I2C bus free, can carry out in real time, avoid in the process of I2C host waits self-inspection, occur that the I2C main frame of current control I2C bus breaks down, I2C main frame for subsequent use can not replace, and causes the problem that the I2C main frame of control I2C bus is changed repeatedly.

Description

A kind of self checking method of internal integrated circuit main frame, device and main frame

Technical field

The present invention relates to communication technical field, particularly a kind of self checking method of internal integrated circuit main frame, device and main frame.

Background technology

I2C (InterIntegratedCircuit, internal integrated circuit) bus is a kind of bus standard that microelectronics Control on Communication field extensively adopts, for connecting I2C main frame, I2C from devices such as machines.The device that I2C main frame is initialization transmission, clocking and termination send, can become the device of control I2C bus, I2C from machine by the device of I2C host addressing.

Usual I2C bus is only provided with a main frame.If I2C bus is connected with two I2C main frames, then one is the I2C main frame of current control I2C bus, and another is I2C main frame for subsequent use.With the I2C main frame that an I2C main frame is current control I2C bus, the 2nd I2C main frame is I2C main frame for subsequent use is example, and when an I2C main frame breaks down, the 2nd I2C main frame can replace an I2C host computer control I2C bus.If the 2nd I2C main frame can not control I2C bus, then an I2C main frame can replace again the 2nd I2C host computer control I2C bus.Because fault has appearred in an I2C main frame, therefore an I2C main frame can not control I2C bus, 2nd I2C main frame replaces an I2C host computer control I2C bus again, so repeatedly, causes I2C bus and is connected to the device cisco unity malfunction in I2C bus.

In order to avoid there is this problem, when I2C main frame for subsequent use is connected with I2C bus, I2C main frame for subsequent use can carry out self-inspection, during to guarantee that I2C main frame (as the 2nd I2C main frame) for subsequent use replaces I2C main frame (as an I2C main frame) the control I2C bus of current control I2C bus, can control I2C bus.The self checking method of existing I2C main frame comprises: I2C main frame for subsequent use at I2C total online application I2C bus resource until this I2C host computer control I2C bus; When after this I2C host computer control I2C bus, send packet to I2C from machine; If receive the response signal of I2C from machine, then judge that this I2C main frame can control I2C bus.

Realizing in process of the present invention, inventor finds that prior art at least exists following problem:

I2C main frame for subsequent use only have by the time I2C bus free time, ability control I2C bus, and after only having this I2C host computer control I2C bus, packet could be sent to I2C from machine, to judge that can this I2C main frame control I2C bus, therefore the self checking method of existing I2C main frame can not carry out in real time.If in the process of I2C host waits I2C bus free for subsequent use, there is fault in the I2C main frame of current control I2C bus, then can not avoid the problem occurring the I2C main frame repeatedly changing control I2C bus.

Summary of the invention

Can not carry out in real time to solve prior art, the problem occurring the I2C main frame repeatedly changing control I2C bus can not be avoided, embodiments provide a kind of self checking method of internal integrated circuit I2C main frame, device and main frame.Described technical scheme is as follows:

On the one hand, embodiments provide a kind of self checking method of internal integrated circuit I2C main frame, described I2C main frame is connected with I2C bus by the link of described I2C main frame, and described method comprises:

Whether I2C Host Detection I2C bus is busy;

When described I2C bus busy, receive the packet that described I2C bus is transmitted, and whether detect the link of described I2C main frame according to described packet normal;

Described I2C main frame comprises main equipment and from equipment, described main equipment is connected with described I2C bus by the link of described I2C main frame, is describedly connected from equipment with described main equipment, and described method also comprises:

When described I2C bus busy, control described main equipment from described from equipment reading data and to described from equipment write data, whether normal with the read-write capability detecting described I2C main frame;

When the link of described I2C main frame is normal and read-write capability that is described I2C main frame is normal, judge that described I2C main frame can control described I2C bus.

In the implementation that the first is possible, the described main equipment of described control, whether normally to detect the read-write capability of described I2C main frame comprising from described from equipment reading data and to described from equipment write data:

Control described main equipment and from equipment, read preset data from described, when the data that described main equipment reads are identical with the preset data in described main equipment, judge described I2C main frame to read function normal, when the data that described main equipment reads are different from the preset data in described main equipment, judge described I2C main frame to read function abnormal;

Control described main equipment by described from equipment for the preset data write in described main equipment, when the write of described main equipment described from the data equipment with described identical from the preset data equipment time, judge described I2C main frame to write function normal, when the write of described main equipment described from the data equipment from described different from the preset data equipment time, judge described I2C main frame to write function abnormal;

Wherein, preset data the described main equipment of described control from described from equipment read data and to described from equipment write data, before whether normal with the read-write capability detecting described I2C main frame, be stored in described main equipment and described from equipment, and preset data in described main equipment and described from the preset data equipment be identical.

In the implementation that the second is possible, described I2C bus comprises serial time clock line and serial data line, the link of described I2C main frame comprises serial clock link and serial data link, the packet that the described I2C bus of described reception is transmitted, and whether normally to detect the link of described I2C main frame according to described packet, comprising:

Receive the clock signal on described serial time clock line, whether identically with the standard clock signal preset detect described clock signal, whether normal to judge described serial clock link;

Receive first response signal on described serial data line after start signal, whether identically with the normal response signal preset detect first response signal after described start signal, to judge that whether described serial data link is normal;

When described serial clock link is normal and described serial data link is normal, judge that the link of described I2C main frame is normal.

Alternatively, whether the described clock signal of described detection is identical with the standard clock signal preset, and to judge that whether described serial clock link is normal, comprising:

Within the sampling time, using the first signal as with reference to signal, described clock signal is sampled, and records the quantity that sampled result is high level, the frequency of described first signal be the n of described standard clock signal frequency doubly, n >=2 and n is integer;

Whether the high level quantity of detection record is identical with predetermined quantity, and described predetermined quantity is within the described sampling time, and using described first signal as reference signal, the sampled result of described standard clock signal being carried out to sampling acquisition is the quantity of high level;

When detecting that the high level quantity of described record is identical with described predetermined quantity, judge that described serial clock link is normal;

When detecting that the high level quantity of described record is different from described predetermined quantity, judge that described serial clock link is abnormal.

Alternatively, whether first response signal after the described start signal of described detection be identical with the normal response signal preset, and to judge that whether described serial data link is normal, comprising:

When the response signal of first after described start signal is low level, judge that described serial data link is normal;

When the response signal of first after described start signal is high level, judge that described serial data link is abnormal.

Further, whether first response signal after the described start signal of described detection be identical with the normal response signal preset, and to judge that whether described serial data link is normal, also comprises:

When first response signal after data direction position, described start signal, second response signal after start signal are low level, or,

When signal after second response signal after to be first response signal after high level, described start signal be low level, start signal when the response signal of second behind data direction position and start signal is stop signal, or,

When data direction position be high level, first response signal after described start signal and second response signal after start signal be low level, start signal after second response signal after signal be not stop signal time, judge that described serial data link is normal;

Otherwise, judge that described serial data link is abnormal.

In the implementation that the third is possible, described method also comprises:

When described I2C bus free, control described I2C bus, and send preset data bag to I2C from machine;

When receiving the response signal that described I2C sends from machine, judge that described I2C main frame can control described I2C bus.

On the other hand, embodiments provide a kind of self-checking unit of internal integrated circuit I2C main frame, described I2C main frame is connected with I2C bus by the link of described I2C main frame, and described device comprises:

Bus detection module, whether busy for detecting I2C bus;

Link detection module, for when described I2C bus busy, receives the packet that described I2C bus is transmitted, and whether detect the link of described I2C main frame according to described packet normal;

Described I2C main frame comprises main equipment and from equipment, described main equipment is connected with described I2C bus by the link of described I2C main frame, is describedly connected from equipment with described main equipment, and described device also comprises:

Whether read-write capability detection module, for when described I2C bus busy, controls described main equipment and reads data and to described from equipment write data from described from equipment, normal with the read-write capability detecting described I2C main frame;

Judge module, for when the link of described I2C main frame is normal and read-write capability that is described I2C main frame is normal, judges that described I2C main frame can control described I2C bus.

In the implementation that the first is possible, described read-write capability detection module comprises:

Read comparing unit, from equipment, preset data is read from described for controlling described main equipment, when the data that described main equipment reads are identical with the preset data in described main equipment, judge described I2C main frame to read function normal, when the data that described main equipment reads are different from the preset data in described main equipment, judge described I2C main frame to read function abnormal;

Write comparing unit, for controlling described main equipment by described from equipment for the preset data write in described main equipment, when the write of described main equipment described from the data equipment with described identical from the preset data equipment time, judge described I2C main frame to write function normal, when the write of described main equipment described from the data equipment from described different from the preset data equipment time, judge described I2C main frame to write function abnormal;

In the implementation that the second is possible, described I2C bus comprises serial time clock line and serial data line, and the link of described I2C main frame comprises serial clock link and serial data link, and described link detection module comprises:

Whether whether identical with the standard clock signal preset serial clock link detecting unit, for receiving the clock signal on described serial time clock line, detect described clock signal, normal to judge described serial clock link;

Serial data link detecting unit, for receiving first response signal on described serial data line after start signal, whether identically with the normal response signal preset detect first response signal after described start signal, to judge that whether described serial data link is normal;

Judging unit, for when described serial clock link is normal and described serial data link is normal, judges that the link of described I2C main frame is normal.

Alternatively, described serial clock link detecting unit comprises:

Sampling subelement, within the sampling time, using the first signal as reference signal, described clock signal is sampled, and record the quantity that sampled result is high level, the frequency of described first signal be the n of described standard clock signal frequency doubly, n >=2 and n is integer;

Quantity detection sub-unit, whether the high level quantity for detection record is identical with predetermined quantity, described predetermined quantity is within the described sampling time, and using described first signal as reference signal, the sampled result of described standard clock signal being carried out to sampling acquisition is the quantity of high level; When detecting that the high level quantity of described record is identical with described predetermined quantity, judge that described serial clock link is normal; When detecting that the high level quantity of described record is different from described predetermined quantity, judge that described serial clock link is abnormal.

Alternatively, described serial data link detecting unit is used for,

Further, described serial data link detecting unit also for,

Otherwise, judge that described serial data link is abnormal.

In the implementation that the third is possible, described device also comprises:

Host Detection module, during for described I2C bus free, control I2C bus, and send preset data bag to I2C from machine;

Judge module, for when receiving the response signal that described I2C sends from machine, judges that described I2C main frame can control described I2C bus.

Another aspect, embodiments provide a kind of internal integrated circuit I2C main frame, described main frame comprises bus interface and processor, and described processor is used for the self checking method of above-mentioned I2C main frame.

The beneficial effect that the technical scheme that the embodiment of the present invention provides is brought is:

By when I2C bus busy, receive the packet that I2C bus is transmitted, and detect the link of I2C main frame according to this packet, therefore do not need by the time I2C bus free time just can carry out the self-inspection of I2C main frame.The embodiment of the present invention can be carried out in real time, avoid in the process of I2C host waits self-inspection, occur that the I2C main frame of the current control I2C bus existed in prior art breaks down, I2C main frame for subsequent use can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the I2C main frame of control I2C bus is changed repeatedly.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the application scenarios figure of the self checking method of a kind of I2C main frame that the embodiment of the present invention provides;

Fig. 2 is the process flow diagram of the self checking method of a kind of I2C main frame that the embodiment of the present invention one provides;

Fig. 3 is the process flow diagram of the self checking method of a kind of I2C main frame that the embodiment of the present invention two provides;

Fig. 4 is the whether normal process flow diagram of link of the detection I2C main frame that the embodiment of the present invention two provides;

Fig. 5 is the process flow diagram of the self checking method of a kind of I2C main frame that the embodiment of the present invention three provides;

Fig. 6 is the structural representation of the self-checking unit of a kind of I2C main frame that the embodiment of the present invention four provides;

Fig. 7 is the structural representation of the self-checking unit of a kind of I2C main frame that the embodiment of the present invention five provides;

Fig. 8 is the hardware structure diagram of a kind of I2C main frame that the embodiment of the present invention six provides.

Embodiment

For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiment of the present invention is described further in detail.

First composition graphs 1 simply introduces the application scenarios of the self checking method of the I2C main frame that the embodiment of the present invention provides, and this application scenarios is only one of them application scenarios of the embodiment of the present invention, and the present invention is not restricted to this.

I2C bus is twin wire universal serial bus, comprises SCL (SerialClock, serial clock) line and SDA (SerialData, serial data) line, is generally used for connecting microcontroller and peripherals thereof.As shown in Figure 1, in order to ensure the stability contorting to I2C bus, I2C bus is generally connected with primary and backup two I2C main frames, in embodiments of the present invention, be respectively an I2C main frame 1, the 2nd I2C main frame 2, easily know, primary I2C main frame refers to the I2C main frame of current control I2C bus, and I2C main frame for subsequent use refers to the I2C main frame of current control I2C bus.

In embodiments of the present invention, I2C main frame can be microcontroller, as CPLD (ComplexProgrammableLogicDevice, CPLD), FPGA (FieldProgrammableGateArray, field programmable gate array).

I2C bus is also connected with several I2C from machine, a such as I2C is from machine 3, the 2nd I2C from machine 4 and the 3rd I2C from machine 5.In embodiments of the present invention, I2C includes but not limited to LCD (LiquidCrystalDisplay from machine, liquid crystal display) driver, I/O (Input/Output, I/O) mouth (as keyboard interface), storer is (as RAM (RandomAccessMemory, random access memory), EEPROM (ElectricallyErasableProgrammableRead-OnlyMemory, EEPROM (Electrically Erasable Programmable Read Only Memo))), data converter, DTMF (the DualToneMultiFrequency of the digital tuning of radio and video system and signal processing circuit and voice-frequency dialing phone, dual-tone multifrequency) generator.

It should be noted that, in Fig. 1, I2C main frame and I2C are only citing from the number of machine, and the I2C number of host be connected with I2C bus can also increase, and I2C can increase or reduce from machine number.

I2C main frame and I2C are all connected to I2C bus 6 by respective I2C link from machine.Particularly, connected by the first link 16 between one I2C main frame 1 and I2C bus 6, connected by the second link 26 between 2nd I2C main frame 2 and I2C bus 6, one I2C is connected between machine 3 and I2C bus 6 by the 3rd link 36,2nd I2C is connected between machine 4 and I2C bus 6 by the 4th link 46, and the 3rd I2C is connected between machine 5 and I2C bus 6 by the 5th link 56.Easily know, because I2C bus comprises SCL line and SDA line, therefore I2C main frame or I2C also comprise SCL link and SDA link two links from the link that machine is connected with I2C bus separately.

Embodiment one

Embodiments provide a kind of self checking method of I2C main frame, the method can perform when I2C main frame for subsequent use and I2C bus connect, and see Fig. 2, the method comprises:

Whether step 101:I2C Host Detection I2C bus is busy.

Whether step 102: when I2C bus busy, receives the packet that I2C bus is transmitted, and normal according to the link of this packet detection I2C main frame.

The embodiment of the present invention, by when I2C bus busy, receives the packet that I2C bus is transmitted, and detects the link of I2C main frame according to this packet, does not therefore need just can carry out the self-inspection of I2C main frame when waiting until I2C bus free.The embodiment of the present invention can be carried out in real time, avoid in the process of I2C host waits self-inspection, occur that the I2C main frame of the current control I2C bus existed in prior art breaks down, I2C main frame for subsequent use can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the I2C main frame of control I2C bus is changed repeatedly.

Embodiment two

Embodiments provide a kind of self checking method of I2C main frame, the method can perform when I2C main frame for subsequent use and I2C bus connect, and see Fig. 3, the method comprises:

Whether step 201:I2C Host Detection I2C bus is busy.

Particularly, whether this step 201 can comprise: have level to change in the cycle detecting standard clock signal default on SCL line; If SCL line has level to change within the cycle of a default standard clock signal, then I2C bus busy; If SCL line does not have level to change within the cycle of a default standard clock signal, then I2C bus free.

It should be noted that, according to I2C agreement, when the enterprising line number of I2C bus is reportedly defeated, namely during I2C bus busy, SCL line there will be the level of height change, and the cycle of level change is the cycle cycle of default standard clock signal (time interval between two high level be) of default standard clock signal; When I2C bus not being carried out data transmission, namely during I2C bus free, SCL line remains high level.Usual each I2C bus can preset a standard clock signal, and each equipment be connected with this I2C bus can get cycle and/or the frequency of the standard clock signal of this I2C bus.Under normal circumstances, the clock signal frequency on SCL line is identical with this standard clock signal frequency.

Whether step 202: when I2C bus busy, receives the packet that I2C bus is transmitted, and normal according to the link of this packet detection I2C main frame.

Particularly, see Fig. 3, this step 202 can comprise:

Whether identical with the standard clock signal preset step 2021: receive the clock signal on SCL line, detect this clock signal, to judge that whether SCL link is normal.

Alternatively, this step 2021 can comprise: within the sampling time, using the first signal as with reference to signal, samples, and record the quantity that sampled result is high level to clock signal; Whether the high level quantity of detection record is identical with predetermined quantity; When detecting that the high level quantity of record is identical with predetermined quantity, judge that SCL link is normal; When detecting that the high level quantity of record is different from predetermined quantity, judge that SCL link is abnormal.

In the present embodiment, the frequency of the first signal be the n of standard clock signal frequency doubly, n >=2 and n is integer.Predetermined quantity is within the sampling time, and using the first signal as reference signal, the sampled result of standard clock signal being carried out to sampling acquisition is the quantity of high level.

Further, the sampling time can be the cycle of at least one standard clock signal.

Whether identical with the normal response signal preset step 2022: receive first response signal after start signal on SDA line, detect first response signal after start signal, to judge that whether SDA link is normal.

Alternatively, this step 2022 can comprise: when the response signal of first after start signal is low level, judges that SDA link is normal; When the response signal of first after start signal is high level, judge that SDA link is abnormal.

It should be noted that, specify in I2C agreement, SDA line must transmit data in units of byte, each byte heel response signal, but the byte quantity of transmission is unrestricted.The normal response signal preset receives successful response signal for showing.Generally show to receive successfully by low level response signal.But when I2C main frame reads I2C from the data of machine, I2C main frame reads I2C after the data of last byte of machine, SDA line can be remained high level (because SDA line and SCL line are all connected to power supply by pull-up circuit, therefore only otherwise carry out operation can to realize response signal be high level), to show to receive successfully, then I2C main frame sends stop signal (when SCL line is high level, SDA line switches to high level from low level).Except above-mentioned situation, general when response signal is high level, show to take defeat.

According to I2C agreement, when I2C bus starting data transmission, first start signal is sent (when SCL line is high level by I2C main frame, SDA line switches to low level from high level), then I2C main frame can send with the I2C of this I2C main-machine communication from seven bit address of machine and data direction position, this seven bit address is the mark of I2C from machine, can determine with the I2C of I2C main-machine communication from machine according to this address.After this I2C to receive seven bit address and data direction position that I2C main frame sends from machine, the level on SDA line is dragged down, to realize response signal for low level, show that I2C successfully receives from machine seven bit address and data direction position that I2C main frame sends.Then according to data direction position, " 0 " (low level) represents that I2C main frame writes data into I2C from machine, " 1 " (high level) represents that I2C main frame reads the data of I2C from machine, I2C main frame and I2C transmit data between machine in I2C bus in units of eight bit data, after every eight bit data is transmitted, have a response signal, response signal is high level, or the side that low level receives data by I2C main frame and I2C from machine determines.After data are transmitted, I2C main frame sends stop signal.

No matter the level of data direction position is high level or low level, after I2C main frame sends seven bit address and data direction position, if I2C successfully receives from machine, is bound to the level on SDA line to drag down, makes response signal be low level.In the process of data transmission, if data are write I2C from machine by I2C main frame, the level on SDA line can drag down, makes response signal be low level after often successfully receiving eight bit data from machine by I2C; If I2C main frame reads the data of I2C from machine, after I2C main frame often successfully receives eight bit data, generally also the level on SDA line can be dragged down, response signal is made to be low level, only have after I2C main frame receives last eight bit data, SDA line just can be kept to be high level, and namely response signal is high level.

Therefore only need whether first response signal (showing whether I2C receives the response signal of seven bit address and data direction position from machine) after detecting start signal is low level, namely whether response signal is identical with normal response signal, can judge that whether SDA link is normal, determination methods is simple and convenient.First response signal after start signal is selected to carry out the reason judged, one is that the position of response signal is determined according to start signal, first response signal is selected to carry out judgement more convenient, two is that this response signal only need judge according to level height, do not need to consider data direction position and be whether last bit data of data transmission, judgement is got up fairly simple.

Further, this step 2022 can also comprise: when data direction position, first response signal after start signal, when second response signal after start signal is low level, or when the response signal of second behind data direction position and start signal is high level, first response signal after start signal is low level, when signal after second response signal after start signal is stop signal, or when data direction position is high level, first response signal after start signal and first response signal after start signal are low level, when signal after second response signal after start signal is not stop signal, judge that SDA link is normal, otherwise, judge that SDA link is abnormal.To prevent after start signal first response signal from being become low level signal due to the maloperation of I2C bus, by judging by accident as well by abnormal SDA link, improve the reliability of detection, reduce risk.

Easily know, this step 2022 can also according to the response signal of the 3rd after start signal, the 4th response signal ..., or even last response signal judge SDA link, the present invention is to judging which response signal after start signal, judging that several response signal does not limit, just preferably, the present invention is not restricted to this for first response signal after detection start signal and second response signal.

Step 2023: when detecting that SCL link is normal and SDA link is normal, judge that the link of I2C main frame is normal.

Step 203: when I2C bus busy, whether control master (main equipment) reads data from salve (from equipment) and writes data to salve, normal with the read-write capability detecting I2C main frame.

In the present embodiment, this step 203 performs after step 201, does not have sequencing with step 202.

In the present embodiment, I2C main frame can comprise Controller (controller), master (main equipment), slave (from equipment), clock counter and ACK (Acknowledgement confirms) counter.The execution of controller for the self-inspection of control I2C main frame and the judgement of self-detection result.Master is for control I2C bus and the read-write capability completing I2C main frame, master can also be used for reading preset data from slave, with judge I2C main frame whether read function normal, write preset data to slave, with make slave judge I2C main frame whether write function normal.Clock counter is for realizing the counting of clock signal on SCL line, and ACK counter is for realizing the counting of low level response signal on SDA line.Master is connected with I2C main frame by the link of I2C main frame, and salve, clock counter, ACK counter are connected with master respectively, and Controller is connected with master, salve, clock counter, ACK counter respectively.Wherein, Controller, master, clock counter, ACK counter can be the components and parts in existing I2C main frame, and salve is the device that the embodiment of the present invention increases in I2C main frame.Salve can be from the identical components and parts of machine with I2C, as storer, but salve and I2C is different from machine, and I2C is connected from machine with I2C bus, salve and master connects and also comprises for comparing the whether identical device of data in salve, as comparer, processor etc.

Particularly, this step 203 can comprise: control master reads preset data from salve, when the data that master reads are identical with the preset data in master, judge I2C main frame to read function normal, when the data that master reads are different from the preset data in master, judge I2C main frame to read function abnormal; Control master is by the preset data write salve in master, when the data that master writes in salve are identical with the preset data in salve, judge I2C main frame to write function normal, when the data that master writes in salve are different from the preset data in salve, judgement I2C main frame to write function abnormal.

It should be noted that, preset data is before step 203, is stored in the data in master and salve, and the preset data in master and the preset data in salve are identical.

Step 204: when detecting that the link of I2C main frame is normal and the read-write capability of I2C main frame is normal, judge that I2C main frame can control I2C bus.This step 204 performs after step 202 and step 203.

In a kind of implementation of the present embodiment, the method can also comprise step 205 and step 206.

Step 205: when I2C bus free, control I2C bus, and send preset data bag to I2C from machine.This step 205 performs after step 201.

Preferably, preset data bag can be that a bag takies the few data of I2C bus time, as only included the packet of seven bit address, data direction position and eight bit data.

Alternatively, I2C can be selected arbitrarily from machine, also can preset.

Step 206: when receiving the response signal that I2C sends from machine, judges that I2C main frame can control I2C bus.This step 206 performs after step 205.

Easily know, before step 202, the method can also comprise step: switch to GPIO (GeneralPurposeInput/Output, general input/output port) pattern from I2C pattern.

Correspondingly, after step 202, the method also comprises step: switch to I2C pattern from GPIO pattern.

Wherein, I2C main frame, under GPIO pattern, only detects the level change in I2C bus, does not carry out data processing.

The embodiment of the present invention is by when I2C bus busy, receive the packet that I2C bus is transmitted, and the link of I2C main frame is detected according to this packet, control master reads data from salve and writes data to salve, whether normal with the read-write capability detecting I2C main frame, and then judge that can this I2C main frame control I2C bus, therefore do not need by the time I2C bus free time just can carry out the self-inspection of I2C main frame.The embodiment of the present invention can be carried out in real time, avoid in the process of I2C host waits self-inspection, occur that the I2C main frame of the current control I2C bus existed in prior art breaks down, I2C main frame for subsequent use can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the device of control I2C bus is changed repeatedly.And the link of I2C main frame and read-write capability two aspect of I2C main frame are detected simultaneously, improve the accuracy of testing result.

Embodiment three

Embodiments provide a kind of self checking method of I2C main frame, be improve the one of embodiment two, the method can perform when I2C main frame for subsequent use and I2C bus connect, and see Fig. 5, the method comprises:

Whether step 301:I2C Host Detection I2C bus is busy.When I2C bus free, perform step 302; When I2C bus busy, perform step 303.

Alternatively, this step 301 can be identical with the step 201 in embodiment two, is not described in detail in this.

Step 302: control I2C bus, sends preset data bag to I2C from machine, and according to the response signal whether receiving I2C and send from machine, judges that can I2C main frame control I2C bus.

Alternatively, this step 302 can comprise: when receiving the response signal that I2C sends from machine, judges that I2C main frame can control I2C bus; When not receiving the response signal that I2C sends from machine, judge that I2C main frame can not control I2C bus.

Whether identical with the standard clock signal preset step 303: receive the clock signal on SCL line, detect the clock signal received, and judge that whether SCL link is normal according to the testing result of clock signal.When SCL link is normal, perform step 304; When SCL link is abnormal, perform step 305.

Alternatively, this step 303 can be identical with the step 2021 in embodiment two, is not described in detail in this.

Step 304: receive first response signal after start signal on SDA line, whether identically with the normal response signal preset detect first response signal after start signal, and judge that whether SDA link is normal according to the testing result of the response signal of first after start signal.When SDA link is normal, perform step 306; When SDA link is abnormal, perform step 305.

Alternatively, this step 304 can be identical with the step 2022 in embodiment two, is not described in detail in this.

Step 305: judge that I2C main frame can not control I2C bus.

Step 306: whether control master reads data from salve and writes data to salve, normal with the read-write capability detecting I2C main frame.When the read-write capability of I2C main frame is normal, perform step 307; When the read-write capability of I2C main frame is abnormal, perform step 305.

Alternatively, this step 306 can be identical with the step 203 in embodiment two, is not described in detail in this.

Step 307: judge that I2C main frame can control I2C bus.

Easily know; the progress of I2C main frame self-inspection can be indicated by service marking position Flag; as Flag 000 shows not carry out self-inspection; Flag 001 shows that the self-inspection of SCL link is by (SCL link is normal); Flag 010 shows that the self-inspection of SDA link is by (SDA link is normal); Flag 100 shows that read-write capability self-inspection is by (read-write capability is normal); Flag 111 shows that all self-inspections are by (link normal and read-write capability is normal), and Flag 101 shows self-inspection not by (link is abnormal or read-write capability is abnormal).

The embodiment of the present invention is by when I2C bus busy, receive the packet that I2C bus is transmitted, and the link of I2C main frame is detected according to this packet, control master reads data from salve and writes data to salve, whether normal with the read-write capability detecting I2C main frame, and then judge that can this I2C main frame control I2C bus, therefore do not need by the time I2C bus free time just can carry out the self-inspection of I2C main frame.The embodiment of the present invention can be carried out in real time, avoid in the process of I2C host waits self-inspection, occur that the I2C main frame of the current control I2C bus existed in prior art breaks down, I2C main frame for subsequent use can not replace the I2C host computer control I2C bus of current control I2C bus, and causes the problem that the device of control I2C bus is changed repeatedly.And the link of I2C main frame and read-write capability two aspect of I2C main frame are detected simultaneously, improve the accuracy of testing result.In addition, when the link detecting I2C main frame is abnormal, directly judge that I2C main frame can not judge I2C bus, do not need to continue to detect the read-write capability of I2C main frame, save the time and resource detecting and expend.

Embodiment four

Embodiments provide a kind of self-checking unit of I2C main frame, be applicable to the I2C main frame detected just and I2C bus connects, see Fig. 6, this device comprises:

Bus detection module 401, whether busy for detecting I2C bus;

Link detection module 402, for when I2C bus busy, receives the packet that I2C bus is transmitted, and whether detect the link of I2C main frame according to this packet normal.

Embodiment five

Embodiments provide a kind of self-checking unit of I2C main frame, be applicable to the I2C main frame detected just and I2C bus connects, see Fig. 7, this device comprises:

Bus detection module 501, whether busy for detecting I2C bus;

Whether link detection module 502, for when I2C bus busy being detected, receives the packet that I2C bus is transmitted, and normal according to the link of this packet detection I2C main frame.

Alternatively, bus detection module 501 can comprise:

Whether level detection unit, have level to change within the cycle detecting standard clock signal default on SCL line;

Bus judging unit, for when SCL line has level to change within the cycle of a default standard clock signal, judges I2C bus busy; When SCL line does not have level to change within the cycle of a default standard clock signal, judge I2C bus free.

In actual applications, level detection unit can be clock counter, and bus judging unit can be Controller.

Alternatively, link detection module 502 can comprise:

Whether identical with the standard clock signal preset SCL link detecting unit, for receiving the clock signal on SCL line, detect this clock signal, to judge that whether SCL link is normal;

Whether identical with the normal response signal preset SDA link detecting unit, for receiving first response signal on SDA line after start signal, detect first response signal after start signal, to judge that whether SDA link is normal;

Judging unit, for when SCL link is normal and SDA link is normal, judges that the link of I2C main frame is normal.

Particularly, SCL link detecting unit can comprise:

Sampling subelement, within the sampling time, using the first signal as with reference to signal, samples to clock signal, and records the quantity that sampled result is high level, the frequency of the first signal be the n of standard clock signal frequency doubly, n >=2 and n is integer;

Quantity detection sub-unit, whether the high level quantity for detection record is identical with predetermined quantity, and predetermined quantity is within the sampling time, and using the first signal as reference signal, the sampled result of standard clock signal being carried out to sampling acquisition is the quantity of high level; When detecting that the high level quantity of record is identical with predetermined quantity, judge that SCL link is normal; When detecting that the high level quantity of record is different from predetermined quantity, judge that SCL link is abnormal.

In actual applications, sampling subelement can be clock counter, and quantity detection sub-unit can be Controller.

Particularly, SDA link detecting unit may be used for, and when the response signal of first after start signal is low level, judges that SDA link is normal; When the response signal of first after start signal is high level, judge that SDA link is abnormal.

In actual applications, SDA link detecting unit can be Controller.Judge the response signal after start signal whether as low level, can be completed by ACK counter.

Further, SDA link detecting unit can also be used for, when data direction position, first response signal after start signal, when second response signal after start signal is low level, or when the response signal of second behind data direction position and start signal is high level, first response signal after start signal is low level, when signal after second response signal after start signal is stop signal, or when data direction position is high level, first response signal after start signal and second response signal after start signal are low level, when signal after second response signal after start signal is not stop signal, judge that SDA link is normal, otherwise, judge that SDA link is abnormal.

Preferably, judging unit can also be used for, and when SCL link is abnormal, judges that the link of I2C main frame is abnormal.

In actual applications, judging unit can be Controller.

In a kind of implementation of the present embodiment, this device can also comprise: read-write capability detection module 503, for when I2C bus busy, whether control master reads data from salve and writes data to salve, normal with the read-write capability detecting I2C main frame.

Judge module 504, for when the link of I2C main frame is normal and the read-write capability of I2C main frame is normal, judges that I2C main frame can control I2C bus.

In actual applications, read-write capability detection module 503 and judge module 504 can be Controller.

Alternatively, read-write capability detection module 503 can comprise:

Read comparing unit, from salve, read preset data for control master, when the data that master reads are identical with the preset data in master, judgement I2C main frame to read function normal; When the data that master reads are different from the preset data in master, judge I2C main frame to read function abnormal;

Write comparing unit, for control master by the preset data write salve in master, when the data that master writes in salve are identical with the preset data in salve, judge I2C main frame to write function normal, when writing the data in salve in master and being different from the preset data in salve, judge I2C main frame to write function abnormal.

In actual applications, judge that whether the data that master reads are identical with the preset data in master, can be completed by master, judge that whether the data that master writes in salve are identical with the preset data in salve, can be completed by salve.

Further, judge module 504 can also be used for, and when the link of I2C main frame is abnormal, judges that I2C main frame can not control I2C bus.

In the another kind of implementation of the present embodiment, this device can also comprise: Host Detection module 505, for when I2C bus free, and control I2C bus, and send preset data bag to I2C from machine.

Correspondingly, judge module 504 for, when receiving the response signal that I2C sends from machine, judge that I2C main frame can control I2C bus.

In actual applications, Host Detection module 505 can be master.

In another implementation of the present embodiment, this device can also comprise isolation module, and for when device does not access I2C bus, spacer assembly and I2C bus, can prevent the maloperation of I2C bus.

Embodiment six

Embodiments provide a kind of I2C main frame, see Fig. 8, this I2C main frame 60 generally comprises the parts such as bus interface 61, storer 62 and processor 63.Bus interface 61 comprises the link of I2C main frame, for receiving packet that I2C bus is transmitted or sending packet to I2C bus.This I2C main frame also comprises clock counter 64 and ACK counter 65.Clock counter 64 is for realizing the counting of clock signal on SCL line, and ACK counter 65 is for realizing the counting of low level response signal on SDA line.It will be understood by those skilled in the art that the structure shown in Fig. 8 does not form the restriction to this I2C main frame 60, this I2C main frame 60 can comprise the parts more more or less than diagram, or combines some parts, or different parts are arranged.

Concrete introduction is carried out below in conjunction with Fig. 8 each component parts to I2C main frame 60:

Storer 62 can be used for storing software program and application module, and processor 63 is stored in software program and the application module of storer 62 by running, thus performs various function application and the data processing of I2C main frame 60.Storer 62 mainly can comprise storage program district and store data field, and wherein, storage program district can store operating system, application program needed at least one function (such as detect I2C bus whether busy etc.) etc.; Store data field and can store the data (testing result that such as whether I2C bus is busy) etc. created according to the process of I2C main frame 60.In addition, storer 62 can comprise high-speed RAM (RandomAccessMemory, random access memory), nonvolatile memory (non-volatilememory) can also be comprised, such as at least one disk memory, flush memory device or other volatile solid-state parts.

Whether busy program in processor 63 run memory 62, can be used for detecting I2C bus.

Whether particularly, clock counter 64 can be used for, have level to change in the cycle detecting standard clock signal default on SCL line.

Correspondingly, processor 63 can realize, and when SCL line has level to change within the cycle of a default standard clock signal, judges I2C bus busy; When SCL line does not have level to change within the cycle of a default standard clock signal, judge I2C bus free.

Further, bus interface 61 can be used for, and when I2C bus busy, receives the packet that I2C bus is transmitted.

Correspondingly, processor 63 can realize, and whether the link detecting I2C main frame according to the packet that I2C bus is transmitted is normal.

Particularly, bus interface 61 can be used for, and receives first response signal after start signal on the clock signal on SCL line, SDA line.

Correspondingly, processor 63 can realize, and whether identically with the standard clock signal preset detects clock signal, to judge that whether SCL link is normal; Whether identically with the normal response signal preset detect first response signal after start signal, to judge that whether SDA link is normal; When SCL link is normal and SDA link is normal, judge that the link of I2C main frame is normal.

More specifically, clock counter 64 can be used for, within the sampling time, using the first signal as with reference to signal, clock signal is sampled, and records the quantity that sampled result is high level, the frequency of the first signal be the n of standard clock signal frequency doubly, n >=2 and n is integer.

Correspondingly, processor 63 can realize, and whether the high level quantity of detection record is identical with predetermined quantity, and predetermined quantity is within the sampling time, using the first signal as reference signal, the sampled result of standard clock signal being carried out to sampling acquisition is the quantity of high level; When detecting that the high level quantity of record is identical with predetermined quantity, judge that SCL link is normal; When detecting that the high level quantity of record is different from predetermined quantity, judge that SCL link is abnormal.

More specifically, processor 63 can realize, and when the response signal of first after start signal is low level, judges that SDA link is normal; When the response signal of first after start signal is high level, judge that SDA link is abnormal.

In actual applications, judge the response signal after start signal whether as low level, can be completed by ACK counter 65.

Further, bus interface 61 can be used for, and receives the data direction position on SDA line and second response signal after start signal.

Correspondingly, processor 63 can realize, when data direction position, first response signal after start signal, when second response signal after start signal is low level, or when the response signal of second behind data direction position and start signal is high level, first response signal after start signal is low level, when signal after second response signal after start signal is stop signal, or when data direction position is high level, first response signal after start signal and first response signal after start signal are low level, when signal after second response signal after start signal is not stop signal, judge that SDA link is normal, otherwise, judge that SDA link is abnormal.To prevent after start signal first response signal from being become low level signal due to the maloperation of I2C bus, by judging by accident as well by abnormal SDA link, improve the reliability of detection, reduce risk.

Preferably, processor 63 can also realize, and when SCL link is abnormal, judges that the link of I2C main frame is abnormal.

In a kind of implementation of the present embodiment, I2C main frame comprises multiple storer 62, wherein, has at least a storer 62 to belong to master, has at least a storer 62 to belong to salve.Master also comprises at least one processor, preset data is read from slave for realizing, with judge I2C main frame whether read function normal, preset data is write to slave, with make slave judge I2C main frame whether write function normal, salve also comprises the device (not shown in Fig. 8) for comparing data, as comparer, processor etc.

Processor 63 can realize, and when I2C bus busy being detected, whether control master reads data from salve and writes data to salve, normal with the read-write capability detecting I2C main frame; When the link of I2C main frame is normal and the read-write capability of I2C main frame is normal, judge that I2C main frame can control I2C bus.

Particularly, processor 63 can realize, control master reads preset data from salve, when the data that master reads are identical with the preset data in master, judge I2C main frame to read function normal, when the data that master reads are different from the preset data in master, judge I2C main frame to read function abnormal; Control master is by the preset data write salve in master, when the data that master writes in salve are identical with the preset data in salve, judge I2C main frame to write function normal, when the data that master writes in salve are different from the preset data in salve, judgement I2C main frame to write function abnormal.

Preferably, processor 63 can also realize, and when the link of I2C main frame is abnormal, judges that I2C main frame can not control I2C bus.

In the another kind of implementation of the present embodiment, processor 63 can also realize, when I2C bus free, and control I2C bus, and send preset data bag to I2C from machine.

Correspondingly, processor 63 can realize, and when receiving the response signal that I2C sends from machine, judges that I2C main frame can control I2C bus.

It should be noted that: the self-checking unit of the I2C main frame that above-described embodiment provides is when the self-inspection of I2C main frame, only be illustrated with the division of above-mentioned each functional module, in practical application, can distribute as required and by above-mentioned functions and be completed by different functional modules, inner structure by device is divided into different functional modules, to complete all or part of function described above.In addition, the self checking method of the I2C main frame that above-described embodiment provides and the self-checking unit embodiment of I2C main frame belong to same design, and its specific implementation process refers to embodiment of the method, repeats no more here.

The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.

One of ordinary skill in the art will appreciate that all or part of step realizing above-described embodiment can have been come by hardware, the hardware that also can carry out instruction relevant by program completes, described program can be stored in a kind of computer-readable recording medium, the above-mentioned storage medium mentioned can be ROM (read-only memory), disk or CD etc.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. a self checking method for internal integrated circuit I2C main frame, described I2C main frame is connected with I2C bus by the link of described I2C main frame, it is characterized in that, described method comprises:

Described in described I2C Host Detection, whether I2C bus is busy;

2. method according to claim 1, is characterized in that, the described main equipment of described control, whether normally to detect the read-write capability of described I2C main frame comprising from described from equipment reading data and to described from equipment write data:

3. method according to claim 1 and 2, it is characterized in that, described I2C bus comprises serial time clock line and serial data line, the link of described I2C main frame comprises serial clock link and serial data link, the packet that the described I2C bus of described reception is transmitted, and whether normally to detect the link of described I2C main frame according to described packet, comprising:

4. method according to claim 3, is characterized in that, whether the described clock signal of described detection is identical with the standard clock signal preset, and to judge that whether described serial clock link is normal, comprising:

5. method according to claim 3, is characterized in that, whether first response signal after the described start signal of described detection be identical with the normal response signal preset, and to judge that whether described serial data link is normal, comprising:

6. method according to claim 5, is characterized in that, whether first response signal after the described start signal of described detection be identical with the normal response signal preset, and to judge that whether described serial data link is normal, also comprises:

Otherwise, judge that described serial data link is abnormal.

7. method according to claim 1 and 2, is characterized in that, described method also comprises:

8. a self-checking unit for internal integrated circuit I2C main frame, described I2C main frame is connected with I2C bus by the link of described I2C main frame, it is characterized in that, described device comprises:

Bus detection module, whether busy for detecting described I2C bus;

9. device according to claim 8, is characterized in that, described read-write capability detection module comprises:

10. device according to claim 8 or claim 9, it is characterized in that, described I2C bus comprises serial time clock line and serial data line, and the link of described I2C main frame comprises serial clock link and serial data link, and described link detection module comprises:

11. devices according to claim 10, is characterized in that, described serial clock link detecting unit comprises:

12. devices according to claim 10, is characterized in that, described serial data link detecting unit is used for,

13. devices according to claim 12, is characterized in that, described serial data link detecting unit also for,

Otherwise, judge that described serial data link is abnormal.

14. devices according to claim 8 or claim 9, it is characterized in that, described device also comprises Host Detection module,

Described Host Detection module is used for, during described I2C bus free, and control I2C bus, and send preset data bag to I2C from machine;

Described judge module also for, when receiving the response signal that described I2C sends from machine, judge that described I2C main frame can control described I2C bus.

15. 1 kinds of internal integrated circuit I2C main frames, it is characterized in that, described main frame comprises bus interface and processor, and described processor is used for the self checking method that enforcement of rights requires the I2C main frame described in any one of 1-7.