CN103389707B

CN103389707B - One realizes AISG controller and control method based on ARM and FPGA

Info

Publication number: CN103389707B
Application number: CN201310304274.5A
Authority: CN
Inventors: 罗宝填; 简托
Original assignee: ZHEJIANG THREE-DIMENSIONAL WIRELESS TECHNOLOGY Co Ltd
Current assignee: ZHEJIANG THREE-DIMENSIONAL WIRELESS TECHNOLOGY Co Ltd
Priority date: 2013-07-17
Filing date: 2013-07-17
Publication date: 2015-12-09
Anticipated expiration: 2033-07-17
Also published as: CN103389707A

Abstract

The present invention relates to one and realize AISG controller and control method based on ARM and FPGA, ARM with FPGA is communicated by SPI interface, and ARM is main SPI pattern, and FPGA is from SPI pattern, when needs read and write data, initiatively initiates by ARM; FPGA is docked with outside RS-485 chip by UART_TXD, UART_RXD and UART_CE; ARM is for the treatment of the agreement of AISG data link layer; FPGA is used for the framing of data, separates frame, coding, decodes and realize RS-485 to communicate.The effect that the present invention is useful is: utilize the remaining logical resource of FPGA on wireless base station to realize AISG controller and effectively reduce the cost of system and the programmability of FPGA meets the requirement of system upgrade, can dock with the wireless device of Geng Duo producer.

Description

One realizes AISG controller and control method based on ARM and FPGA

Technical field

The present invention relates to antenna equipment field, is that one realizes AISG controller and control method based on ARM and FPGA.

Background technology

Along with going deep into of 3G and 4G network application, smart antenna adopts electric conditioning technology to become inexorable trend.

In the coverage mode of outdoor base station, GSM, CDMA antenna of 2G and WCDMA, CDMA2000 antenna of 3G are all adopting electrical tilt antenna in a large number.This is due to along with network Development, and wireless environment becomes increasingly complex, more and more higher to the frequency of overall plan of network and optimization, makes the adjustment of antennas orthogonal face angle of declination also more and more frequent.Now adopt electrical tilt antenna greatly to increase work efficiency, reduce cost of labor, avoid human error.The remote control standard of electrical tilt antenna is AISG agreement.In platform in the past, most hdlc controller adopting PowerPC to carry docks electrical tilt antenna.PowerPC degree of integration is high, and need not design complicated peripheral circuit, but the price of PowerPC is higher, power consumption is also larger.The maximum advantage of arm processor is that volume is little, low in energy consumption, cheap, and quite high performance is provided, ARM and FPGA combines, and makes embedded system hardware solution more flexibly, can solve most arm processor on the market and all certainly not show off the problem of hdlc controller.FPGA flexible hardware establishes the powerful software function of transference processor organically to combine, and when design has the system of complicated algorithm and steering logic, ARM and FPGA in conjunction with advantage clearly.

Summary of the invention

The present invention will solve the shortcoming of above-mentioned prior art, provides a kind of and realizes AISG controller and control method based on ARM and FPGA, come electrical tilt antenna Long-distance Control.

The present invention solves the technical scheme that its technical matters adopts: thisly realize AISG controller based on ARM and FPGA, ARM with FPGA is communicated by SPI interface, and ARM is main SPI pattern, and FPGA is from SPI pattern, when needs read and write data, initiatively initiate by ARM; FPGA is docked with outside RS-485 chip by UART_TXD, UART_RXD and UART_CE; ARM, for the treatment of the agreement of AISG data link layer, completes the reception to electrical tilt antenna data link layer information and transmission, produces the CRC check of transmission information and carries out CRC check to the information received; FPGA is used for the framing of data, separates frame, coding, decodes and realize RS-485 to communicate.

FPGA inside contains HDLC_ENCODE, HDLC_DECODE and UART tri-large modules, and wherein UART module is divided into again TX_UART and RX_UART two modules, and UART_CE is the set direction of RS-485, is produced by UART module; FIFO is also had to be used for the storage of data in TX_UART and HDLC_DECODE module.

At sending direction, ARM is sent to FPGA the information that will send by SPI interface, and FPGA, then to send by RS-485 module data framing and coding according to HDLC agreement; At receive direction, the RS-485 module in FPGA receives physical layer data, and then according to HDLC agreement solution frame, decoding, ARM detects in FPGA have data, then receives the data in FPGA.

RS-485 adopts semiduplex pattern, and RS-485 module is defaulted as receiving mode, only when having data to send and not having data receivable, is just switched to sending mode.

FPGA is 2.4576MHz in the clock frequency of process HDLC framing, coding, solution frame, decoding, TX_UART and RX_UART.

This control method realizing AISG controller based on ARM and FPGA, the agreement of ARM process AISG data link layer, complete the reception to electrical tilt antenna data link layer information and transmission, produce the CRC check of transmission information and CRC check is carried out to the information received; FPGA to the framing of data, separate frame, coding, decode and realize RS-485 to communicate; At sending direction, ARM is sent to FPGA the information that will send by SPI interface, and FPGA, then to send by RS-485 module data framing and coding according to HDLC agreement; At receive direction, the RS-485 module in FPGA receives physical layer data, and then according to HDLC agreement solution frame, decoding, ARM detects in FPGA have data, then receives the data in FPGA.

The effect that the present invention is useful is: the present invention is applicable to wireless base station and antenna equipment (ALD), as tower amplifier (TMA) and remote electric tilt the Long-distance Control of (RET) antenna.Utilize the remaining logical resource of FPGA on wireless base station to realize AISG controller and effectively can reduce the cost of system and the programmability of FPGA meets the requirement of system upgrade, can dock with the wireless device of Geng Duo producer.Based on ARM and FPGA realize AISG controller can remote monitoring, more on diagnosis and debugging tower, antenna equipment widely.

Accompanying drawing explanation

Fig. 1 is the interconnected schematic diagram of ARM and FPGA of the present invention

Fig. 2 is FPGA internal module of the present invention and interconnected figure

Fig. 3 is the FSM figure of the inner HDLC framing of FPGA of the present invention and coding

Fig. 4 is the FSM figure that the inner HDLC of FPGA of the present invention separates frame and decoding

Fig. 5 is the interface sequence figure between the inner HDLC module of FPGA of the present invention (comprise framing and conciliate frame) and UART module

Fig. 6 is sequential chart and the ARM receiving data stream journey figure that ARM of the present invention receives FPGA

Fig. 7 is sequential chart and the ARM transmission data flowchart that ARM of the present invention sends data to FPGA

Embodiment

Below in conjunction with accompanying drawing, the invention will be further described:

Fig. 1 is the interconnected schematic diagram of ARM and FPGA of the present invention.Wherein ARM with FPGA is communicated by SPI interface, and ARM is main SPI pattern, and FPGA is from SPI pattern, when needs read and write data, initiatively initiates by ARM.FPGA is docked with outside RS-485 chip by UART_TXD, UART_RXD and UART_CE.

Fig. 2 is FPGA internal module of the present invention and interconnected figure.FPGA inside contains HDLC_ENCODE, HDLC_DECODE and UART tri-large modules, and wherein UART module is divided into again TX_UART and RX_UART two modules, and UART_CE is the set direction of RS-485, is produced by UART module; FIFO is also had to be used for the storage of data in TX_UART and HDLC_DECODE module.

Fig. 3 and Fig. 4 is the FSM figure that the inner HDLC framing of FPGA of the present invention conciliates frame.HDLC frame take 0x7e as frame head, postamble, if there is 0x7d and 0x7e 0x7d, 0x5d and 0x7d, 0x5e replacement in the middle of HDLC frame, prevents the erroneous judgement to frame format.

Fig. 5 is the interface sequence figure that the inner HDLC framing of FPGA of the present invention conciliates between frame module and UART module.When UART module and HDLC framing reconciliation frame module all adopt data_en to be 1, the effective mode of data_in.Data_en and data_in is a 2.4576M clock period effective time.

Fig. 6 is sequential chart and the ARM receiving data stream journey figure that ARM of the present invention receives FPGA.Initiatively initiated by ARM, below describe for ARM receives FPGA composition graphs 6 flow process.

A) judging whether tx_cpu_flag is 0, is namely have data to need to receive;

B) tx_cpu_data_flag=1 is sent;

C) read tx_cpu_data_length, read the length wanting read data frame;

D) tx_cpu_data_en sends a rising edge;

E) tx_cpu_data is read

F) again tx_cpu_data_en is set to 0

G) judge whether to run through according to the data frame length read in c.Run through, namely jump to h; Do not run through, namely circulate d, e, f are until digital independent completes.

H) arranging tx_cpu_data_flag is 0

I) terminate

Fig. 7 is sequential chart and the ARM transmission data flowchart that ARM of the present invention sends data to FPGA.Initiatively initiated by ARM, below for ARM sends data to the flow process description of FPGA composition graphs 7.

A) data length that will send is write to FPGA, rx_cpu_data_length

B) data that will send are write to FPGA, rx_cpu_data

C) rx_cpu_data_en is set to 0 – 1 – 0, allows FPGA receive rising edge and the negative edge of a rx_cpu_data_en

D) transmission has been judged whether.If completed, namely jump to e; Do not complete and namely repeat b and c.

E) rx_cpu_data_length is set to 0

F) terminate.

In addition to the implementation, the present invention can also have other embodiments.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection domain of application claims.

Claims

1. realize an AISG controller based on ARM and FPGA, it is characterized in that: ARM with FPGA is communicated by SPI interface, ARM is main SPI pattern, and FPGA is from SPI pattern, when needs read and write data, initiatively initiates by ARM; FPGA is docked with outside RS-485 chip by UART_TXD, UART_RXD and UART_CE; ARM, for the treatment of the agreement of AISG data link layer, completes the reception to electrical tilt antenna data link layer information and transmission, produces the CRC check of transmission information and carries out CRC check to the information received; FPGA is used for the framing of data, separates frame, coding, decodes and realize RS-485 to communicate.

2. according to claim 1ly realize AISG controller based on ARM and FPGA, it is characterized in that: FPGA inside contains HDLC_ENCODE, HDLC_DECODE and UART tri-large modules, wherein UART module is divided into again TX_UART and RX_UART two modules, UART_CE is the set direction of RS-485, is produced by UART module; FIFO is also had to be used for the storage of data in TX_UART and HDLC_DECODE module.

3. according to claim 1ly realize AISG controller based on ARM and FPGA, it is characterized in that: at sending direction, ARM is sent to FPGA the information that will send by SPI interface, and FPGA, then to send by RS-485 module data framing and coding according to HDLC agreement; At receive direction, the RS-485 module in FPGA receives physical layer data, and then according to HDLC agreement solution frame, decoding, ARM detects in FPGA have data, then receives the data in FPGA.

4. one kind adopts the control method realizing AISG controller based on ARM and FPGA as claimed in claim 1, it is characterized in that: the agreement of ARM process AISG data link layer, complete the reception to electrical tilt antenna data link layer information and transmission, produce the CRC check of transmission information and CRC check is carried out to the information received; FPGA to the framing of data, separate frame, coding, decode and realize RS-485 to communicate; At sending direction, ARM is sent to FPGA the information that will send by SPI interface, and FPGA, then to send by RS-485 module data framing and coding according to HDLC agreement; At receive direction, the RS-485 module in FPGA receives physical layer data, and then according to HDLC agreement solution frame, decoding, ARM detects in FPGA have data, then receives the data in FPGA.

5. the control method realizing AISG controller based on ARM and FPGA according to claim 4, is characterized in that: initiatively initiated by ARM, and it is as follows that ARM receives FPGA flow process:

A) judging whether tx_cpu_flag is 0, is namely have data to need to receive;

B) tx_cpu_data_flag=1 is sent;

C) read tx_cpu_data_length, read the length wanting read data frame;

D) tx_cpu_data_en sends a rising edge;

E) tx_cpu_data is read;

F) again tx_cpu_data_en is set to 0;

G) judge whether to run through according to the data frame length read in c; Run through, namely jump to h; Do not run through, namely circulate d, e, f are until digital independent completes;

H) arranging tx_cpu_data_flag is 0;

I) terminate.

6. the control method realizing AISG controller based on ARM and FPGA according to claim 4, is characterized in that: initiatively initiated by ARM, it is as follows that ARM sends data to FPGA flow process:

A) data length that will send is write to FPGA, rx_cpu_data_length;

B) data that will send are write to FPGA, rx_cpu_data;

C) rx_cpu_data_en is set to 0 – 1 – 0, allows FPGA receive rising edge and the negative edge of a rx_cpu_data_en;

D) transmission has been judged whether; If completed, namely jump to e; Do not complete and namely repeat b and c;

E) rx_cpu_data_length is set to 0;

F) terminate.