CN103389707A - AISG (antenna interface standards group) controller realized on basis of ARM (advanced RISC machine) and FPGA (field programmable gate array) and control method - Google Patents

Abstract

The invention relates to an AISG controller realized on the basis of an ARM and an FPGA and a control method. The ARM and the FPGA communicate through an SPI (serial peripheral interface), the ARM adopts a main SPI mode, the SPGA adopts an auxiliary SPI mode, and data reading and data writing are actively initiated by the ARM when required; the FPGA is in butt joint with an external PS-485 chip through a UART_TXD, a UART_RXD and a UART_CE; the ARM is used for processing a protocol in an AISG data link layer; and the FPGA is used for framing, de-framing, encoding and decoding the data and realizing RS-485 communication. The controller and the control method have the benefits as follows: by the aid of residual logical resources of the FPGA on a wireless base station, the AISG controller can effectively reduce the system cost, the programmability of the FPGA can meet requirements of system upgrade, and the controller can be in butt joint with wireless devices of more manufacturers.

Description

A kind ofly based on ARM and FPGA, realize AISG controller and control method

Technical field

The present invention relates to the antenna equipment field, is a kind ofly based on ARM and FPGA, to realize AISG controller and control method.

Background technology

Along with going deep into of 3G and 4G network application, smart antenna adopts electric conditioning technology to become inexorable trend.

In the coverage mode of outdoor base station, the WCDMA of the GSM of 2G, CDMA antenna and 3G, CDMA2000 antenna are all at a large amount of electrical tilt antennas that adopt.This is due to along with network Development, and wireless environment becomes increasingly complex, and is more and more higher to the frequency of overall plan of network and optimization, makes the adjustment of antenna vertical plane angle of declination also more and more frequent.Adopt electrical tilt antenna greatly to increase work efficiency this moment, reduces cost of labor, avoids human error.The Long-distance Control standard of electrical tilt antenna is the AISG agreement.In platform in the past, most hdlc controllers that adopt PowerPC to carry dock electrical tilt antenna.The PowerPC degree of integration is high, need not design complicated peripheral circuit, but the price of PowerPC is higher, and power consumption is also larger.The advantage of arm processor maximum is that volume is little, low in energy consumption, cheap, and provide quite high performance, ARM and FPGA combination, make embedded system hardware solution more flexibly, can solve most arm processors on the market and all certainly not show off the problem of hdlc controller.The powerful software function that the flexible hardware of FPGA is established the transference processor organically combines, and when design had the system of complicated algorithm and steering logic, ARM and FPGA were very obvious in conjunction with advantage.

Summary of the invention

The present invention will solve the shortcoming of above-mentioned prior art, provides a kind of and realizes AISG controller and control method based on ARM and FPGA, completes the electrical tilt antenna Long-distance Control.

The present invention solves the technical scheme that its technical matters adopts: thisly based on ARM and FPGA, realize the AISG controller, ARM and FPGA communicate by the SPI interface, and ARM is main SPI pattern, and FPGA is from the SPI pattern, when needs read with data writing, by ARM, initiatively initiate; FPGA docks with outside RS-485 chip by UART_TXD, UART_RXD and UART_CE; ARM, for the treatment of the agreement of AISG data link layer, completes reception and transmission to electrical tilt antenna data link layer information, produces the CRC check of transmission information and the information that receives is carried out CRC check; FPGA be used for to data framing, separate frame, coding, decode and realize that RS-485 communicates by letter.

FPGA inside has comprised HDLC_ENCODE, HDLC_DECODE and three large modules of UART, and wherein the UART module is divided into again TX_UART and two modules of RX_UART, and UART_CE is the set direction of RS-485, by the UART module, is produced; Also have FIFO to be used for the storage of data in TX_UART and HDLC_DECODE module.

At sending direction, ARM crosses the SPI interface to the information exchange that will send and sends to FPGA, and FPGA, then sends with the RS-485 module data framing and coding according to the HDLC agreement; At receive direction, the RS-485 module in FPGA receives physical layer data, and then according to HDLC agreement solution frame, decoding, ARM detects in FPGA data, then receives the data in FPGA.

RS-485 adopts semiduplex pattern, and the RS-485 module is defaulted as receiving mode, is only having data will send and not have just to be switched to sending mode in the receivable situation of data.

FPGA is 2.4576MHz in the clock frequency of processing HDLC framing, coding, solution frame, decoding, TX_UART and RX_UART.

This control method that realizes the AISG controller based on ARM and FPGA, ARM processes the agreement of AISG data link layer, complete reception and transmission to electrical tilt antenna data link layer information, produce the CRC check of transmission information and the information that receives is carried out CRC check; FPGA to the framing of data, separate frame, coding, decode and realize that RS-485 communicates by letter; At sending direction, ARM crosses the SPI interface to the information exchange that will send and sends to FPGA, and FPGA, then sends with the RS-485 module data framing and coding according to the HDLC agreement; At receive direction, the RS-485 module in FPGA receives physical layer data, and then according to HDLC agreement solution frame, decoding, ARM detects in FPGA data, then receives the data in FPGA.

The effect that the present invention is useful is: the present invention is applicable to wireless base station and antenna equipment (ALD), as the Long-distance Control of tower amplifier (TMA) and remote electric inclination (RET) antenna.The programmability of utilizing the remaining logical resource of FPGA on wireless base station to realize that the AISG controller can effectively reduce the cost of system and FPGA meets the requirement of system upgrade, can dock with the wireless device of more producers.Based on ARM and FPGA realize the AISG controller can remote monitoring, more on diagnosis and debugging tower, antenna equipment widely.

Description of drawings

Fig. 1 is the interconnected schematic diagram of ARM of the present invention and FPGA

Fig. 2 is FPGA internal module of the present invention and interconnected figure

Fig. 3 is the FSM figure of the inner HDLC framing of FPGA of the present invention and coding

Fig. 4 is the FSM figure that the inner HDLC of FPGA of the present invention separates frame and decoding

Fig. 5 is the interface sequence figure between the inner HDLC module of FPGA of the present invention (comprising framing reconciliation frame) and UART module

Fig. 6 is sequential chart and the ARM receiving data stream journey figure that ARM of the present invention receives FPGA

Fig. 7 is sequential chart and the ARM transmission data flowchart that ARM of the present invention sends data to FPGA

Embodiment

The invention will be further described below in conjunction with accompanying drawing:

Fig. 1 is ARM of the present invention and the interconnected schematic diagram of FPGA.Wherein ARM and FPGA communicate by the SPI interface, and ARM is main SPI pattern, and FPGA is from the SPI pattern, when needs read with data writing, by ARM, initiatively initiates.FPGA docks with outside RS-485 chip by UART_TXD, UART_RXD and UART_CE.

Fig. 2 is FPGA internal module of the present invention and interconnected figure.FPGA inside has comprised HDLC_ENCODE, HDLC_DECODE and three large modules of UART, and wherein the UART module is divided into again TX_UART and two modules of RX_UART, and UART_CE is the set direction of RS-485, by the UART module, is produced; Also have FIFO to be used for the storage of data in TX_UART and HDLC_DECODE module.

Fig. 3 and Fig. 4 are the FSM figure that the inner HDLC framing of FPGA of the present invention is conciliate frame.The HDLC frame take 0x7e as frame head, postamble, if occur in the middle of the HDLC frame that 0x7d and 0x7e replace with 0x7d, 0x5d and 0x7d, 0x5e, prevent the erroneous judgement to frame format.

Fig. 5 is that the inner HDLC framing of FPGA of the present invention is conciliate the interface sequence figure between frame module and UART module.It is 1 o'clock that UART module and HDLC framing reconciliation frame module all adopt data_en, the effective mode of data_in.Data_en and data_in are a 2.4576M clock period effective time.

Fig. 6 is sequential chart and the ARM receiving data stream journey figure that ARM of the present invention receives FPGA.Initiatively initiated by ARM, below for ARM receives FPGA, in conjunction with Fig. 6 flow process, describe.

A) judging whether tx_cpu_flag is 0, is namely to have data to need to receive;

B) send tx_cpu_data_flag=1;

C) read tx_cpu_data_length, read the length of wanting read data frame;

D) tx_cpu_data_en sends a rising edge;

E) read tx_cpu_data

F) tx_cpu_data_en is set to 0 again

G) judge whether to run through according to the Frame length that reads in c.Run through, namely jump to h; Do not run through, the d that namely circulates, e, f until data read.

H) tx_cpu_data_flag being set is 0

I) finish

Fig. 7 is sequential chart and the ARM transmission data flowchart that ARM of the present invention sends data to FPGA.Initiatively initiated by ARM, below for ARM sends data to FPGA, in conjunction with the flow process of Fig. 7, describe.

A) write the data length that will send, rx_cpu_data_length to FPGA

B) write the data that will send, rx_cpu_data to FPGA

C) rx_cpu_data_en is set to 0 – 1 – 0, allows FPGA receive rising edge and the negative edge of a rx_cpu_data_en

D) judged whether transmission., if complete, namely jump to e; Do not complete and namely repeat b and c.

E) rx_cpu_data_length is set to 0

F) finish.

In addition to the implementation, the present invention can also have other embodiments.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection domain of requirement of the present invention.

Claims (6)

1. realize the AISG controller based on ARM and FPGA for one kind, it is characterized in that: ARM and FPGA communicate by the SPI interface, and ARM is main SPI pattern, and FPGA is from the SPI pattern, when needs read with data writing, by ARM, initiatively initiates; FPGA docks with outside RS-485 chip by UART_TXD, UART_RXD and UART_CE; ARM, for the treatment of the agreement of AISG data link layer, completes reception and transmission to electrical tilt antenna data link layer information, produces the CRC check of transmission information and the information that receives is carried out CRC check; FPGA be used for to data framing, separate frame, coding, decode and realize that RS-485 communicates by letter.

2. according to claim 1ly based on ARM and FPGA, realize the AISG controller, it is characterized in that: FPGA inside has comprised HDLC_ENCODE, HDLC_DECODE and three large modules of UART, wherein the UART module is divided into again TX_UART and two modules of RX_UART, UART_CE is the set direction of RS-485, by the UART module, is produced; Also have FIFO to be used for the storage of data in TX_UART and HDLC_DECODE module.

3. according to claim 1ly based on ARM and FPGA, realize the AISG controller, it is characterized in that: at sending direction, ARM crosses the SPI interface to the information exchange that will send and sends to FPGA, and FPGA, then sends with the RS-485 module data framing and coding according to the HDLC agreement; At receive direction, the RS-485 module in FPGA receives physical layer data, and then according to HDLC agreement solution frame, decoding, ARM detects in FPGA data, then receives the data in FPGA.

4. one kind is adopted the control method that realizes the AISG controller based on ARM and FPGA as claimed in claim 1, it is characterized in that: ARM processes the agreement of AISG data link layer, complete reception and transmission to electrical tilt antenna data link layer information, produce the CRC check of transmission information and the information that receives is carried out CRC check; FPGA to the framing of data, separate frame, coding, decode and realize that RS-485 communicates by letter; At sending direction, ARM crosses the SPI interface to the information exchange that will send and sends to FPGA, and FPGA, then sends with the RS-485 module data framing and coding according to the HDLC agreement; At receive direction, the RS-485 module in FPGA receives physical layer data, and then according to HDLC agreement solution frame, decoding, ARM detects in FPGA data, then receives the data in FPGA.

5. the control method that realizes the AISG controller based on ARM and FPGA according to claim 4, it is characterized in that: initiatively initiated by ARM, it is as follows that ARM receives the FPGA flow process:

A) judging whether tx_cpu_flag is 0, is namely to have data to need to receive;

B) send tx_cpu_data_flag=1;

C) read tx_cpu_data_length, read the length of wanting read data frame;

D) tx_cpu_data_en sends a rising edge;

E) read tx_cpu_data;

F) tx_cpu_data_en is set to 0 again;

G) judge whether to run through according to the Frame length that reads in c; Run through, namely jump to h; Do not run through, the d that namely circulates, e, f until data read;

H) tx_cpu_data_flag being set is 0;

I) finish.

6. the control method that realizes the AISG controller based on ARM and FPGA according to claim 4, it is characterized in that: initiatively initiated by ARM, it is as follows that ARM sends data to the FPGA flow process:

A) write the data length that will send, rx_cpu_data_length to FPGA;

B) write the data that will send, rx_cpu_data to FPGA;

C) rx_cpu_data_en is set to 0 – 1 – 0, allows FPGA receive rising edge and the negative edge of a rx_cpu_data_en;

D) judged whether transmission; , if complete, namely jump to e; Do not complete and namely repeat b and c;

E) rx_cpu_data_length is set to 0;

F) finish.

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