CN103176916B - The address conversion method of flash memory and flash memory - Google Patents
The address conversion method of flash memory and flash memory Download PDFInfo
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- CN103176916B CN103176916B CN201310071967.4A CN201310071967A CN103176916B CN 103176916 B CN103176916 B CN 103176916B CN 201310071967 A CN201310071967 A CN 201310071967A CN 103176916 B CN103176916 B CN 103176916B
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Abstract
A kind of flash memory, communicate to connect with SRAM, be made up of physical block, wherein physical block is made up of multiple Physical Page, logical page (LPAGE) and Physical Page one_to_one corresponding, second level mapping table and third level mapping table is comprised in Physical Page, multiple physical block forms a superblock, also comprise: acquisition module, logging modle, set up module, judge module and output module, the present invention sets up first order mapping table by utilizing superblock allocation table on SRAM, and judge second level mapping table, the buffer memory of third level mapping table and superblock allocation table obtains the address of Physical Page, SRAM sets up according to the first order mapping table buffer memory of second level mapping table, the buffer memory of third level mapping table is set up according to the buffer memory of second level mapping table, and according to the buffer memory of second level mapping table, the buffer memory of third level mapping table and the buffer memory of superblock allocation table combine the block number obtaining described physical block, to obtain described logical page (LPAGE) physically, effectively raise the efficiency of address conversion.
Description
Technical field
The present invention relates to computing machine and electronic information technical field, particularly relate to the address conversion method of a kind of flash memory and flash memory.
Background technology
Flash memory, NANDFlash has non-volatile, low in energy consumption, the feature such as performance is high and anti-seismic performance is strong, has a wide range of applications.NANDflash has following characteristics: 1), read-write least unit be page; 2), wiping least unit is block; 3), can not make carbon copies, first must wipe and write afterwards; 4), the block that has can become bad block when dispatching from the factory or in use procedure, can not continue to use.The page of NAND has main (main) district and (spare) for subsequent use district to form, and user data is deposited in primary area, and ECC error correcting code, part mapping information and other management information etc. are generally deposited in spare area.
Flash translation layer (FTL) (FTL) is responsible for the mapping of logical address to physical address, and the information such as bad block management, are abstracted into a calibrated bolck equipment by NAND, to hiding host NAND bottom-up information.The mapping mode of flash memory is generally divided into block mapping, page maps and mixed-use developments three kinds.Block mapping pair memory source takies few, but efficiency is low; Page mapping efficiency is high, but large to internal memory resource occupation; Mixed-use developments does according to demand between both compromises.
Application number be 201010133944.8 Chinese invention patent application " address conversion method of flash storage FTL " propose a kind of three grades map principles, but do not indicate in practice, how mapping table at different levels stores and builds, and efficiency is low.
Summary of the invention
In view of this, the address conversion method that a kind of flash memory and flash memory are provided is necessary.
Flash memory provided by the invention, flash memory and SRAM communicate to connect, be made up of physical block, wherein said physical block is made up of multiple Physical Page, logical page (LPAGE) and Physical Page one_to_one corresponding, second level mapping table and third level mapping table is comprised in described Physical Page, described multiple physical block forms a superblock, also comprise: acquisition module, logging modle, set up module, judge module and output module, wherein: acquisition module is used for logical page (LPAGE) to be divided into three sections, respectively corresponding superblock block number, group number and group bias internal; The physical block block number that logging modle is used for each superblock to comprise is recorded in superblock allocation table; Set up module for setting up first order mapping table in sram according to described superblock allocation table, and using described superblock block number as the index of described first order mapping table; Judge module is used for judging whether described second level mapping table is hit at the buffer memory of SRAM by described superblock block number, and judge whether described third level mapping table at the buffer memory of SRAM be hit when the buffer memory of SRAM is hit by described group number at described second level mapping table, judge when the buffer memory of SRAM is hit whether described superblock allocation table is hit at the buffer memory of SRAM at described third level mapping table; Output module, for combining the block number that obtain described physical block, to obtain the physical address of described logical page (LPAGE) when the buffer memory of SRAM is hit according to the buffer memory of the buffer memory of described second level mapping table, described third level mapping table and the buffer memory of described superblock allocation table at described superblock allocation table.
The address conversion method of flash memory provided by the invention, wherein, flash memory and SRAM communicate to connect, be made up of physical block, wherein said physical block is made up of multiple Physical Page, logical page (LPAGE) and Physical Page one_to_one corresponding, second level mapping table and third level mapping table is comprised in described Physical Page, described multiple physical block forms a superblock, said method comprising the steps of: logical page (LPAGE) is divided into three sections, respectively corresponding superblock block number, group number and group bias internal; The physical block block number distributed by each superblock is recorded in superblock allocation table; First order mapping table is set up in sram according to described superblock allocation table, and using described superblock block number as the index of described first order mapping table; Judge whether described second level mapping table is hit at the buffer memory of SRAM by described superblock block number; If so, then judge whether described third level mapping table is hit at the buffer memory of SRAM by described group number; If so, then judge whether described superblock allocation table is hit at the buffer memory of SRAM; If so, then the block number obtaining described physical block is combined, to obtain the physical address of described logical page (LPAGE) according to the buffer memory of the buffer memory of described second level mapping table, the buffer memory of described third level mapping table and described superblock allocation table.
The address conversion method of flash memory provided by the invention and flash memory, on SRAM, first order mapping table is set up by utilizing superblock allocation table, and on SRAM, the buffer memory of second level mapping table is set up according to first order mapping table, the buffer memory of third level mapping table is set up according to the buffer memory of second level mapping table, and combine according to the buffer memory of the buffer memory of second level mapping table, the buffer memory of third level mapping table and superblock allocation table the block number obtaining described physical block, to obtain described logical page (LPAGE) physically, effectively raise the efficiency of address conversion.
Accompanying drawing explanation
Fig. 1 is the graph of a relation of logical block, physical block, logical page (LPAGE) and Physical Page in an embodiment of the present invention;
Fig. 2 is the structural drawing of an embodiment of the present invention logical page (LPAGE);
Fig. 3 is the structural drawing of an embodiment of the present invention Physical Page;
Fig. 4 is the module map of flash memory in an embodiment of the present invention;
Fig. 5 is the structural drawing of superblock allocation table in an embodiment of the present invention;
Fig. 6 is the process flow diagram of the address conversion method of flash memory in an embodiment of the present invention;
Fig. 7 is the particular flow sheet of step S20 in process flow diagram shown in Fig. 6.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Being exemplary below by the embodiment be described with reference to the drawings, only for explaining the present invention, and can not limitation of the present invention being interpreted as.
In describing the invention, term " interior ", " outward ", " longitudinal direction ", " transverse direction ", " on ", D score, " top ", the orientation of the instruction such as " end " or position relationship be based on orientation shown in the drawings or position relationship, be only the present invention for convenience of description instead of require that the present invention with specific azimuth configuration and operation, therefore must can not be interpreted as limitation of the present invention.
Refer to Fig. 1, Figure 1 shows that the graph of a relation of logical block in an embodiment of the present invention, physical block, logical page (LPAGE) and Physical Page.
In the present embodiment, flash memory and SRAM(scheme not show) communicate to connect, be made up of physical block, wherein said physical block is made up of multiple Physical Page, logical page (LPAGE) and Physical Page one_to_one corresponding, comprise second level mapping table and third level mapping table in described Physical Page, described multiple physical block forms a superblock, and physical block is made up of multiple Physical Page.In the present embodiment, flash memory has 8 physical blocks, and each physical block has 8 Physical Page, and a total 8x8=64 Physical Page, if a physical page size is 8KB, so the capacity of physical block is 64x8=512KB.The operable Spatial General 6 R of main frame is less than this value, such as 256KB (this is divided by deviser oneself completely), be equivalent to the useful space (4*6=32 Physical Page) only having 4 physical blocks, superblock is logical concept, and superblock is generally greater than physical block, if the size of superblock is the size of 2 physical blocks, so main frame thinks that one has 4/2=2 superblock, each superblock has 8*2=16 logical page (LPAGE), and be also just 32 logical page (LPAGE)s altogether, logical page (LPAGE) is equal with physical page size.
Logical page (LPAGE), superblock are logical addresses, the address of namely main frame use; Physical Page, physical block are physical addresss, refer to the address on NAND.
Logical page (LPAGE) 0 ~ 15 belongs to superblock 0, logical page (LPAGE) 16 ~ 31 belongs to superblock 1(and divides in order), what provide when main frame reads and writes data is logical address, it is indifferent to data and specifically leaves physical address on NAND in, when such as logical page (LPAGE) 0 read by main frame, logical page (LPAGE) 0 just belongs to superblock 0, so by three grades of mapping relations, this logical page (LPAGE) 0 of final discovery is stored on the Physical Page 1 of the physical block 3 of NAND, so reads this page and just obtains data.
Refer to Fig. 2, Fig. 2 is the structural drawing of an embodiment of the present invention logical page (LPAGE).
In the present embodiment, logical page (LPAGE) comprises superblock block number, group number and group bias internal three part.
Refer to Fig. 3, Fig. 3 is the structural drawing of an embodiment of the present invention Physical Page.
In the present embodiment, the content of Physical Page comprises user data, second level mapping table, third level mapping table and other guide.
In the present embodiment, second level mapping table and third level mapping table disperse to be stored in multiple Physical Page.
Refer to Fig. 4, Fig. 4 is the module map of flash memory 10.
In the present embodiment, flash memory 10 comprises acquisition module 102, logging modle 104, sets up module 106, judge module 108, output module 110, memory module 112 and processor 114, wherein, memory module 112 for storing acquisition module 102, logging modle 104, set up module 106, judge module 108 and output module 110, processor 114 is for performing each functional module in memory module 112.
In the present embodiment, flash memory 10 and SRAM(scheme not show) communicate to connect, be made up of physical block, wherein said physical block is made up of multiple Physical Page, logical page (LPAGE) and Physical Page one_to_one corresponding, second level mapping table and third level mapping table is comprised in described Physical Page, described multiple physical block forms a superblock, logical page (LPAGE) and Physical Page one_to_one corresponding, second level mapping table and third level mapping table is comprised in described Physical Page, described multiple Physical Page forms a physical block, and described multiple physical block forms a superblock.
In the present embodiment, in the fixed-size situation of superblock, divide into groups less, second level mapping table is less, and third level mapping table is larger.
In the present embodiment, acquisition module 102 for logical page (LPAGE) is divided into three sections, respectively corresponding superblock block number, group number and group bias internal.In the present embodiment, group number be used for index second level mapping table (also known as group mapping table), group bias internal be used for index third level mapping table (also known as group in mapping table).
Logging modle 104 is recorded in superblock allocation table for the block number of the physical block comprised by each superblock.In the present embodiment, superblock allocation table is stored in the specific physical block of flash memory 10, and specific physical block is stored on other non-volatile memory devices (as NORFlash).
Refer to Fig. 5, Figure 5 shows that the structural drawing of superblock allocation table.
In the present embodiment, Physical Page comprises effectively (invalid) page, invalid (valid) page and sky (empty) page.
In the present embodiment, superblock allocation table is stored in specific piece of flash memory, may need to take multiple page, when super allocation table upgrades, is written in next blank page.
Please continue to refer to Fig. 4, set up module 106 for setting up first order mapping table in sram according to described superblock allocation table, and using described superblock block number as the index of described first order mapping table.
In the present embodiment, described module 106 of setting up comprises acquisition submodule 1062, searches submodule 1064, reading submodule 1066 and judge submodule 1068.
In the present embodiment, submodule 1062 is obtained for obtaining the block number of the physical block of described superblock allocation table on flash memory.
Search submodule 1064 for the Physical Page page number by utilizing binary chop to search last write on described physical block.
Reading submodule 1066 is for reading described up-to-date superblock allocation table, and record corresponding Physical Page page number, wherein, described submodule 1064 of searching also obtains for inquiring about described superblock allocation table the physical block block number that each superblock finally writes, and the page number of last write on the physical block utilizing binary chop to search described last write.
Judge that submodule 1068 is for determining whether last superblock, if be last superblock, then described first order mapping table completes foundation.
Described search submodule 1064 also at described superblock if not last superblock, then continue the block number of the described superblock allocation table of the inquiry physical block that finds next superblock finally to write.
Please continue to refer to Fig. 4, by described superblock block number, judge module 108 is for judging whether described second level mapping table is hit at the buffer memory of SRAM, and judge whether described third level mapping table at the buffer memory of SRAM be hit when the buffer memory of SRAM is hit by described group number at described second level mapping table, judge when the buffer memory of SRAM is hit whether described superblock allocation table is hit at the buffer memory of SRAM at described third level mapping table.
In the present embodiment, the buffer memory in SRAM maintains the buffer memory of a small amount of third level mapping table and the buffer memory of as far as possible many second level mapping tables, like this, makes flash memory 10 have optimum order readwrite performance and random read-write performance.
In the present embodiment, the buffer memory of second level mapping table and third level mapping table comprises block inquiry code, the page number of Physical Page and cache tag.Block inquiry code is the block number obtaining physical block in order to inquire about superblock allocation table.Because the physical block of flash memory 10 is a lot, and the physical block number that each superblock drops on is limited.Such as, a superblock can be written at most (this can be defined by deviser oneself) on 4 physical blocks, and so block inquiry code only needs 2bit just passable, effective use of saving space, flash memory Physical Page spare area.
Output module 110 is for combining the block number that obtain described physical block, to obtain the physical address of described logical page (LPAGE) when the buffer memory of SRAM is hit according to the buffer memory of the buffer memory of described second level mapping table, described third level mapping table and the buffer memory of described superblock allocation table at described superblock allocation table.
Concrete, in the present embodiment, output module 110 is according to second level mapping table buffer memory, third level mapping table buffer memory and superblock allocation table buffer memory are combined and are obtained physical block number, page number in physical block is obtained according to second level mapping table buffer memory and third level mapping table buffer memory, obtain the physical address of a logical page (LPAGE) thus, the physical page number namely in physical address and physical block block number and physical block.
In the present embodiment, describedly set up module 106 also for when described second level mapping table is not hit at the buffer memory of SRAM, by the described superblock block number described first order mapping table of inquiry, and set up the buffer memory of second level mapping table at SRAM according to described first order mapping table.
In the present embodiment, describedly set up module 106 also for when described third level mapping table is not hit at the buffer memory of SRAM, inquired about the buffer memory of described second level mapping table by described group number, and be buffered according to the described second level mapping table buffer memory that SRAM sets up third level mapping table.
In the present embodiment, describedly set up module 106 also for when described superblock allocation table is not hit at the buffer memory of SRAM, described superblock allocation table is write back, and replaces the buffer memory of described superblock allocation table.
Refer to Fig. 6, Figure 6 shows that the process flow diagram of the address conversion method of flash memory 10 in an embodiment of the present invention.
In the present embodiment, flash memory 10 and SRAM(scheme not show) communicate to connect, be made up of physical block, wherein said physical block is made up of multiple Physical Page, logical page (LPAGE) and Physical Page one_to_one corresponding, comprise second level mapping table and third level mapping table in described Physical Page, described multiple physical block forms a superblock, said method comprising the steps of:
In step S00, logical page (LPAGE) is divided into three sections by acquisition module 102, respectively corresponding superblock block number, group number and group bias internal.In the present embodiment, group number be used for index second level mapping table (also known as group mapping table), group bias internal be used for index third level mapping table (also known as group in mapping table).
In step S10, the physical block block number that each superblock distributes by logging modle 104 is recorded in superblock allocation table.
In step S20, set up module 106 and set up first order mapping table in sram according to described superblock allocation table, and using described superblock block number as the index of described first order mapping table.
In step S30, by described superblock block number, judge module 108 judges whether described second level mapping table is hit at the buffer memory of SRAM.
In the present embodiment, the buffer memory of second level mapping table and third level mapping table comprises block inquiry code, the page number of Physical Page and cache tag.
In the present embodiment, block inquiry code is the block number obtaining physical block in order to inquire about superblock allocation table.Because the physical block of flash memory 10 is a lot, and the physical block number that each superblock drops on is limited.Such as, a superblock can be written at most (this can be defined by deviser oneself) on 4 physical blocks, and so block inquiry code only needs 2bit just passable, effective use of saving space, flash memory Physical Page spare area.
If described second level mapping table is hit at the buffer memory of SRAM, then in step S40, by described group number, judge module 108 judges whether described third level mapping table is hit at the buffer memory of SRAM;
If described third level mapping table is hit at the buffer memory of SRAM, then in step S50, judge module 108 judges whether described superblock allocation table is hit at the buffer memory of SRAM.
If described superblock allocation table is hit at the buffer memory of SRAM, then in step S60, output module 110 follows the buffer memory according to the buffer memory of described second level mapping table, the buffer memory of described third level mapping table and described superblock allocation table to combine the block number obtaining described physical block, to obtain the physical address of described logical page (LPAGE).In the present embodiment, output module 110 is according to second level mapping table buffer memory, third level mapping table buffer memory and superblock allocation table buffer memory are combined and are obtained physical block number, page number in physical block is obtained according to second level mapping table buffer memory and third level mapping table buffer memory, obtain the physical address of a logical page (LPAGE) thus, the physical page number namely in physical address and physical block block number and physical block.
If described second level mapping table is not hit at the buffer memory of SRAM, then in step S70, set up module 106 by the described superblock block number described first order mapping table of inquiry, and set up the buffer memory of second level mapping table according to described first order mapping table at SRAM.
If described third level mapping table is not hit at the buffer memory of SRAM, then in step S80, set up module 106 inquires about described second level mapping table buffer memory by described group number, and be buffered according to the described second level mapping table buffer memory that SRAM sets up third level mapping table.
If described superblock allocation table is not hit at the buffer memory of SRAM, then in step S90, set up module 106 and described superblock allocation table is write back, and replace the buffer memory of described superblock allocation table.
Refer to Fig. 7, Figure 7 shows that the particular flow sheet of S20 in Fig. 6.
In the present embodiment, step S20 comprises the following steps:
In step S202, obtain the block number that submodule 1062 obtains the physical block of described superblock allocation table on flash memory.
In step S204, search submodule 1064 and utilize binary chop to search the Physical Page page number of last write on described physical block.
In step S206, reading submodule 1066 reads up-to-date superblock allocation table, and records corresponding Physical Page page number.In the present embodiment, reading submodule 1066 reads the Physical Page of last write, and back reads each Physical Page, until all read by up-to-date superblock allocation table, and writes down corresponding physical page number and the corresponding relation of superblock allocation table
In step S208, search submodule 1064 and inquire about described superblock allocation table and obtain the physical block block number that each superblock finally writes.
In step S210, search submodule 1066 and utilize binary chop to search the page number that the physical block of described last write finally writes.
In step S212, judge that submodule 1068 judges whether described superblock is last superblock.
If described superblock is last superblock, then in step S214, set up the foundation that module 106 completes described first order mapping table.
If described superblock is not last superblock, then continue to return step S208, search the block number that submodule 1064 inquires about the physical block that described superblock allocation table finds next superblock finally to write.
The address conversion method of flash memory 10 provided by the invention and flash memory, on SRAM, first order mapping table is set up by utilizing superblock allocation table, and on SRAM, the buffer memory of second level mapping table is set up according to first order mapping table, the buffer memory of third level mapping table is set up according to the buffer memory of second level mapping table, and follow the buffer memory according to the buffer memory of described second level mapping table, the buffer memory of described third level mapping table and described superblock allocation table to combine the block number obtaining described physical block, to obtain the physical address of described logical page (LPAGE), effectively raise the efficiency of address conversion.
Although the present invention is described with reference to current better embodiment; but those skilled in the art will be understood that; above-mentioned better embodiment is only used for the present invention is described; not be used for limiting protection scope of the present invention; any within the spirit and principles in the present invention scope; any modification of doing, equivalence replacement, improvement etc., all should be included within the scope of the present invention.
Claims (10)
1. a flash memory, communicate to connect with SRAM, be made up of physical block, wherein said physical block is made up of multiple Physical Page, logical page (LPAGE) and Physical Page one_to_one corresponding, comprise second level mapping table and third level mapping table in described Physical Page, the buffer memory in SRAM maintains the buffer memory of a small amount of third level mapping table and the buffer memory of as far as possible many second level mapping tables, described multiple physical block forms a superblock, also comprises:
Acquisition module, for each logical page (LPAGE) is divided into three sections, respectively corresponding superblock block number, group number and group bias internal;
Logging modle, the physical block block number for being comprised by each superblock is recorded in superblock allocation table;
Set up module, for setting up first order mapping table in sram according to described superblock allocation table, and using described superblock block number as the index of described first order mapping table;
Judge module, for judging whether described second level mapping table is hit at the buffer memory of SRAM by described superblock block number, and judge whether described third level mapping table at the buffer memory of SRAM be hit when the buffer memory of SRAM is hit by described group number at described second level mapping table, judge when the buffer memory of SRAM is hit whether described superblock allocation table is hit at the buffer memory of SRAM at described third level mapping table;
Output module, for combining the block number that obtain described physical block, to obtain the physical address of described logical page (LPAGE) when the buffer memory of SRAM is hit according to the buffer memory of the buffer memory of described second level mapping table, described third level mapping table and the buffer memory of described superblock allocation table at described superblock allocation table;
Wherein, described module of setting up comprises:
Obtain submodule, for obtaining the block number of the physical block of described superblock allocation table on flash memory;
Search submodule, for the Physical Page page number utilizing binary chop to search last write on described physical block;
Reading submodule, for reading up-to-date superblock allocation table, and record corresponding Physical Page page number, wherein, described submodule of searching also obtains for inquiring about described up-to-date superblock allocation table the physical block block number that each superblock finally writes, and the page number of last write on the physical block utilizing binary chop to search described last write;
Judge submodule, for determining whether last superblock, if last superblock, then described first order mapping table completes foundation.
2. flash memory as claimed in claim 1, it is characterized in that, described set up module also for described second level mapping table when the buffer memory of SRAM is not hit by the described first order mapping table of described superblock block number inquiry, and set up the buffer memory of second level mapping table at SRAM according to described first order mapping table.
3. flash memory as claimed in claim 1, it is characterized in that, describedly set up module also for being inquired about the buffer memory of described second level mapping table by described group number when the buffer memory of SRAM is not hit at described third level mapping table, and be buffered according to the described second level mapping table buffer memory that SRAM sets up third level mapping table.
4. flash memory as claimed in claim 1, is characterized in that, describedly sets up module also for being write back by described superblock allocation table when the buffer memory of SRAM is not hit at described superblock allocation table, and replaces the buffer memory of described superblock allocation table.
5. flash memory as claimed in claim 1, is characterized in that, described in search submodule also for when described superblock is not last superblock, continue the block number of the physical block that the described superblock allocation table of inquiry finds next superblock finally to write.
6. the address conversion method of a flash memory, wherein, flash memory and SRAM communicate to connect, be made up of physical block, wherein said physical block is made up of multiple Physical Page, logical page (LPAGE) and Physical Page one_to_one corresponding, second level mapping table and third level mapping table is comprised in described Physical Page, buffer memory in SRAM maintains the buffer memory of a small amount of third level mapping table and the buffer memory of as far as possible many second level mapping tables, and described multiple physical block forms a superblock, said method comprising the steps of:
Each logical page (LPAGE) is divided into three sections, respectively corresponding superblock block number, group number and group bias internal;
The block number of the physical block distributed by each superblock is recorded in superblock allocation table;
First order mapping table is set up in sram according to described superblock allocation table, and using described superblock block number as the index of described first order mapping table;
Judge whether described second level mapping table is hit at the buffer memory of SRAM by described superblock block number;
If so, then judge whether described third level mapping table is hit at the buffer memory of SRAM by described group number;
If so, then judge whether described superblock allocation table is hit at the buffer memory of SRAM;
If so, then the block number obtaining described physical block is combined, to obtain the physical address of described logical page (LPAGE) according to the buffer memory of the buffer memory of described second level mapping table, the buffer memory of described third level mapping table and described superblock allocation table;
Wherein, described foundation in sram in the step of first order mapping table according to described superblock allocation table comprises the following steps:
Obtain the block number of the physical block of described superblock allocation table on flash memory;
Binary chop is utilized to search the Physical Page page number of last write on described physical block;
Read up-to-date superblock allocation table, and record corresponding Physical Page page number;
Inquire about described superblock allocation table and obtain the physical block block number that each superblock finally writes;
Binary chop is utilized to search the Physical Page page number that the physical block of described last write finally writes;
Judge whether described superblock is last superblock;
If so, then described first order mapping table completes foundation.
7. the address conversion method of flash memory as claimed in claim 6, it is characterized in that, if described second level mapping table is not hit at the buffer memory of SRAM, then by the described superblock block number described first order mapping table of inquiry, and set up the buffer memory of second level mapping table at SRAM according to described first order mapping table.
8. the address conversion method of flash memory as claimed in claim 6, it is characterized in that, if described third level mapping table is not hit at the buffer memory of SRAM, then inquired about the buffer memory of described second level mapping table by described group number, and be buffered according to the described second level mapping table buffer memory that SRAM sets up third level mapping table.
9. the address conversion method of flash memory as claimed in claim 6, is characterized in that, if described superblock allocation table is not hit at the buffer memory of SRAM, then write back by described superblock allocation table, and replace the buffer memory of described superblock allocation table.
10. the address conversion method of flash memory as claimed in claim 6, is characterized in that, if described superblock is not last superblock, then continues the block number of the physical block that the described superblock allocation table of inquiry finds next superblock finally to write.
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