CN103176916A - Flash memory and address transfer approach thereof - Google Patents
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Abstract
Provided is a flash memory. The flash memory is in communication connection with a static random access memory (SRAM) and is composed of physical blocks. Each physical block is composed of a plurality of physical pages, logic pages are in one-to-one correspondence with the physical pages. The physical pages comprise a second-level mapping table and a third-level mapping table, and the plurality of physical blocks form a superblock. The flash memory further comprises an obtaining module, a recording module, an establishing module, a judging module and an outputting module. According to the flash memory and an address transfer approach of the flash memory, first-level mapping tables are established on the SRAM through a superblock assignment table, cache of the second-level mapping tables, the third-level mapping tables and the superblock assignment table is judged, and therefore addresses of the physical pages are obtained. The cache of the second-level mapping tables is established on the SRAM according to the first-level mapping tables, the cache of the third-level mapping tables is established on the SRAM according to the second-level mapping tables, then block numbers of the physical blocks are obtained through the cache of the second-level mapping tables, the cache of the third-level mapping tables and the superblock assignment table in a combined mode, and therefore physical domains of the logic pages are obtained. The flash memory and the address transfer approach of the flash memory effectively improve address transferring efficiency.
Description
Technical field
The present invention relates to computing machine and electronic information technical field, relate in particular to the address conversion method of a kind of flash memory and flash memory.
Background technology
The characteristics such as that flash memory, NAND Flash have is non-volatile, low in energy consumption, performance is high and anti-seismic performance is strong have a wide range of applications.NAND flash has following characteristics: 1), the read-write least unit be page; 2), wiping least unit is piece; 3), can not make carbon copies, must first wipe afterwards and write; 4), the piece that has can become bad piece when dispatching from the factory or in use procedure, can not continue to use.The page of NAND has main (main) district and standby (spare) district to consist of, and user data is deposited in the primary area, and ECC error correcting code, part mapping information and other management information etc. are generally deposited in the spare area.
Flash translation layer (FTL) (FTL) is responsible for logical address to the mapping of physical address, and the information such as bad block management are abstracted into a calibrated bolck equipment with NAND, to hiding host NAND bottom-up information.The mapping mode of flash memory generally is divided into piece mapping, page mapping and mixes three kinds of mappings.The piece mapping is few to the internal memory resource occupation, but efficient is low; The page mapping efficiency is high, but large to the internal memory resource occupation; Mix mapping and do compromise aforementioned between both according to demand.
Application number is the principle that 201010133944.8 Chinese invention patent application " address conversion method of flash storage FTL " has proposed a kind of three grades of mappings, but does not indicate in practice, and how mapping tables at different levels are stored and built, and efficient is low.
Summary of the invention
In view of this, be necessary to provide the address conversion method of a kind of flash memory and flash memory.
Flash memory provided by the invention, flash memory and SRAM communication connection, formed by physical block, wherein said physical block is comprised of a plurality of Physical Page, logical page (LPAGE) is corresponding one by one with Physical Page, comprise second level mapping table and third level mapping table in described Physical Page, described a plurality of physical block forms a superblock, also comprise: acquisition module, logging modle, set up module, judge module and output module, wherein: acquisition module is used for logical page (LPAGE) is divided into three sections, respectively corresponding superblock piece number, group number and group bias internal; Logging modle is used for physical block piece that each superblock is comprised and number is recorded to the superblock allocation table; Set up module and be used for setting up first order mapping table according to described superblock allocation table at SRAM, and with the described superblock piece number index as described first order mapping table; Judge module is used for number judging whether described second level mapping table is hit at the buffer memory of SRAM by described superblock piece, and judge by described group number whether described third level mapping table is hit at the buffer memory of SRAM at described second level mapping table when the buffer memory of SRAM is hit, judge at described third level mapping table whether described superblock allocation table is hit at the buffer memory of SRAM when the buffer memory of SRAM is hit; Output module, be used for uniting according to the buffer memory of the buffer memory of the buffer memory of described second level mapping table, described third level mapping table and described superblock allocation table the piece number that obtains described physical block at described superblock allocation table when the buffer memory of SRAM is hit, to obtain the physical address of described logical page (LPAGE).
The address conversion method of flash memory provided by the invention, wherein, flash memory and SRAM communication connection, be comprised of physical block, wherein said physical block is comprised of a plurality of Physical Page, and logical page (LPAGE) is corresponding one by one with Physical Page, comprise second level mapping table and third level mapping table in described Physical Page, described a plurality of physical block forms a superblock, said method comprising the steps of: logical page (LPAGE) is divided into three sections, respectively corresponding superblock piece number, group number and group bias internal; The physical block piece that each superblock is distributed number is recorded in the superblock allocation table; Set up first order mapping table according to described superblock allocation table in SRAM, and with the described superblock piece number index as described first order mapping table; Number judge whether described second level mapping table is hit at the buffer memory of SRAM by described superblock piece; If judge by described group number whether described third level mapping table is hit at the buffer memory of SRAM; If judge whether described superblock allocation table is hit at the buffer memory of SRAM; If unite according to the buffer memory of the buffer memory of the buffer memory of described second level mapping table, described third level mapping table and described superblock allocation table the piece number that obtains described physical block, to obtain the physical address of described logical page (LPAGE).
The address conversion method of flash memory provided by the invention and flash memory, set up first order mapping table by utilizing the superblock allocation table on SRAM, and set up the buffer memory of second level mapping table according to first order mapping table on SRAM, set up the buffer memory of third level mapping table according to the buffer memory of second level mapping table, and unite the piece number that obtains described physical block according to the buffer memory of the buffer memory of the buffer memory of second level mapping table, third level mapping table and superblock allocation table, to obtain described logical page (LPAGE) physically, effectively raise the efficient of address translation.
Description of drawings
Fig. 1 is the graph of a relation of logical block, physical block, logical page (LPAGE) and Physical Page in an embodiment of the present invention;
Fig. 2 is the structural drawing of an embodiment of the present invention logical page (LPAGE);
Fig. 3 is the structural drawing of an embodiment of the present invention Physical Page;
Fig. 4 is the module map of flash memory in an embodiment of the present invention;
Fig. 5 is the structural drawing of superblock allocation table in an embodiment of the present invention;
Fig. 6 is the process flow diagram of the address conversion method of flash memory in an embodiment of the present invention;
Fig. 7 is the particular flow sheet of step S20 in process flow diagram shown in Figure 6.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention, term " interior ", " outward ", " vertically ", " laterally ", " on ", orientation or the position relationship of the indications such as D score, " top ", " end " be based on orientation shown in the drawings or position relationship, be only the present invention for convenience of description rather than require the present invention with specific orientation structure and operation, therefore can not be interpreted as limitation of the present invention.
See also Fig. 1, Figure 1 shows that the graph of a relation of logical block in an embodiment of the present invention, physical block, logical page (LPAGE) and Physical Page.
In the present embodiment, flash memory and SRAM(figure do not show) communication connection, formed by physical block, wherein said physical block is comprised of a plurality of Physical Page, logical page (LPAGE) is corresponding one by one with Physical Page, comprise second level mapping table and third level mapping table in described Physical Page, described a plurality of physical blocks form a superblock, and physical block is comprised of a plurality of Physical Page.In the present embodiment, flash memory has 8 physical blocks, and each physical block has 8 Physical Page, a total 8x8=64 Physical Page, if a physical page size is 8KB, the capacity of physical block is 64x8=512KB so.The operable Spatial General 6 R of main frame is worth less than this, 256KB (this fully by deviser oneself divide) for example, be equivalent to only have the useful space (4*6=32 Physical Page) of 4 physical blocks, superblock is logical concept, and superblock is generally greater than physical block, if super block size is 2 physics block sizes, main frame thinks that one has 4/2=2 superblock so, each superblock has 8*2=16 logical page (LPAGE), is also just 32 logical page (LPAGE)s altogether, and logical page (LPAGE) and physical page size equate.
Logical page (LPAGE), superblock are logical addresses, the address of namely main frame use; Physical Page, physical block are physical addresss, refer to the address on NAND.
Logical page (LPAGE) 0～15 belongs to superblock 0, logical page (LPAGE) 16～31 belongs to superblock 1(and divides in order), what provide when main frame reads and writes data is logical address, it is indifferent to data and specifically leaves physical address on NAND in, when reading logical page (LPAGE) 0 such as main frame, logical page (LPAGE) 0 just belongs to superblock 0, so by three grades of mapping relations, final find that this logical page (LPAGE) 0 is stored on the Physical Page 1 of physical block 3 of NAND, reads so this page and just obtains data.
See also Fig. 2, Fig. 2 is the structural drawing of an embodiment of the present invention logical page (LPAGE).
In the present embodiment, logical page (LPAGE) comprises superblock piece number, group number and group bias internal three parts.
See also Fig. 3, Fig. 3 is the structural drawing of an embodiment of the present invention Physical Page.
In the present embodiment, the content of Physical Page comprises user data, second level mapping table, third level mapping table and other guide.
In the present embodiment, second level mapping table and third level mapping table disperse to be stored in a plurality of Physical Page.
See also Fig. 4, Fig. 4 is the module map of flash memory 10.
In the present embodiment, flash memory 10 comprises acquisition module 102, logging modle 104, sets up module 106, judge module 108, output module 110, memory module 112 and processor 114, wherein, memory module 112 is used for storage acquisition module 102, logging modle 104, sets up module 106, judge module 108 and output module 110, and processor 114 is used for carrying out each functional module of memory module 112.
In the present embodiment, flash memory 10 does not show with SRAM(figure) communication connection, formed by physical block, wherein said physical block is comprised of a plurality of Physical Page, logical page (LPAGE) is corresponding one by one with Physical Page, comprise second level mapping table and third level mapping table in described Physical Page, described a plurality of physical block forms a superblock, logical page (LPAGE) is corresponding one by one with Physical Page, comprise second level mapping table and third level mapping table in described Physical Page, described a plurality of Physical Page forms a physical block, and described a plurality of physical blocks form a superblock.
In the present embodiment, in the fixed-size situation of superblock, divide into groups less, second level mapping table is less, and third level mapping table is larger.
In the present embodiment, acquisition module 102 is used for logical page (LPAGE) is divided into three sections, respectively corresponding superblock piece number, group number and group bias internal.In the present embodiment, group number is used for index second level mapping table (title group mapping table again), and the group bias internal is used for index third level mapping table (mapping table in the title group again).
The piece that logging modle 104 is used for physical block that each superblock is comprised number is recorded to the superblock allocation table.In the present embodiment, the superblock allocation table is stored in the specific physical block of flash memory 10, and specific physical block is stored on other non-volatile memory devices (as NOR Flash).
See also Fig. 5, Figure 5 shows that the structural drawing of superblock allocation table.
In the present embodiment, Physical Page comprises effectively (invalid) page, invalid (valid) page and empty (empty) page.
In the present embodiment, the superblock allocation table is stored in specific of flash memory, may need to take a plurality of pages, when super allocation table upgrades, is written in next blank page.
Please continue to consult Fig. 4, set up module 106 and be used for setting up first order mapping table according to described superblock allocation table at SRAM, and with the described superblock piece number index as described first order mapping table.
In the present embodiment, described set up module 106 comprise obtain submodule 1062, search submodule 1064, reading submodule 1066 and judgement submodule 1068.
In the present embodiment, obtain the piece number that submodule 1062 is used for obtaining the physical block of described superblock allocation table on flash memory.
Search submodule 1064 for the Physical Page page number that writes at last on described physical block by utilizing binary chop to search.
Describedly search that submodule 1064 also is used at described superblock if not last superblock, continue the piece number that the described superblock allocation table of inquiry finds the physical block that next superblock writes at last.
Please continue to consult Fig. 4, judge module 108 is used for number judging whether described second level mapping table is hit at the buffer memory of SRAM by described superblock piece, and judge by described group number whether described third level mapping table is hit at the buffer memory of SRAM at described second level mapping table when the buffer memory of SRAM is hit, judge at described third level mapping table whether described superblock allocation table is hit at the buffer memory of SRAM when the buffer memory of SRAM is hit.
In the present embodiment, the buffer memory in SRAM is kept the buffer memory of the buffer memory of a small amount of third level mapping table and second level mapping table as much as possible, like this, makes flash memory 10 that optimum order readwrite performance and random read-write performance be arranged.
In the present embodiment, the buffer memory of second level mapping table and third level mapping table comprises page number and the buffer memory mark of piece inquiry code, Physical Page.The piece inquiry code is to obtain the piece number of physical block in order to inquire about the superblock allocation table.Because the physical block of flash memory 10 is a lot, and the physical block number that each superblock drops on is limited.For example, a superblock can be written at most (this can be defined by deviser oneself) on 4 physical blocks, and the piece inquiry code only needs 2bit just passable so, the use of effectively saving space, flash memory Physical Page spare area.
Concrete, in the present embodiment, output module 110 is according to second level mapping table buffer memory, third level mapping table buffer memory and superblock allocation table buffer memory are united and are obtained physical block number, obtain page number in physical block according to second level mapping table buffer memory and third level mapping table buffer memory, obtain thus the physical address of a logical page (LPAGE), namely physical address is the physical page number in physical block piece number and physical block.
In the present embodiment, the described module 106 of setting up also is used at described second level mapping table when the buffer memory of SRAM is not hit, number inquire about described first order mapping table by described superblock piece, and set up the buffer memory of second level mapping table at SRAM according to described first order mapping table.
In the present embodiment, the described module 106 of setting up also is used at described third level mapping table when the buffer memory of SRAM is not hit, by the buffer memory of described group number inquiry described second level mapping table, and according to the buffer memory that SRAM sets up third level mapping table that is buffered in of described second level mapping table.
In the present embodiment, the described module 106 of setting up also is used at described superblock allocation table described superblock allocation table being write back, and replacing the buffer memory of described superblock allocation table when the buffer memory of SRAM is not hit.
See also Fig. 6, Figure 6 shows that the process flow diagram of the address conversion method of flash memory 10 in an embodiment of the present invention.
In the present embodiment, flash memory 10 does not show with SRAM(figure) communication connection, formed by physical block, wherein said physical block is comprised of a plurality of Physical Page, logical page (LPAGE) is corresponding one by one with Physical Page, comprise second level mapping table and third level mapping table in described Physical Page, described a plurality of physical blocks form a superblock, said method comprising the steps of:
At step S00, acquisition module 102 is divided into three sections with logical page (LPAGE), respectively corresponding superblock piece number, group number and group bias internal.In the present embodiment, group number is used for index second level mapping table (title group mapping table again), and the group bias internal is used for index third level mapping table (mapping table in the title group again).
At step S10, the physical block piece that logging modle 104 is distributed each superblock number is recorded in the superblock allocation table.
At step S20, set up module 106 and set up first order mapping table according to described superblock allocation table in SRAM, and with the described superblock piece number index as described first order mapping table.
At step S30, judge module 108 number judges whether described second level mapping table is hit at the buffer memory of SRAM by described superblock piece.
In the present embodiment, the buffer memory of second level mapping table and third level mapping table comprises page number and the buffer memory mark of piece inquiry code, Physical Page.
In the present embodiment, the piece inquiry code is to obtain the piece number of physical block in order to inquire about the superblock allocation table.Because the physical block of flash memory 10 is a lot, and the physical block number that each superblock drops on is limited.For example, a superblock can be written at most (this can be defined by deviser oneself) on 4 physical blocks, and the piece inquiry code only needs 2bit just passable so, the use of effectively saving space, flash memory Physical Page spare area.
If described second level mapping table is hit at the buffer memory of SRAM, at step S40, judge module 108 judges by described group number whether described third level mapping table is hit at the buffer memory of SRAM;
If described third level mapping table is hit at the buffer memory of SRAM, at step S50, judge module 108 judges whether described superblock allocation table is hit at the buffer memory of SRAM.
If described superblock allocation table is hit at the buffer memory of SRAM, at step S60, output module 110 is followed according to the buffer memory of the buffer memory of the buffer memory of described second level mapping table, described third level mapping table and described superblock allocation table and is united the piece number that obtains described physical block, to obtain the physical address of described logical page (LPAGE).In the present embodiment, output module 110 is according to second level mapping table buffer memory, third level mapping table buffer memory and superblock allocation table buffer memory are united and are obtained physical block number, obtain page number in physical block according to second level mapping table buffer memory and third level mapping table buffer memory, obtain thus the physical address of a logical page (LPAGE), namely physical address is the physical page number in physical block piece number and physical block.
If described second level mapping table is not hit at the buffer memory of SRAM, at step S70, sets up module 106 and number inquire about described first order mapping table by described superblock piece, and set up the buffer memory of second level mapping table at SRAM according to described first order mapping table.
If described third level mapping table is not hit at the buffer memory of SRAM, at step S80, set up module 106 by the buffer memory of described group number inquiry described second level mapping table, and according to the buffer memory that SRAM sets up third level mapping table that is buffered in of described second level mapping table.
If described superblock allocation table is not hit at the buffer memory of SRAM, at step S90, sets up module 106 described superblock allocation table is write back, and replace the buffer memory of described superblock allocation table.
See also Fig. 7, Figure 7 shows that the particular flow sheet of S20 in Fig. 6.
In the present embodiment, step S20 comprises the following steps:
At step S202, obtain the piece number that submodule 1062 obtains the physical block of described superblock allocation table on flash memory.
At step S204, search the Physical Page page number that submodule 1064 utilizes binary chop to search to write at last on described physical block.
At step S206, reading submodule 1066 reads up-to-date superblock allocation table, and records corresponding Physical Page page number.In the present embodiment, reading submodule 1066 reads the Physical Page that writes at last, and back reads each Physical Page, until up-to-date superblock allocation table is all read, and write down corresponding physical page number and the corresponding relation of superblock allocation table
At step S208, search the described superblock allocation tables of submodule 1064 inquiry and obtain physical block piece that each superblock writes at last number.
At step S210, search submodule 1066 and utilize binary chop to search the page number that writes at last on the described physical block that writes at last.
At step S212, judge that submodule 1068 judges whether described superblock is last superblock.
If described superblock is last superblock, at step S214, set up the foundation that module 106 is completed described first order mapping table.
If described superblock is not last superblock, continue to return to step S208, search the piece number that the described superblock allocation tables of submodule 1064 inquiry find the physical block that next superblock writes at last.
The address conversion method of flash memory 10 provided by the invention and flash memory, set up first order mapping table by utilizing the superblock allocation table on SRAM, and set up the buffer memory of second level mapping table according to first order mapping table on SRAM, set up the buffer memory of third level mapping table according to the buffer memory of second level mapping table, and the buffer memory of following the buffer memory of the buffer memory according to described second level mapping table, described third level mapping table and described superblock allocation table is united the piece number that obtains described physical block, to obtain the physical address of described logical page (LPAGE), effectively raise the efficient of address translation.
Although the present invention is described with reference to current better embodiment; but those skilled in the art will be understood that; above-mentioned better embodiment only is used for illustrating the present invention; be not to limit protection scope of the present invention; any within the spirit and principles in the present invention scope; any modification of doing, equivalence replacement, improvement etc. are within all should being included in the scope of the present invention.
Claims (12)
1. a flash memory, with the SRAM communication connection, be comprised of physical block, wherein said physical block is comprised of a plurality of Physical Page, and logical page (LPAGE) is corresponding one by one with Physical Page, comprises second level mapping table and third level mapping table in described Physical Page, described a plurality of physical block forms a superblock, also comprises:
Acquisition module is used for logical page (LPAGE) is divided into three sections, respectively corresponding superblock piece number, group number and group bias internal;
Logging modle is used for physical block piece that each superblock is comprised and number is recorded to the superblock allocation table;
Set up module, be used for setting up first order mapping table according to described superblock allocation table at SRAM, and with the described superblock piece number index as described first order mapping table;
Judge module, be used for number judging whether described second level mapping table is hit at the buffer memory of SRAM by described superblock piece, and judge by described group number whether described third level mapping table is hit at the buffer memory of SRAM at described second level mapping table when the buffer memory of SRAM is hit, judge at described third level mapping table whether described superblock allocation table is hit at the buffer memory of SRAM when the buffer memory of SRAM is hit;
Output module, be used for uniting according to the buffer memory of the buffer memory of the buffer memory of described second level mapping table, described third level mapping table and described superblock allocation table the piece number that obtains described physical block at described superblock allocation table when the buffer memory of SRAM is hit, to obtain the physical address of described logical page (LPAGE).
2. flash memory as claimed in claim 1, it is characterized in that, the described module of setting up also is used for number not inquiring about described first order mapping table by described superblock piece at described second level mapping table when the buffer memory of SRAM is hit, and sets up the buffer memory of second level mapping table at SRAM according to described first order mapping table.
3. flash memory as claimed in claim 1, it is characterized in that, the described module of setting up also is used for inquiring about by described group number when the buffer memory of SRAM is not hit at the described third level mapping table buffer memory of described second level mapping table, and according to the buffer memory that SRAM sets up third level mapping table that is buffered in of described second level mapping table.
4. flash memory as claimed in claim 1, is characterized in that, the described module of setting up also is used for described superblock allocation table not being write back when the buffer memory of SRAM is hit at described superblock allocation table, and replaces the buffer memory of described superblock allocation table.
5. flash memory as claimed in claim 1, is characterized in that, the described module of setting up comprises:
Obtain submodule, be used for obtaining the piece number of the physical block of described superblock allocation table on flash memory;
Search submodule, the Physical Page page number that is used for utilizing binary chop to search and writes at last on described physical block;
Reading submodule, be used for reading up-to-date superblock allocation table, and record corresponding Physical Page page number, wherein, the described submodule of searching also is used for inquiring about described up-to-date superblock allocation table and obtains physical block piece that each superblock writes at last number, and utilizes binary chop to search the page number that writes at last on the described physical block that writes at last;
The judgement submodule is used for determining whether last superblock that if last superblock, described first order mapping table is completed foundation.
6. flash memory as claimed in claim 5, is characterized in that, the described submodule of searching also is used for when described superblock is not last superblock, continues the piece number that the described superblock allocation table of inquiry finds the physical block that next superblock writes at last.
7. the address conversion method of a flash memory, wherein, flash memory and SRAM communication connection, formed by physical block, wherein said physical block is comprised of a plurality of Physical Page, and logical page (LPAGE) is corresponding one by one with Physical Page, comprises second level mapping table and third level mapping table in described Physical Page, described a plurality of physical block forms a superblock, said method comprising the steps of:
Logical page (LPAGE) is divided into three sections, respectively corresponding superblock piece number, group number and group bias internal;
The piece of the physical block that each superblock is distributed number is recorded in the superblock allocation table;
Set up first order mapping table according to described superblock allocation table in SRAM, and with the described superblock piece number index as described first order mapping table;
Number judge whether described second level mapping table is hit at the buffer memory of SRAM by described superblock piece;
If judge by described group number whether described third level mapping table is hit at the buffer memory of SRAM;
If judge whether described superblock allocation table is hit at the buffer memory of SRAM;
If unite according to the buffer memory of the buffer memory of the buffer memory of described second level mapping table, described third level mapping table and described superblock allocation table the piece number that obtains described physical block, to obtain the physical address of described logical page (LPAGE).
8. the address conversion method of flash memory as claimed in claim 7, it is characterized in that, if described second level mapping table is not hit at the buffer memory of SRAM, number inquire about described first order mapping table by described superblock piece, and set up the buffer memory of second level mapping table at SRAM according to described first order mapping table.
9. the address conversion method of flash memory as claimed in claim 7, it is characterized in that, if described third level mapping table is not hit at the buffer memory of SRAM, the buffer memory by described group number inquiry described second level mapping table, and according to the buffer memory that SRAM sets up third level mapping table that is buffered in of described second level mapping table.
10. the address conversion method of flash memory as claimed in claim 7, is characterized in that, if described superblock allocation table is not hit at the buffer memory of SRAM, described superblock allocation table write back, and replace the buffer memory of described superblock allocation table.
11. the address conversion method of flash memory as claimed in claim 7 is characterized in that, comprises the following steps in the step of described " setting up first order mapping table according to described superblock allocation table in SRAM ":
Obtain the piece number of the physical block of described superblock allocation table on flash memory;
The Physical Page page number that utilizes binary chop to search to write at last on described physical block;
Read described up-to-date superblock allocation table, and record corresponding Physical Page page number;
Inquire about described superblock allocation table and obtain physical block piece that each superblock writes at last number;
Utilize binary chop to search the page number that writes at last on the described physical block that writes at last;
Judge whether described superblock is last superblock;
If described first order mapping table is completed foundation.
12. the address conversion method of flash memory as claimed in claim 11 is characterized in that, if described superblock is not last superblock, continues the piece number that the described superblock allocation table of inquiry finds the physical block that next superblock writes at last.
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