CN105607862A - Solid state disk capable of combining DRAM (Dynamic Random Access Memory) with MRAM (Magnetic Random Access Memory) and being provided with backup power - Google Patents
Solid state disk capable of combining DRAM (Dynamic Random Access Memory) with MRAM (Magnetic Random Access Memory) and being provided with backup power Download PDFInfo
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Abstract
The invention provides a solid state disk capable of combining a DRAM (Dynamic Random Access Memory) with a MRAM (Magnetic Random Access Memory) and being provided with a backup power. The solid state disk comprises a host interface, a main control chip, the DRAM, the MRAM, one or a plurality of NAND chips and the backup power, wherein the main control chip comprises a CPU (Central Processing Unit); the NAND chip stores a logic physical address comparison table; the DRAM comprises write cache or read and write cache; when a system is started, the logic physical address comparison table in the NAND chip is loaded to the DRAM; and the MRAM comprises an update table, wherein the update table is used for storing an update record of the logic physical address comparison table. The solid state disk capable of combining the DRAM with the MRAM and being provided with the backup power can use the DRAM as the write cache to provide a large cache size, write cache maximization is exchanged by small cost increase, and therefore, the performance and the service life of the solid state disk are optimal. When outage happens, the backup power is used for writing a cache page in the write cache or the read and write cache back to an erased idle page in the NAND chip, speed for writing one page is high, and the performance of the solid state disk can be greatly improved.
Description
Technical field
The present invention relates to memory device, be specifically related to a kind of DRAM and be combined with MRAM and there is the solid state hard disc of backup battery.
Background technology
Current, the development of nand flash memory technology has promoted SSD industry. As shown in Figure 1, between SSD and main frame, use at a high speedSerial line interface is as SATA, the technology such as PICe. Inner by one group of NAND chip for storing data, calculate for supporting andData cached DDRDRAM (internal memory), and a main control chip (SSDController) composition. Sometimes also needWant circuit breaking protective system.
NAND is a kind of memory device of monoblock read-write, and the unit that minimum readable is got is page (page), minimum erasable listPiece (block) is in unit, and a piece is often made up of a lot of pages, and the page that piece is wiped rear the inside can carry out independent write operation.Write operation is very slow, much slower than reading, and erase operation is much slower than writing.
A problem of nand flash memory is that NAND has the limited life-span. Each page of certain number of times of process erasable of the insideAfter, will permanent failure can not continue to use. The current trend of industry development is capacity and the packing density of NAND chipIncrease very fast, but taking reduce the life-span as cost. Erasable number of times is reduced to current 3000 for 100,000 times from initialInferior left and right.
Since the above characteristic of nand flash memory, the NAND management software more complicated of SSD inside. In order not make some frequentThe piece that write operation occurs damages in advance, need to write equilibrium treatment. The logical address that file system software is identified and physicsAddress is different, needs a table that the two is mapped.
Because NAND chip erase is too slow, while generally revising a content, do not upgrade in original Kuai district, but new contentWrite a Ge Xinkuai district, it is invalid that Jiu Kuai district is labeled as, and waits the CPU free time to get off to wipe it again. Like this, logical physical addressThe table of comparisons constantly dynamically updates.
The size of logical physical address translation table is proportional to the total capacity of memory device, is stored in DDRDRAM, exists in additionIn NAND chip, also there is corresponding backup information. Along with increasing sharply of SSD capacity on market, this telogenesis be DRAMLarge consumer.
Because the read or write speed of NAND is much slower than DRAM, can also utilize a part of dram space to make the buffer memory of reading and writing(Cache), to improve the performance of whole SSD.
Write buffer memory and produced new problem but introduce: once there is power-off, in DRAM buffer memory, not yet write the content of NANDCan lose, cause the damage of the even whole file system of system loss data. Therefore must use simultaneously expensive, volume is largeCircuit breaking protective system (generally being formed by battery or a large amount of capacitors). And the logical-physical address table of comparisons is occurringAfter power-off, be to utilize the data in NAND to re-construct, although very time-consuming.
About MRAM:
MRAM is a kind of new internal memory and memory technology, can be as SRAM/DRAM quick random read-write, can also look likeThe same data that forever retain after power-off of Flash flash memory.
The economy of MRAM is fairly good, and the silicon area that unit capacity takies has very large advantage than SRAM, than at this type of coreThe NORFlash often using in sheet also has superiority, larger than the advantage of embedded NOR Flash. The performance of MRAM alsoFairly good, read-write time delay approaches best SRAM, and power consumption is best at various internal memories and memory technology. And MRAM unlikeDRAM and Flash, incompatible with standard CMOS semiconductor technology, MRAM can be integrated into a chip with logic circuitIn.
About operating system and software:
As shown in Figure 2, the file operation mode of computer is as follows:
(1) application software send to operating system open, close, reading and writing file instruction;
(2) the file system part in operating system is converted into the instruction of reading and writing file the instruction of reading and writing memory block;
(3) NAND drives the instruction of accepting read-write memory block district with management software, and carry out buffer memory, write the optimizations such as balanced, toChip sends read-write page, wipes the instructions such as block.
In computer, NAND drives with management software and conventionally on the main control chip of solid state hard disc, moves.
Use MRAM as the buffer memory of writing in memory device, can improve writing speed, can save again circuit breaking protective system,When adopt some strategies that the NAND page that often carries out write operation is stayed and write in buffer memory as far as possible, can reduce and write NAND chipNumber of times, extend service life of product.
But MRAM within following a period of time, price can be very high, capacity can be less than normal, less buffer memory capacity can limitThe performance of solid state hard disc, the resistivity of particularly impacting for data in the short time, also can weaken MRAM to NANDThe protective effect of chip.
And logical physical address translation table is when very large, can not wholely be stored in MRAM; And the contrast of logical physical addressTable changes again at any time. By present general algorithm, write operation of every generation, all can have corresponding logical physical addressTable of comparisons change. Therefore also it can not be kept in NAND chip.
Thereby need to find a kind of better solid state hard disc, and can either there is larger buffer memory capacity, can deposit safely againStorage logical physical address translation table, to ensure the readwrite performance of solid state hard disc.
Summary of the invention
Because the above-mentioned defect of prior art, technical problem to be solved by this invention is to provide a kind of DRAM and MRAMIn conjunction with the solid state hard disc with backup battery, can either there is larger buffer memory capacity, again stored logic thing safelyReason address translation table, to ensure the readwrite performance of solid state hard disc.
If operating speed is fast and power-off after keep the MRAM of content to replace DRAM, no doubt can write safely buffer memoryAnd the stored logic physical address table of comparisons, but in following significant period of time, MRAM still can be expensive more a lot of than DRAM,Capacity can be less than normal, and less buffer memory capacity can limit the performance of solid state hard disc, particularly impacts for data in the short timeResistivity, also can weaken the protective effect of MRAM to NAND chip.
The present invention, in solid state hard disc, mixes and uses MRAM and DRAM, and uses and have backup battery, can use DRAMWrite buffer memory larger buffer memory capacity is provided, can exchange the maximization of writing buffer memory for very little cost increase, make solidThe performance of state hard disk and life-span optimum.
But it is larger to write buffer memory, while there is power-off, it is write back to the time needing in NAND chip just longer. SimultaneouslyMay need the renewal that also has logical physical address translation table writing back. Therefore need to optimize distribution, make these contentsCan full out write back, being equipped with under the condition of same backup battery, just can use in DRAM larger like thisWrite buffer memory.
The data of buffer memory being write back to the time of NAND chip, different in the situation that, is to have very large difference.If revise in existing data, may need handle to read out containing whole that carries many pages, want at least wholeWipe and again write again one time. This time is very long. Taking certain the type NAND on present market as example, a pieceHave 512 pages, the capacity of every page of 16KB, wipes and needs 3ms, and writing one page needs 1.6ms, wipes for whole again and rewritesNeed 822ms, the time is very long.
The renewal of logical physical address translation table is write back to NAND and just belong to this situation. Because this form existsIn NAND, storage can not have been used logical address, generally can only be stored in physical address fixing in NAND, moreNewly generally can only on original address, upgrade. Like this, the little amendment of any one logical physical address translation table all needsWant 822ms, this will need sizable super capacitor. If different pieces all needs amendment in same Plane,Such amendment can only sequentially be carried out, and the time also will increase exponentially.
And the common caching page of writing is write back to NAND chip, can be very fast. NAND management software can select oneIndividual free page of having wiped writes, and writing one page only needs 1.6ms, and just logical physical address translation table needs sameStep is upgraded. The more important thing is, a lot of pages can write abreast. Also taking the NAND chip of same model as example,The hard disk of a 1TB can be made up of the chip of 8 1Tb, and each chip internal has 8 silicon chips, and each silicon chip has2 Plane, altogether 8x8x2=128 page (2MB) can complete and write being slightly more than 1.6ms.
So preferably strategy is that the renewal of logical physical address is kept in MRAM. Can use so largerDRAM write buffer memory.
The invention provides a kind of DRAM and be combined with MRAM and there is the solid state hard disc of backup battery, comprise HPI, masterControl chip, DRAM, MRAM, one or more NAND chip and backup battery, main control chip comprises CPU; NANDChip-stored logical physical address translation table, DRAM comprises and writes buffer memory or read-write cache, when system boot by NAND coreLogical physical address translation table in sheet is loaded into DRAM, and MRAM comprises updating form, and updating form is for stored logic thingThe more new record of reason address translation table.
DRAM provided by the invention is combined with MRAM has the solid state hard disc of backup battery, can use DRAM to write slowDeposit the buffer memory capacity that provides larger, can exchange the maximization of writing buffer memory for very little cost increase, make solid state hard discPerformance and life-span optimum
Further, the number of the more new record in updating form is more than or equal to setting value, uses more new record to upgradeLogical physical address translation table in NAND chip, and delete more new record.
Further, in the time there is power-off, utilize backup battery, the caching page of writing in buffer memory or read-write cache is write backTo the free page of having wiped in NAND chip, while writing a NAND page to NAND chip each time, upgradeTable, if there is the more new record of NAND page correspondence, upgrades new record more, otherwise adds in updating form, a new record more. Write back the free page of having wiped, write one page speed very fast, approximately only need 1.6ms, energyEnough performances that greatly improves solid state hard disc.
Further, write back to abreast in NAND chip and wiped writing caching page in buffer memory or read-write cacheFree page. Write back to abreast in NAND chip, can further improve the performance of solid state hard disc.
Further, while writing a NAND page to NAND chip each time, check updating form, if there is NANDThe more new record that page is corresponding, upgrades new record more, otherwise add a more new record in updating form; CPUIn the time of read-write operation, use logical physical address translation table and updating form in DRAM to carry out address translation.
Further, while writing a NAND page to NAND chip each time, check updating form, if there is NANDThe more new record that page is corresponding, upgrades new record more, otherwise add a more new record in updating form; And moreLogical physical address translation table in new DRAM, CPU uses the logical physical address pair in DRAM in the time of read-write operationCarry out address translation according to table.
Further, when system boot, the logical physical address translation table in NAND chip is loaded into after DRAM, makesWith the logical physical address translation table in the more new record renewal DRAM in updating form.
Further, MRAM is connected with main control chip by DRAM interface, or MRAM is integrated in main control chip.Due to MRAM unlike DRAM and Flash with standard CMOS semiconductor technology incompatible, MRAM can with logic electricityRoad is integrated in a chip, thereby can be integrated in a chip with main control chip, has simplified the structure of solid state hard disc.
Further, MRAM also comprises and writes buffer memory or read-write cache, further increases the capacity of writing buffer memory or read-write cache.
Compared with prior art, DRAM provided by the invention is combined with MRAM has the solid state hard disc of backup battery, hasFollowing beneficial effect:
(1) can use DRAM to write buffer memory larger buffer memory capacity is provided, can exchange for very little cost increaseWrite the maximization of buffer memory, make performance and the life-span optimum of solid state hard disc;
(2) in the time there is power-off, utilize backup battery, the caching page of writing in buffer memory or read-write cache is write back to NANDThe free page of having wiped in chip, writes one page speed very fast, can greatly improve the performance of solid state hard disc.
Below with reference to accompanying drawing, the technique effect of design of the present invention, concrete structure and generation is described further, with fullyObject of the present invention, feature and effect are understood in ground.
Brief description of the drawings
Fig. 1 is the structural representation of solid state hard disc in prior art;
Fig. 2 is that the DRAM of one embodiment of the present of invention is combined the structure of the solid state hard disc with backup battery and is shown with MRAMIntention.
Detailed description of the invention
As shown in Figure 2, the DRAM of one embodiment of the present of invention is combined with MRAM has the solid state hard disc of backup battery, bagDraw together HPI, main control chip, DRAM, MRAM, one or more NAND chip and backup battery, main control chip bagDraw together CPU; NAND chip-stored logical physical address translation table, DRAM comprises and writes buffer memory or read-write cache, when system bootLogical physical address translation table in NAND chip is loaded into DRAM, and MRAM comprises updating form, and updating form is patrolled for storageCollect the more new record of the physical address table of comparisons.
DRAM in the present embodiment is combined with MRAM has the solid state hard disc of backup battery, can use DRAM to write buffer memoryLarger buffer memory capacity is provided, can exchanges the maximization of writing buffer memory for very little cost increase, make the performance of solid state hard discWith life-span optimum.
For the piece that does not make some that write operation often occurs damages in advance, need to write equilibrium treatment. The physical address upgradingUpgrade just because of writing equilibrium.
The number of the more new record in updating form is more than or equal to setting value, uses more new record to upgrade patrolling in NAND chipCollect the physical address table of comparisons, and delete more new record.
In updating form, need to reserve at any time a part of space, the record count that this headspace holds be more than or equal to write slowThe number of the caching page in depositing, ensures to write back NAND by writing caching pages all in buffer memory or read-write cache while there is power-offWhen chip, the more new record of all logical physical address translation tables can both be saved in updating form.
In the time there is power-off, utilize backup battery, the caching page of writing in buffer memory or read-write cache is write back in NAND chipThe free page of having wiped, while writing a NAND page each time, checks updating form to NAND chip, if existedThe more new record of NAND page correspondence, upgrades new record more, otherwise add a more new record in updating form.Because NAND chip erase is too slow, while generally revising a content, namely NAND page is carried out to write operation, be not formerLai Kuai district upgrades, but new content is write to a Ge Xinkuai district, and it is invalid that Jiu Kuai district is labeled as, and waits the CPU free timeGet off to wipe again it, therefore just need to upgrade logical physical address translation table. Write back the free page of having wiped, write one pageSpeed is very fast, approximately only needs 1.6ms, can greatly improve the performance of solid state hard disc.
The caching page of writing in buffer memory or read-write cache is write back to the free page of having wiped in NAND chip abreast. FlatWrite back in NAND chip capablely, can further improve the performance of solid state hard disc.
While writing a NAND page to NAND chip each time, check updating form, if there is NAND page correspondence moreNew record, upgrades new record more, otherwise add a more new record in updating form; CPU is at read-write operationTime, use logical physical address translation table and updating form in DRAM to carry out address translation.
Particularly, CPU carries out write operation to a NAND page:
(1) first in updating form, obtain the physical address of renewal according to the logical address of NAND page, if deposited in updating formAt the more new record of NAND page correspondence, from this more new record obtain the physical address of renewal; If do not existed more in updating formNew record, obtains physical address in the logical physical address translation table from DRAM;
(2) according to the physical address obtaining, NAND page is carried out to read-write operation.
Add one more when new record each, check the more new record that whether has NAND page correspondence in updating form, ifExist, replace the physical address in new record more with new physical address; If there is no, in updating form, add oneBar is new record more.
MRAM is connected with main control chip by DRAM interface, or MRAM is integrated in main control chip. Due to MRAM unlikeDRAM and Flash are such and standard CMOS semiconductor technology is incompatible, and MRAM can be integrated into a core with logic circuitIn sheet, thereby can be integrated in a chip with main control chip, simplify the structure of solid state hard disc.
MRAM also comprises and writes buffer memory or read-write cache, further increases the capacity of writing buffer memory or read-write cache.
In another embodiment, be with the difference of above-described embodiment: write a NAND to NAND chip each timeWhen page in,, check updating form, if there is the more new record of NAND page correspondence, new record more upgraded, otherwiseIn updating form, add a more new record, and upgrade the logical physical address translation table in DRAM, CPU is at read-write operationTime use the logical physical address translation table in DRAM to carry out address translation.
When system boot, the logical physical address translation table in NAND chip is loaded into after DRAM, uses in updating form moreNew record upgrades the logical physical address translation table in DRAM.
DRAM provided by the invention is combined with MRAM has the solid state hard disc of backup battery, can use DRAM to write buffer memoryLarger buffer memory capacity is provided, can exchanges the maximization of writing buffer memory for very little cost increase, make the performance of solid state hard discWith life-span optimum; In the time there is power-off, utilize backup battery, the caching page of writing in buffer memory or read-write cache is write back to NANDThe free page of having wiped in chip, writes one page speed very fast, can greatly improve the performance of solid state hard disc.
More than describe preferred embodiment of the present invention in detail. Should be appreciated that those of ordinary skill in the art withoutCreative work just can design according to the present invention be made many modifications and variations. Therefore, all people of technology in the artMember is under this invention's idea on the basis of existing technology by the available skill of logical analysis, reasoning, or a limited experimentArt scheme, all should be in by the determined protection domain of claims.
Claims (9)
1. DRAM is combined with MRAM and is had the solid state hard disc of backup battery, comprise HPI, main control chip, DRAM,MRAM, one or more NAND chip and backup battery, described main control chip comprises CPU; Described NAND chipThe stored logic physical address table of comparisons, described DRAM comprises and writes buffer memory or read-write cache, when system boot by described NANDLogical physical address translation table in chip is loaded into described DRAM, it is characterized in that, described MRAM comprises updating form,Described updating form is for the more new record of the stored logic physical address table of comparisons.
2. DRAM as claimed in claim 1 is combined with MRAM and is had the solid state hard disc of backup battery, it is characterized in that,The number of the more new record in described updating form is more than or equal to setting value, and more new record upgrades described NAND described in useLogical physical address translation table in chip, and new record more described in deleting.
3. DRAM as claimed in claim 2 is combined with MRAM and is had the solid state hard disc of backup battery, it is characterized in that,In the time there is power-off, utilize described backup battery, the described caching page of writing in buffer memory or described read-write cache is write back toThe free page of having wiped in NAND chip, while writing a NAND page to described NAND chip each time, inspectionLook into described updating form, if there is the more new record of described NAND page correspondence, described more new record upgraded,Otherwise add a more new record in described updating form.
4. DRAM as claimed in claim 3 is combined with MRAM and is had the solid state hard disc of backup battery, it is characterized in that,The described caching page of writing in buffer memory or described read-write cache is write back to the sky of having wiped in NAND chip abreastNot busy page.
5. DRAM as claimed in claim 1 is combined with MRAM and is had the solid state hard disc of backup battery, it is characterized in that,While writing a NAND page to described NAND chip each time, check described updating form, if there is described NANDThe more new record that page is corresponding, upgrades described more new record, otherwise adds a renewal note in described updating formRecord; Described CPU, in the time of read-write operation, uses logical physical address translation table and described updating form in described DRAMCarry out address translation.
6. DRAM as claimed in claim 1 is combined with MRAM and is had the solid state hard disc of backup battery, it is characterized in that,While writing a NAND page to described NAND chip each time, check described updating form, if there is described NANDThe more new record that page is corresponding, upgrades described more new record, otherwise adds a renewal note in described updating formRecord; And upgrading the logical physical address translation table in described DRAM, described CPU uses described DRAM in the time of read-write operationIn logical physical address translation table carry out address translation.
7. DRAM as claimed in claim 6 is combined with MRAM and is had the solid state hard disc of backup battery, it is characterized in that,When system boot, the logical physical address translation table in described NAND chip is loaded into after described DRAM, described in useMore new record in updating form upgrades the logical physical address translation table in described DRAM.
8. DRAM as claimed in claim 1 is combined with MRAM and is had the solid state hard disc of backup battery, it is characterized in that,Described MRAM is connected with described main control chip by DRAM interface, or described MRAM is integrated in described main control chipIn.
9. DRAM as claimed in claim 1 is combined with MRAM and is had the solid state hard disc of backup battery, it is characterized in that,Described MRAM also comprises and writes buffer memory or read-write cache.
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