CN102981996A - Expansion device and method for periphery interfaces - Google Patents
Expansion device and method for periphery interfaces Download PDFInfo
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- CN102981996A CN102981996A CN2012104926768A CN201210492676A CN102981996A CN 102981996 A CN102981996 A CN 102981996A CN 2012104926768 A CN2012104926768 A CN 2012104926768A CN 201210492676 A CN201210492676 A CN 201210492676A CN 102981996 A CN102981996 A CN 102981996A
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Abstract
The invention discloses an expansion method for periphery interfaces. The expansion method for the periphery interfaces comprises the steps that a master SPI (Serial Peripheral Interface) is arranged on a main control chip; when the arrangement of the master SPI is completed, a slave SPI of an expansion chip is gated, and the reading/writing operation is performed on the slave SPI; an SPI2APB (Serial Peripheral Interface 2 Advanced Peripheral Bus) module receives and analyzes an SPI signal sent by the slave SPI, and the SPI signal is partitioned into a command signal, an address signal and a data signal; an APB is decoded according to the address signal, a periphery module corresponding to the address signal is gated, and the reading-writing operation of a register is performed on the gated periphery module; and the function task of the periphery module is executed according to the reading-writing operation of the register. The invention also discloses an expansion device for the periphery interfaces.
Description
Technical field
The present invention relates to a kind of expanding unit and method of Peripheral Interface.
Background technology
Along with the progress of science and technology and the continuous lifting of chip technology level, increasing SOC chip provides performance higher for the user, and integrated level is better, the single-chip solution that cost is lower.
Although these SOC chips itself are integrated abundant Peripheral Interface, but because the quantitative limitation of IO number of ports or the needs of application scenario or the appearance of new Peripheral Interface, under many circumstances, the Peripheral Interface that only provides by the SOC chip still is not enough to build the electronic system of a complexity.For example the first function of the part pin of SOC chip is used, and causes the Peripheral Interface of making the second function to use.Or the quantity of GPIO is inadequate, or the interface of UART is not enough, or lacks new Peripheral Interface etc.This can limit the application scenario of SOC chip, shortens the production life cycle of SOC chip.
Existing situation is, generally is the function that realizes SPI expansion GPI0 or UART by the Interface Expanding chip of an external special use.The interface type of this scheme extension is limited, generally only has GPIO and UART.Helpless for the Interface Expanding demand outside GPIO and the UART, the quantity of expansion also is subjected to the restriction of special-purpose Interface Expanding chip.In addition, also have and utilize the external chip with single-chip microcomputer of SPI, the Peripheral Interface that carries by single-chip microcomputer is again finished the expansion of peripheral hardware, this mode is subjected to the restriction of selected single-chip microcomputer, extendible interface is limited, and will additionally operate single-chip microcomputer, increases the construction cycle.
Summary of the invention
For solving the problems of the technologies described above, the invention provides solution and be:
A kind of expanding unit of Peripheral Interface is provided, comprises main control chip and extended chip, described main control chip includes at least one main SPI, and described extended chip comprises that at least one is from SPI, SPI2APB module and a plurality of peripheral module; Described at least one are connected the corresponding connection of a signal wire from the main SPI of SPI and main control chip with SS_n by SCLK, MOSI, MISO; Described SPI2APB module links to each other from SPI and ABP bus with described respectively; Described a plurality of peripheral module is connected with described ABP bus by the APB interface; Described main control chip is used for main SPI is configured; Described main SPI is used for when finishing when disposing gating from SPI, to carrying out read-write operation from SPI; Described SPI2APB module is used for receiving and resolving since the SPI of SPI signal, and the SPI signal is split into command signal, address signal and data-signal; The APB bus is used for deciphering according to address signal, and the peripheral module that gating is corresponding with address signal also carries out the register read write operation to the peripheral module of gating; Described peripheral module is used for carrying out its functional task according to described register read write operation.
Wherein, described extended chip is programmable logic device (PLD) or asic chip, and described programmable logic device (PLD) is FPGA or CPLD.
Wherein, described peripheral module is the peripheral control unit of GPIO controller, UART controller, I2C controller or other APB interface.
Another technical scheme provided by the invention is:
A kind of extended method of Peripheral Interface is provided, runs in the expanding unit of described Peripheral Interface, comprising:
Main control chip is configured main SPI; Main SPI when finish when configuration gating extended chip from SPI, to carrying out read-write operation from SPI; The SPI2APB module receives and resolves the SPI signal that sends from SPI, and the SPI signal is split into command signal, address signal and data-signal; The APB bus is deciphered according to address signal, and the peripheral module that gating is corresponding with address signal also carries out the register read write operation to the peripheral module of gating; Peripheral module is carried out its functional task according to described register read write operation.
Wherein, described extended chip is programmable logic device (PLD) or asic chip, and described programmable logic device (PLD) is FPGA or CPLD.
Wherein, described peripheral module is the peripheral control unit of GPIO controller, UART controller, I2C controller or other APB interface.
The invention has the beneficial effects as follows: by realizing that in programmable logic device (PLD) or asic chip SPI is to the conversion of APB bus, and articulate the IP module of various required APB interfaces in the APB bus, the multiplexing easily IP module of existing APB interface, realized that SPI turns GPIO, SPI turns UART and SPI turns the functions such as I2C, main control chip IO deficiency or peripheral module have been solved not or do not have the problem of new Peripheral Interface, enlarge the application scenario of main control chip, prolonged the production life cycle of main control chip.
Description of drawings
Fig. 1 is the structured flowchart of a kind of expanding unit of Peripheral Interface in an embodiment of the present invention;
Fig. 2 be in an embodiment of the present invention main SPI with from the connection diagram of SPI;
Fig. 3 is the process flow diagram of a kind of extended method of Peripheral Interface in an embodiment of the present invention.
The main element symbol description
Expanding unit 100; Main control chip 10; Extended chip 20; Main SPI 11; From SPI 21; SPI2APB module 22; GPIO controller 23 1; UART controller 232; I2C controller 233.
Embodiment
By describing technology contents of the present invention, structural attitude in detail, realized purpose and effect, below in conjunction with embodiment and cooperate that accompanying drawing is detailed to give explanation.
Seeing also Fig. 1, is the structured flowchart of a kind of expanding unit of Peripheral Interface in an embodiment of the present invention.A kind of expanding unit 100 of Peripheral Interface comprises main control chip 10 and extended chip 20, and described extended chip 20 is programmable logic device (PLD) or asic chip, and described programmable logic device (PLD) is FPGA or CPLD.
Described main control chip 10 comprises at least one main SPI11, described extended chip 20 comprises that at least one is from SPI21, SPI2APB module 22 and a plurality of peripheral module, in the present embodiment, described peripheral module is the peripheral control unit of GPIO controller 231, UART controller 232, I2C controller 233 or other APB interface.See also Fig. 2, be in an embodiment of the present invention main SPI with from the connection diagram of SPI, described at least one pass through SCLK, MOSI, MISO from SPI21 and main SPI11 of main control chip 10 and be connected the corresponding connection of a signal wire with SS_n.Described SPI2APB module 22 links to each other from SPI21 and ABP bus with described respectively.Described a plurality of peripheral module is connected with described ABP bus by the APB interface.
Described main control chip 10 is used for main SPI11 is configured, and described main SPI11 is used for when finishing when disposing gating from SPI21, to carrying out read-write operation from SPI21.Described SPI2APB module 22 is used for receiving and resolving since the SPI of SPI21 signal, and the SPI signal is split into command signal, address signal and data-signal.The APB bus is used for deciphering according to address signal, and the peripheral module that gating is corresponding with address signal also carries out the register read write operation to the peripheral module of gating.Described peripheral module is used for carrying out its functional task according to described register read write operation.
Seeing also Fig. 3, is the process flow diagram of a kind of extended method of Peripheral Interface in an embodiment of the present invention.
A kind of extended method of Peripheral Interface runs in the expanding unit 100 of described Peripheral Interface, comprising:
Step S1, main control chip are configured main SPI;
Step S2, main SPI when finish when configuration gating extended chip from SPI, to carrying out read-write operation from SPI;
Step S3, SPI2APB module receive and resolve the SPI signal that sends from SPI, and the SPI signal is split into command signal, address signal and data-signal;
Step S4, APB bus are deciphered according to address signal, and the peripheral module that gating is corresponding with address signal also carries out the register read write operation to the peripheral module of gating;
Step S5, peripheral module are carried out its functional task according to described register read write operation.
Wherein, described extended chip 20 is programmable logic device (PLD) or asic chip, and described programmable logic device (PLD) is FPGA or CPLD.Described peripheral module is the peripheral control unit of GPIO controller, UART controller, I2C controller or other APB interface.
The invention has the beneficial effects as follows: by realizing that in programmable logic device (PLD) or asic chip SPI is to the conversion of APB bus, and articulate the peripheral module of various required APB interfaces in the APB bus, the multiplexing easily peripheral module of existing APB interface, realized that SPI turns GPIO, SPI turns UART and SPI turns the functions such as I2C, main control chip IO deficiency or peripheral module have been solved not or do not have the problem of new Peripheral Interface, enlarge the application scenario of main control chip, prolonged the production life cycle of main control chip.
The above only is embodiments of the invention; be not so limit claim of the present invention; every equivalent structure or equivalent flow process conversion that utilizes instructions of the present invention and accompanying drawing content to do; or directly or indirectly be used in other relevant technical fields, all in like manner be included in the scope of patent protection of the present invention.
Claims (6)
1. the expanding unit of a Peripheral Interface is characterized in that, comprises main control chip and extended chip, and described main control chip includes at least one main SPI, and described extended chip comprises that at least one is from SPI, SPI2APB module and a plurality of peripheral module; Described at least one are connected the corresponding connection of a signal wire from the main SPI of SPI and main control chip with SS_n by SCLK, MOSI, MISO; Described SPI2APB module links to each other from SPI and ABP bus with described respectively; Described a plurality of peripheral module is connected with described ABP bus by the APB interface;
Described main control chip is used for main SPI is configured;
Described main SPI is used for when finishing when disposing gating from SPI, to carrying out read-write operation from SPI;
Described SPI2APB module is used for receiving and resolving since the SPI of SPI signal, and the SPI signal is split into command signal, address signal and data-signal;
The APB bus is used for deciphering according to address signal, and the peripheral module that gating is corresponding with address signal also carries out the register read write operation to the peripheral module of gating;
Described peripheral module is used for carrying out its functional task according to described register read write operation.
A kind of Peripheral Interface according to claim 1 and expanding unit, it is characterized in that described extended chip is programmable logic device (PLD) or asic chip, described programmable logic device (PLD) is FPGA or CPLD.
A kind of Peripheral Interface according to claim 1 and expanding unit, it is characterized in that described peripheral module is the peripheral control unit of GPIO controller, UART controller, I2C controller or other APB interface.
4. the extended method of a Peripheral Interface is characterized in that, runs in the expanding unit of the described Peripheral Interface of claim 1-3 any one, comprising:
Main control chip is configured main SPI;
Main SPI when finish when configuration gating extended chip from SPI, to carrying out read-write operation from SPI;
The SPI2APB module receives and resolves the SPI signal that sends from SPI, and the SPI signal is split into command signal, address signal and data-signal;
The APB bus is deciphered according to address signal, and the peripheral module that gating is corresponding with address signal also carries out the register read write operation to the peripheral module of gating;
Peripheral module is carried out its functional task according to described register read write operation.
A kind of Peripheral Interface according to claim 4 and extended method, it is characterized in that described extended chip is programmable logic device (PLD) or asic chip, described programmable logic device (PLD) is FPGA or CPLD.
A kind of Peripheral Interface according to claim 4 and extended method, it is characterized in that described peripheral module is the peripheral control unit of GPIO controller, UART controller, I2C controller or other APB interface.
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| CN2012104926768A CN102981996A (en) | 2012-11-26 | 2012-11-26 | Expansion device and method for periphery interfaces |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984268A (en) * | 2014-05-28 | 2014-08-13 | 大连美恒时代科技有限公司 | Input and output device of signal logic controller and signal logic controller |
| CN104794088A (en) * | 2015-04-22 | 2015-07-22 | 成都为开微电子有限公司 | Multi-interface bus converting expanding chip design |
| CN104820644A (en) * | 2015-04-30 | 2015-08-05 | 武汉大学 | Non-time-sharing port multiplexing method and device |
| CN105045746A (en) * | 2015-09-09 | 2015-11-11 | 四川九洲电器集团有限责任公司 | Interface expanding device |
| CN105446929A (en) * | 2015-12-14 | 2016-03-30 | 武汉芯昌科技有限公司 | Port multiplexing circuit capable of supporting SPI, I2C, I2CL and UART protocols |
| CN105720967A (en) * | 2014-12-22 | 2016-06-29 | 大陆汽车有限公司 | Interface module |
| CN106445853A (en) * | 2016-08-30 | 2017-02-22 | 天津天地伟业数码科技有限公司 | Transformation method of SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver/Transmitter) interface on the basis of FPGA (Field Programmable Gate Array) |
| CN106569973A (en) * | 2016-10-25 | 2017-04-19 | 深圳市科陆精密仪器有限公司 | Serial peripheral interface multiplexing method and communication system |
| CN109213716A (en) * | 2018-08-29 | 2019-01-15 | 郑州云海信息技术有限公司 | A kind of I2C bus unit and a kind of I2C signal protection method |
| CN109491945A (en) * | 2018-11-05 | 2019-03-19 | 深圳市瑞驰信息技术有限公司 | A kind of system and method for UART cascade extension |
| CN109756664A (en) * | 2017-11-08 | 2019-05-14 | 福州瑞芯微电子股份有限公司 | A kind of intelligent electronic device and image processing unit, device, method |
| CN110781117A (en) * | 2019-09-12 | 2020-02-11 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996021974A1 (en) * | 1995-01-11 | 1996-07-18 | Aristocrat Leisure Industries Pty. Ltd. | Serial peripheral interface |
| CN101246462A (en) * | 2008-03-26 | 2008-08-20 | 中兴通讯股份有限公司 | Periphery communication interface extension device and method |
| CN102541788A (en) * | 2010-12-27 | 2012-07-04 | 北京国睿中数科技股份有限公司 | APB (advanced peripheral bus) bridge and method for executing reading or writing by using APB bridge |
-
2012
- 2012-11-26 CN CN2012104926768A patent/CN102981996A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996021974A1 (en) * | 1995-01-11 | 1996-07-18 | Aristocrat Leisure Industries Pty. Ltd. | Serial peripheral interface |
| CN101246462A (en) * | 2008-03-26 | 2008-08-20 | 中兴通讯股份有限公司 | Periphery communication interface extension device and method |
| CN102541788A (en) * | 2010-12-27 | 2012-07-04 | 北京国睿中数科技股份有限公司 | APB (advanced peripheral bus) bridge and method for executing reading or writing by using APB bridge |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984268B (en) * | 2014-05-28 | 2016-11-23 | 大连美恒时代科技有限公司 | The input/output unit of a kind of signal logic controller and signal logic controller |
| CN103984268A (en) * | 2014-05-28 | 2014-08-13 | 大连美恒时代科技有限公司 | Input and output device of signal logic controller and signal logic controller |
| CN105720967B (en) * | 2014-12-22 | 2019-01-01 | 大陆汽车有限公司 | interface module |
| CN105720967A (en) * | 2014-12-22 | 2016-06-29 | 大陆汽车有限公司 | Interface module |
| CN104794088A (en) * | 2015-04-22 | 2015-07-22 | 成都为开微电子有限公司 | Multi-interface bus converting expanding chip design |
| CN104794088B (en) * | 2015-04-22 | 2018-05-01 | 成都为开微电子有限公司 | A kind of multiplex roles general line system extended chip design |
| CN104820644B (en) * | 2015-04-30 | 2018-07-27 | 武汉大学 | Multiplexed port method and device when a kind of overstepping one's bounds |
| CN104820644A (en) * | 2015-04-30 | 2015-08-05 | 武汉大学 | Non-time-sharing port multiplexing method and device |
| CN105045746A (en) * | 2015-09-09 | 2015-11-11 | 四川九洲电器集团有限责任公司 | Interface expanding device |
| CN105446929A (en) * | 2015-12-14 | 2016-03-30 | 武汉芯昌科技有限公司 | Port multiplexing circuit capable of supporting SPI, I2C, I2CL and UART protocols |
| CN106445853A (en) * | 2016-08-30 | 2017-02-22 | 天津天地伟业数码科技有限公司 | Transformation method of SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver/Transmitter) interface on the basis of FPGA (Field Programmable Gate Array) |
| CN106569973A (en) * | 2016-10-25 | 2017-04-19 | 深圳市科陆精密仪器有限公司 | Serial peripheral interface multiplexing method and communication system |
| CN106569973B (en) * | 2016-10-25 | 2019-09-17 | 深圳市科陆精密仪器有限公司 | Serial Peripheral Interface (SPI) multiplexing method and communication system |
| CN109756664B (en) * | 2017-11-08 | 2020-09-11 | 瑞芯微电子股份有限公司 | Intelligent electronic equipment and image processing unit, device and method |
| CN109756664A (en) * | 2017-11-08 | 2019-05-14 | 福州瑞芯微电子股份有限公司 | A kind of intelligent electronic device and image processing unit, device, method |
| CN109213716A (en) * | 2018-08-29 | 2019-01-15 | 郑州云海信息技术有限公司 | A kind of I2C bus unit and a kind of I2C signal protection method |
| CN109491945A (en) * | 2018-11-05 | 2019-03-19 | 深圳市瑞驰信息技术有限公司 | A kind of system and method for UART cascade extension |
| CN109491945B (en) * | 2018-11-05 | 2021-11-09 | 深圳市瑞驰信息技术有限公司 | UART cascade extension system and method |
| CN110781117A (en) * | 2019-09-12 | 2020-02-11 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
| CN110781117B (en) * | 2019-09-12 | 2020-11-20 | 广东高云半导体科技股份有限公司 | SPI expansion bus interface and system on chip based on FPGA |
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Application publication date: 20130320 |