CN102882534A - Parallel implementation method and device for reed-solomon (RS) code - Google Patents

Abstract

The invention discloses a parallel implementation method and a parallel implementation device for a reed-solomon (RS) code. The method comprises the following steps of: determining a generating polynomial G(x) of an RS code according to parameters m, n and k, judging whether k and (n-k) can be exactly divided by H; selecting a corresponding parallel code implementation structure according to the condition whether (n-k) can be exactly divided by H; calculating a coefficient of a constant coefficient multiplier in the parallel code implementation structure according to the generating polynomial G(x); determining whether zero-fill or zero-suppression processing is required according to the condition whether k can be exactly divided by H; determining control of feedback door control signal, and input enabling and output selection signals in the parallel code implementation structure according to the parameters n, k and H; and outputting a parallel coding result. The parallel implementation method and the parallel implementation device are suitable for the parallel implementation of an arbitrary RS code pattern on a Galois Field (GF)(2m) under arbitrary parallelism degree H (H is not greater than k).

Description

Parallel Implementation method and the device of RS coding

Affiliated technical field

The present invention relates to optical communication technique, be specifically related to Parallel Implementation method and the device of RS coding.

Background technology

Along with optical communication to ultrahigh speed, vast capacity future development, SDH (Synchronous Digital Hierarchy) (synchronous digital hierarchy, referred to as SDH) structure, Dense Waveleng Division Multiplexing (Dense Wavelength Division Multiplexing, referred to as DWDM) technology such as system, all optical network and optical cross connect constantly use in optical fiber telecommunications system, so that line speed reaches 10Gbps, 40Gbps and 100Gbps even higher.

The validity and reliability of transmission is conflict: on the one hand, the significantly raising of transmission rate, dispersion, nonlinear effect, receiver performance also becomes the principal element of system for restricting performance.On the other hand, the expansion of power system capacity also can cause a series of such as crosstalking between each road light signal, signal synchronously, regularly, the problem recovered, these problems all can cause the generation of error code in the communication process, thereby reduce the reliability of communication, the reduction of communication reliability has finally restricted again the raising of communication quality, the prolongation of communication distance, multiplexed large-scale application, and the reduction of communication equipment cost, has therefore greatly hindered further developing of optical communication.

Forward error correction (FEC) technology is one of key technology that addresses the above problem, the FEC technology increased certain redundant code according to certain coding rule by coding side before data send, do not produce correlation so that do not have the data of correlation originally, hold then according to decoding rule in decoding, utilize the redundant data that produce to correct the error code that produces in the channel, recover to send data, thereby reach Optical Signal To Noise Ratio (the optical signal to noise ratio that reduces receiving terminal, referred to as OSNR) tolerance limit, reduce the purpose of required transmitting power.The coding gain that adopts FEC to obtain, thereby greatly reduce the error rate, effectively improved communication reliability and reach the purpose of improving systematic function, reducing system cost, and reed-solomon (Reed-Solomon, referred to as RS) code multi-system Bo Sichadehulihuo elder brother lattice nurse code (the Bose Chaudhuri Hocquenghem that has very strong error correcting capability as a class, referred to as BCH), because of its good performance and high-throughput, be widely used in the various fields such as radio communication, light transmission.

At present, RS is coded in the method that usually adopts serial code when realizing, as shown in Figure 1, and among Fig. 1

Be d type flip flop,

With

Be respectively galois field GF(2 ^m) (Galois Field, referred to as GF, m is the integer greater than zero, determines that galois field is GF(2 ^m)) on multiplication of constant coefficient device and adder (being XOR gate),

Be the data selector of alternative, select to be output as information code element W or the verification code element C of input by the output_sel signal,

Be gate, feedback_gate and input_en signal are respectively as an input of two gates, whether be used for the information code element of control feedback signal and input by this gate, the implementation structure of method shown in Figure 1 mainly by (n-k) individual d type flip flop and (n-k) individual multiplication of constant coefficient device and (n-k) individual XOR gate forms the linear feedback shift register (Linear Feedback Shift Register is referred to as LFSR) of (n-k) grade.In the method, a code element and then code element is encoded, can only process a code element at every turn, need to carry out multi-shift and just can finish the cataloged procedure of a code word, this method not only code efficiency is not high, and the throughput of data is not high yet, is seriously restricting the raising of whole system transmission rate.

Summary of the invention

Technical problem to be solved by this invention is that solution RS code code efficiency is not high, the problem that restriction whole system transmission rate improves.

In order to solve the problems of the technologies described above, the technical solution adopted in the present invention provides a kind of Parallel Implementation method and device of RS coding, can a plurality of code elements of single treatment, significantly improved the efficient of RS code coding, and satisfy the requirement of whole system transmission rate.

The Parallel Implementation method of RS coding may further comprise the steps:

Determine the generator polynomial G (x) of RS code according to parameter m, n, k, m is the integer greater than zero, determines that galois field is GF(2 ^m), n is the length of RS code word, and k is the length of information bit in the RS code word, and H is the degree of parallelism of required realization;

Whether can be divided exactly each feedback loop progression of determining H route feedback shift register LFSR by H according to (n-k); When (n-k) can be divided exactly by H, described feedback loop progression was (n-k)/H; When (n-k) can not be divided exactly by H, feedback loop 0 to the feedback progression of feedback loop r is A1, feedback loop (r+1) is (H-A1) to the feedback progression of feedback loop (H-1), and A1 rounds downwards for (n-k)/H, and r is that (n-k) is divided by the remainder of H gained;

According to formula $x^{n-k+j}\≡{\mathrm{\Σ}}_{i=0}^{n-k-1}{g}_i^j{x}^i\mathrm{mod}G\left(x\right)$ Obtain the coefficient of each multiplication of constant coefficient device

I=0,1 ..., n-k-1; J=0,1 ..., H-1;

Whether can be divided exactly by H according to k, need determine whether zero padding and the processing of zero-suppressing, when k can not be divided exactly by H, mend (H-R) individual zero symbol through residue R code element front after T the processing; When k can be divided exactly by H, need not zero padding and zero-suppress processing; R is that k is divided by the remainder of H gained, k=T*H+R;

According to parameter n, k, H, determine that corresponding feedback door control signal, input enable and export the selection signal;

By H road LFSR output parallel encoding result.

In said method, described G (x) is according to parameter m, n, k and GF(2 ^m) the origin multinomial, in conjunction with tabling look-up or utilizing the matlab instrument to obtain.

In said method, utilize the matlab instrument to obtain the coefficient of described multiplication of constant coefficient device according to G (x)

The present invention also provides a kind of RS code device, comprises the individual GF(2 of H road LFSR and H * (n-k) ^m) on the multiplication of constant coefficient device, the described LFSR in each road of described H road LFSR has (n-k) individual XOR gate of being connected in series and (n-k) individual d type flip flop, described XOR gate and the setting of described d type flip flop interval; Every H LFSR is one group, the described H of connection road LFSR in order successively circulates take group as unit, when (n-k) can be divided exactly by H, the feedback loop progression of described LFSR is (n-k)/H, when (n-k) can not be divided exactly by H, the feedback loop progression of described LFSR is no longer consistent, feedback loop 0 to the feedback progression of feedback loop r is A1, A1=(n-k)/H rounds (A1 is for being not more than the maximum integer of (n-k)/H) downwards, feedback loop (r+1) is H-A1 to the feedback progression of feedback loop (H-1), and r is that (n-k) is divided by the remainder of H gained;

The individual GF(2 of H * (n-k) ^m) on the multiplication of constant coefficient device

The coefficient of each multiplication of constant coefficient device

According to formula

Determine; Wherein: m is the integer greater than zero, determines that galois field is GF(2 ^m); N is the length of RS code word; K is the length of information bit in the RS code word; H is the degree of parallelism of required realization; I=0,1 ..., n-k-1; J=0,1 ..., H-1.

The present invention compares with traditional coding method and prior art, can a parallel processing H code element, yet computing consumption or hardware realize resource and can linearly not increase, the more important thing is, this structure or method go for GF(2 ^m) upper any RS pattern is not more than k at any degree of parallelism H(H) and under Parallel Implementation, thereby have great flexibility.

Description of drawings

Fig. 1 is existing GF(2 ^m) the upper schematic diagram of realizing the RS code device;

Fig. 2 is the flow chart of RS provided by the invention coding Parallel Implementation method;

Fig. 3 is RS code device the first execution mode schematic diagram provided by the invention;

Fig. 4 is RS code device the second execution mode schematic diagram provided by the invention;

Fig. 5 is the local detail schematic diagram of Fig. 4;

Fig. 6 is the course of work of the RS code device of Parallel Implementation;

Instantiation schematic diagram when Fig. 7 is the second execution mode H=7 shown in Figure 4.

Embodiment

Below in conjunction with accompanying drawing the present invention is made detailed explanation.

RS coding Parallel Implementation method provided by the invention may further comprise the steps as shown in Figure 2:

Whether step S10 determines the generator polynomial G (x) of RS code according to parameter m, n, k, and judge k and (n-k) can be divided exactly by H.Wherein: m is the integer greater than zero, determines that galois field is GF(2 ^m), n is the length of RS code word, and k is the length of information bit in the RS code word, and H is the degree of parallelism of required realization, namely needs the code element number of encoder single treatment.G (x) can be according to parameter m, n, k and GF (2 ^m) the origin multinomial, in conjunction with tabling look-up or utilizing matlab or other instrument to generate.

Whether step S20 can be divided exactly each feedback loop progression of determining H road LFSR by H according to (n-k), thereby determines to select corresponding parallel encoding implementation structure.

When (n-k) can be divided exactly by H, its implementation structure as shown in Figure 3, wherein the feedback loop progression of LFSR is (n-k)/H.Among Fig. 3:

Be d type flip flop,

With

Be respectively GF(2 ^m) on multiplication of constant coefficient device and adder (being XOR gate), Be the data selector of alternative, select to be output as information code element W or the verification code element C of input by the output_sel signal,

Be gate, whether feedback_gate and input_en signal are used for the information code element of control feedback signal and input by this gate as an input of two gates respectively.The individual GF(2 of (n-k) individual d type flip flop, H * (n-k) wherein ^m) on multiplication of constant coefficient device and (n-k) individual GF(2 ^m) on two input summers and (n-k) individual GF(2 ^m) on the H input summer combine consisted of H the displacement feedback loop, every loop, this H loop all can be seen the LFSR of (n-k)/H level as, final stage output state by LFSR between the loop is connected with each other, the LFSR concurrent working of H road.Like this when Parallel Implementation device shown in Figure 3 carries out a shifting function, be equivalent to existing serial code device shown in Figure 1 and carried out H shifting function, therefore, H information code element can be sent in the parallel encoding device shown in Figure 3 simultaneously, thereby can once be finished the parallel processing of H information code element.

When (n-k) can not be divided exactly by H, its implementation structure is shown in Fig. 4,5, different from Parallel Implementation device shown in Figure 3 is: in H the LFSR loop, the number of shift register stages in every loop is no longer consistent, feedback loop 0 to the feedback progression of feedback loop r is A1, A1=(n-k)/H rounds downwards, and feedback loop (r+1) is H-A1 to the feedback progression of feedback loop (H-1), and r is that (n-k) is divided by the remainder of H gained.

S30 is according to the coefficient of multiplication of constant coefficient device in generator polynomial G (x) calculating chart 3 or the Parallel Implementation device shown in Figure 4

I=0,1 ..., n-k-1; J=0,1 ..., H-1.As shown in Figure 3 and Figure 4, the individual GF(2 of a total H in the Parallel Implementation device * (n-k) ^m) on the multiplication of constant coefficient device, the individual coefficient of H * (n-k) need to be arranged

According to formula

Calculate by coding or other instruments.

Whether S40 can be divided exactly by H according to k, need to determine whether zero padding and the processing of zero-suppressing;

When k can not be divided exactly by H, make that R is the remainder that k obtains divided by H, the Parallel Implementation device is processed H code element at every turn, so after T processing, (wherein R is that k is divided by the remainder of H gained can to remain R code element, be k=T * H+R), need to be in a code word W (k-1) before encoding this moment at every turn, ..., W (1), the high position of k the code elements such as W (0) is mended (H-R) individual zero symbol, so just code element number in the code word of input can be gathered into (k+H-R), can be divided exactly by H, because the state of LFSR is zero in the Parallel Implementation device before encoding, therefore the coding result that can not affect a back k information code element is processed in zero padding, just when output, need correspondingly will before the zero symbol of benefit remove.When k can be divided exactly by H, need not zero padding and zero-suppress processing.

S50 according to n, k, H parameter, determines feedback door control signal, input in the Parallel Implementation device are enabled and export the control of selecting signal;

In concrete the application, when coding enables when invalid, the Parallel Implementation device need to carry out former state output to data, and the feedback gate-control signal feedback_gate shown in this moment Fig. 3 and Fig. 4 is invalid, it is invalid that input enables input_en, and output selects signal output_sel to select to be output as the input data; When coding enables when effective, the Parallel Implementation device is finished the cataloged procedure needs of a code word

Inferior feedback shift is front

In the inferior shifting process, feedback_gate is effective for the feedback gate-control signal, and it is effective that input enables input_en, and output selects signal output_sel to select to be output as the input data, ensuing

In the inferior shifting process, gate-control signal feedback_gate is still effective for feedback, and it is invalid that input enables input_en, and output selects signal output_sel to select to be output as the LFSR State-output.

S60 is by H road LFSR output parallel encoding result.

Step S60 comprises following steps:

S601: the input data are carried out zero padding process (note zero padding processing module herein whether determine in the concrete application needs according to step S40 in the above-mentioned Parallel Implementation flow process);

S602: after the process zero padding is processed afterwards or with the zero padding processing

Individual information code element is divided into

Group, every group of H information code element, send into successively in Fig. 3 or the structure shown in Figure 4, send into one group of H code element at every turn, the parallel LFSR in H road in the encoder carries out a shifting function simultaneously, it is effective that feed back gate-control signal feedback_gate this moment, simultaneously output selects signal output_sel to select to be output as the input data, what therefore encoder was exported in this process is the information code element of input, here process corresponding with zero padding, for some situation, may be also need will output the information code element processing of zero-suppressing;

Afterbody H the output q of each loop neutral line feedback shift register LFSR _N-k-1, q _N-k-2..., q _N-k-H-1, q _N-k-HWith corresponding input W (k-1) ..., W (1), W (0) is through GF(2 ^m) on add operation (XOR) after feed back to corresponding constant multiplier, pass through again multiplication and add operation after, feed back to the different progression of the shift register in corresponding loop, thereby change the state of linear feedback shift register.

S603: process After the inferior shifting function, after zero padding is processed or after not processing through zero padding

Individual information code element has all moved in the encoder, and encoder input this moment input_en enables to close, and no longer moves into information code element, and output selects signal output_sel to select to be output as the LFSR State-output, in this process, encoder can with

Individual verification code element shifts out successively.

Therefore, see on the whole, in input In the time of individual information code element, the RS encoder also can be exported successively

Individual information code element and corresponding

Individual verification code element.

The first execution mode of RS code device provided by the invention as shown in Figure 3, this device comprises:

H road LFSR, the described LFSR in each road has (n-k) individual XOR gate of being connected in series and (n-k) individual d type flip flop, described XOR gate and described d type flip flop interval arrange, every H LFSR is one group, the described H of connection road LFSR in order successively circulates take group as unit, (n-k) can be divided exactly by H, and the feedback loop progression of described LFSR is (n-k)/H.

The individual GF(2 of H * (n-k) ^m) on the multiplication of constant coefficient device

The coefficient of each multiplication of constant coefficient device

According to formula

Determine.Wherein: m is the integer greater than zero, determines that galois field is GF(2 ^m); N is the length of RS code word; K is the length of information bit in the RS code word; H is the degree of parallelism of required realization; I=0,1 ..., n-k-1; J=0,1 ..., H-1.

Gate is used for the control to whole code device, comprises whether inputting data, and whether LFSR feeds back, and selecting the output data is information code element or verification code element.

Fig. 4 is the second execution mode schematic diagram of RS code device provided by the invention, as shown in Figure 4, the difference of this execution mode and the first execution mode is: (n-k) can not be divided exactly by H, therefore feedback loop 0 to the feedback progression of feedback loop r is A1, feedback loop (r+1) to the feedback progression of feedback loop (H-1) is (H-A1), A1 rounds downwards for (n-k)/H, and r is that (n-k) is divided by the remainder of H gained.

Below in conjunction with example GF(2 ⁸) on the Parallel Implementation of RS (248,216) encoder under degree of parallelism H=7 be elaborated, as shown in Figure 7.

In this example, the exponent number m=8 of galois field, RS code code length n=248, k=216 is the shortening code of RS (255,223), degree of parallelism H=7, the each displacement of parallel encoder that realizes can be processed 7 code elements (each code element 8bit binary number), 56bit namely, and its specific implementation step is as follows:

Step S10: according to parameter m, n, k determine the generator polynomial G (x) of RS code (generator polynomial can be according to GF (2 here ⁸) the origin multinomial in conjunction with tabling look-up or utilizing matlab or other instrument to obtain, just repeat no more here), k=216 simultaneously, n-k=32, H=7, k and (n-k) all can not being divided exactly by H.

Step S20: because n-k=32, H=7 (n-k) can not be divided exactly by H, thereby should select implementation structure shown in Figure 4.

Step S30: according to the generator polynomial G (x) of the RS code of determining among the step S10, and the formula described in the summary of the invention 1, calculate GF (2 in the structure shown in Figure 4 ⁸) coefficient of upper multiplication of constant coefficient device I=0 wherein, 1 ..., 31, j=0,1 ..., 6, one have 192 coefficient (coefficients here

Can use matlab or other instrument to calculate).

Step S40: because k=216, H=7, k can not be divided exactly by H, therefore need to carry out the zero padding operation to the input data, and k=216 is 6 divided by H=7 gained remainder, so need to mend 1 zero symbol (each code element 8bit binary number), so just obtain 217 information code elements (comprising 1 zero symbol), similarly, for the information code element operation of also will zero-suppressing of output, 1 zero symbol of before introducing is removed.

Step S50: when coding enables when invalid, encoder need to carry out former state output to data, and the feedback gate-control signal feedback_gate shown in this moment Fig. 4 is invalid, and output selects signal output_sel to select to be output as the input data; When coding enables when effective, the code word of cataloged procedure finish to(for) the encoder in this example needs 36 feedback shifts, feedback gate-control signal feedback_gate is effective in front 31 shifting processes, output selects signal output_sel to select to be output as the input data, what exported this moment is information code element, in ensuing 5 shifting processes, feedback_gate is still effective for the feedback gate-control signal, output selects signal output_sel to select to be output as the LFSR State-output, and what exported this moment is the verification code element.

Comprehensive above-described six steps, can obtain RS (248 as shown in Figure 6,216) parallel realization structure of encoder under degree of parallelism H=7, in this structure, one total H=7 displacement feedback loop worked simultaneously, the progression of the linear feedback shift register LFSR in each loop is 5 or 4, the register of total total n-k=32 m=8bit, be equivalent to 32 grades of LFSR of work in series in traditional implementation are split into 45 grades LFSR of concurrent working and 34 grades LFSR, the final stage output state by each loop between these 7 LFSR loops is connected with each other.In this example, k can not be divided exactly by H, thereby will carry out zero padding for the input message code element and process, in the output processing of also correspondingly zero-suppressing, in addition, n in this example can not be divided exactly by H, in actual applications, each timeticks is processed H code element, so during for the continuous processing of a plurality of code words, last several code elements of each code word need to form a beat of data with the several code elements in the front of next code word, also will consider the Bonding Problem between the code word.

The present invention is not limited to above-mentioned preferred forms, and anyone should learn the structural change of making under enlightenment of the present invention, and every have identical or close technical scheme with the present invention, all falls within protection scope of the present invention.

Claims (5)

1.RS the Parallel Implementation method of coding is characterized in that, may further comprise the steps:

Determine the generator polynomial G (x) of RS code according to parameter m, n, k, m is the integer greater than zero, determines that galois field is GF(2 ^m), n is the length of RS code word, and k is the length of information bit in the RS code word, and H is the degree of parallelism of required realization;

Whether can be divided exactly each feedback loop progression of determining H route feedback shift register LFSR by H according to (n-k); When (n-k) can be divided exactly by H, described feedback loop progression was (n-k)/H; When (n-k) can not be divided exactly by H, feedback loop 0 to the feedback progression of feedback loop r is A1, feedback loop (r+1) is (H-A1) to the feedback progression of feedback loop (H-1), and A1 rounds downwards for (n-k)/H, and r is that (n-k) is divided by the remainder of H gained;

According to formula Obtain the coefficient of each multiplication of constant coefficient device

I=0,1 ..., n-k-1; J=0,1 ..., H-1;

Whether can be divided exactly by H according to k, need determine whether zero padding and the processing of zero-suppressing, when k can not be divided exactly by H, mend (H-R) individual zero symbol through residue R code element front after T the processing; When k can be divided exactly by H, need not zero padding and zero-suppress processing; R is that k is divided by the remainder of H gained, k=T*H+R;

According to parameter n, k, H, determine that corresponding feedback door control signal, input enable and export the selection signal;

By H road LFSR output parallel encoding result.

2. the Parallel Implementation method of RS coding as claimed in claim 1 is characterized in that,

Described G (x) is according to parameter m, n, k and GF(2 ^m) the origin multinomial, in conjunction with tabling look-up or utilizing the matlab instrument to obtain.

3. the Parallel Implementation method of RS coding as claimed in claim 1 is characterized in that,

Utilize the matlab instrument to obtain the coefficient of described multiplication of constant coefficient device according to G (x)

4.RS code device is characterized in that, comprising:

H road LFSR, the described LFSR in each road have (n-k) individual XOR gate of being connected in series and (n-k) individual d type flip flop, described XOR gate and the setting of described d type flip flop interval;

The individual GF(2 of H * (n-k) ^m) on the multiplication of constant coefficient device, every H LFSR is one group, take group as unit in order successively circulation connect described H road LFSR; (n-k) can be divided exactly by H, and the feedback loop progression of described LFSR is (n-k)/H the coefficient of each multiplication of constant coefficient device According to formula $x^{n-k+j}\≡{\mathrm{\Σ}}_{i=0}^{n-k-1}{g}_i^j{x}^i\mathrm{mod}G\left(x\right)$ Determine;

Wherein: m is the integer greater than zero, determines that galois field is GF(2 ^m); N is the length of RS code word; K is the length of information bit in the RS code word; H is the degree of parallelism of required realization; I=0,1 ..., n-k-1; J=0,1 ..., H-1.

5.RS the Parallel Implementation device of coding is characterized in that, comprising:

H road LFSR, the described LFSR in each road have (n-k) individual XOR gate of being connected in series and (n-k) individual d type flip flop, described XOR gate and the setting of described d type flip flop interval;

The individual GF(2 of H * (n-k) ^m) on the multiplication of constant coefficient device, every H LFSR is one group, take group as unit in order successively circulation connect described H road LFSR; (n-k) can not be divided exactly by H, and feedback loop 0 to the feedback progression of feedback loop r is A1, feedback loop (r+1) is (H-A1) to the feedback progression of feedback loop (H-1), and A1 rounds downwards for (n-k)/H, and r is that (n-k) is divided by the remainder of H gained; The coefficient of each multiplication of constant coefficient device

According to formula $x^{n-k+j}\≡{\mathrm{\Σ}}_{i=0}^{n-k-1}{g}_i^j{x}^i\mathrm{mod}G\left(x\right)$ Determine;

Wherein: m is the integer greater than zero, determines that galois field is GF(2 ^m); N is the length of RS code word; K is the length of information bit in the RS code word; H is the degree of parallelism of required realization; I=0,1 ..., n-k-1; J=0,1 ..., H-1.

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