CN102857238B - LDPC (Low Density Parity Check) encoder and encoding method based on summation array in deep space communication - Google Patents

Abstract

The invention relates to a scheme of solving parallel encoding of nine QC-LDPC (Quasi-Cyclic-Low Density Parity Check) codes in a CCSDS (Consultative Committee for Space Data Systems) deep space communication system, which is characterized in that a parallel encoder of the QC-LDPC codes in the system is mainly composed of four parts of a register, a summation array, a selecting expander and a b-digit 2-input exclusive-or gate. The QC-LDPC parallel encoder provided by the invention is compatible with a multi-code rate, and resource requirements can be effectively reduced in the condition that the encoding speed is kept unchanged. The QC-LDPC parallel encoder has the advantages of simple control, less resource consumption, little power consumption, low cost and the like.

Description

Based on LDPC encoder and coding method in the deep space communication of sum array

Technical field

The present invention relates to deep space data communication field, particularly a kind of Parallel Implementation method of QC-LDPC code coder in CCSDS deep space communication system.

Background technology

Because the various distortion that exists in transmission channel and noise can produce interference to transmission signal, receiving terminal inevitably digital signal produces the situation of error code.In order to reduce the error rate, need to adopt channel coding technology.

Low-density checksum (Low-Density Parity-Check, LDPC) code becomes the study hotspot of field of channel coding with the excellent properties that it approaches Shannon limit.Quasi-cyclic LDPC code (Quasic-LDPC, QC-LDPC) code is a kind of special LDPC code, and its coding can adopt shift register to add accumulator (Shift-Register-Adder-Accumulator, SRAA) and be realized.

SRAA method utilizes generator matrix G to encode.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array that (1≤i≤a, 1≤j≤t) is formed, t=a+c.The a part of generator matrix corresponding with information vector is unit matrix, and the remainder generator matrix corresponding with verification vector is high-density matrix.Suppose that a is not prime number, can a=ux(u≤x be broken down into), wherein, u is not equal to 1, x and is not equal to a.So, the u road SRAA method that walks abreast completes first encoding and needs bx+t clock cycle, needs (uc+t) b register, ucb two inputs to input XOR gate with door and ucb individual two.In addition, acb bit ROM is also needed to store the first trip of circular matrix.

CCSDS deep space communication system recommendation 9 kinds of QC-LDPC codes, wherein code check η is divided into 1/2,2/3 and 4/5 3 kind, square formation exponent number b is divided into 32,64,128,256,512,1024 and 2,048 seven kinds.As shown in Figure 1, η and b has 9 kinds of efficient combination (η, b): (4/5,32), (2/3,64), (1/2,128), (4/5,128), (2/3,256), (1/2,512), (4/5,512), (2/3,1024) and (1/2,2048), corresponding 9 kinds of QC-LDPC codes.For all QC-LDPC codes, all have c=12, the greatest common divisor of all a is u=8.Fig. 2 gives parameter a, t and x under different code check η.

In CCSDS deep space communication system, the existing solution of QC-LDPC high spped coding adopts u=8 road to walk abreast SRAA method, and the scramble time needed for 9 kinds of QC-LDPC codes is 172,156,148,556,540,532,2092,2076 and 2068 clock cycle respectively.Logical resource needs 237568 registers, 196608 two inputs input XOR gate with door and 196608 two, and this is determined by the parameter that (η, b)=(1/2,2048) are corresponding.In addition, 9 kinds of QC-LDPC codes need 774 altogether, and 144 bit ROM store the first trip of circular matrix.When adopting hardware implementing, need more memory and register, equipment cost will certainly be caused high, and power consumption is large.

Summary of the invention

The large shortcoming of resources requirement existed in existing implementation for CCSDS deep space communication system multiple QC-LDPC code high spped coding, the invention provides a kind of parallel encoding method based on sum array, can keep, under the prerequisite that coding rate is constant, reducing resource requirement.

As shown in Figure 3, in CCSDS deep space communication system, the parallel encoder of multiple QC-LDPC code forms primarily of 4 parts: register, sum array, selection expander and b position two input XOR gate.Whole cataloged procedure divides 4 steps to complete: the 1st step, and input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t, and for selecting expander M _l(1≤l≤c) configures appropriate code check η and square formation exponent number b; 2nd step, register R ₁~ R _aserial moves to left 1 time, for sum array walks abreast input vector (s _{1, k}, s _{2, k}..., s _u,k) (1≤k≤bx), control end input ρ=[(k-1)/b]+1(symbol [(k-1)/b] of all selection expanders represents the maximum integer being not more than (k-1)/b), all selection expanders are selected a part respectively and are extended to b from the output of sum array, jointly form vector (s _{1, k}, s _{2, k}..., s _u,k) product of the sub-block first trip matrix F ρ corresponding with efficient combination (η, b), b position two inputs XOR gate A _l(1≤l≤c) is by the l section b bit of product and register R _a+lserial loop moves to left the results added of 1 time, and deposits back register R _a+l; 3rd step, with 1 for step-length increases progressively the value changing k, repeats the 2nd step bx time; 4th step, parallel output code word v=(s, p).

The compatible multi code Rate of Chinese character of QC-LDPC parallel encoder provided by the invention, can keep effectively reducing resource requirement under the constant prerequisite of coding rate, thus reach the object reducing hardware cost and power consumption.

Be further understood by ensuing detailed description and accompanying drawings about the advantages and spirit of the present invention.

Accompanying drawing explanation

Fig. 1 gives the efficient combination (η, b) of code check η and square formation exponent number b;

Fig. 2 gives parameter a, t and x under different code check η;

Fig. 3 is the parallel encoder overall structure of compatible 9 kinds of QC-LDPC codes in CCSDS deep space communication system;

Fig. 4 is the formation schematic diagram of sum array;

Fig. 5 gives the quantity of various multi input XOR gate;

Fig. 6 compares traditional u road and to walk abreast SRAA method and resource consumption of the present invention.

Embodiment

Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as a limitation of the invention.

QC-LDPC code is the special LDPC code of a class, and its generator matrix G and check matrix H are all the arrays be made up of circular matrix, have stages cycle feature, therefore are called as quasi-cyclic LDPC code.From the angle of row, each provisional capital of circular matrix is the result of lastrow (first trip is footline) ring shift right one; From the angle of row, each row of circular matrix are all the results that previous column (first is terminal column) circulation moves down.The set that the row vector of circular matrix is formed is identical with the set that column vector is formed, and therefore, circular matrix can be characterized by its first trip or first completely.The generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array that (1≤i≤a, 1≤j≤t) is formed:

G(or H) continuous b capable and b row be called as the capable and block row of block respectively.Suppose g _i,j(1≤i≤a, a+1≤j≤t) is circular matrix G _i,jfirst trip, so can define a × bc rank block first trip matrix F in the following manner:

F is made up of the first trip of all circular matrixes during c block after generator matrix G arranges, and can be considered to be made up of bc a dimensional vector.Suppose that a is not prime number, can a=ux(u≤x be broken down into), wherein, u is not equal to 1, x and is not equal to a.So, u (ρ-1)+1 ~ u ρ (1≤ρ≤x) row of block first trip matrix F constitutes u × bc rank matrix, is referred to as sub-block first trip matrix, is denoted as F _ρ.F _ρcan be considered and to be made up of bc u dimensional vector.

For CCSDS deep space communication system, the corresponding code word v=(s, p) of generator matrix G, that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification.Be one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a); Verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c).For i-th (1≤i≤a) segment information vector s _i, have s _i=(s _{i, 1}, s _{i, 2}..., s _i,b).As shown in Figure 1, CCSDS deep space communication system have employed 9 kinds of QC-LDPC codes, and wherein code check η is divided into 1/2,2/3 and 4/5 3 kind, and square formation exponent number b is divided into 32,64,128,256,512,1024 and 2,048 seven kinds.η and b has 9 kinds of efficient combination (η, b): (4/5,32), (2/3,64), (1/2,128), (4/5,128), (2/3,256), (1/2,512), (4/5,512), (2/3,1024) and (1/2,2048).For all QC-LDPC codes, all have c=12, the greatest common divisor of all a is u=8.Fig. 2 gives parameter a, t and x under different code check η.

By the feature of formula (1), (2) and circular matrix, Fig. 3 gives the parallel encoder being applicable to 9 kinds of QC-LDPC codes in CCSDS deep space communication system, and it inputs XOR gate four kinds of functional module compositions primarily of register, sum array, selection expander and b position two.

Register R ₁~ R _afor cache information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c).

Sum array is to the u position information bit s of parallel input _{1, k}, s _{2, k}..., s _u,k(1≤k≤bx) sues for peace, and specifically, is therefrom choose m(1≤m≤u) individual different element carries out mould 2 and adds.From permutation and combination knowledge, exhaustively obtain 2 ^uthe individual different summation expression formula of-1=255.255 summation expression formulas can be realized by 255 multi input XOR gate.The input number range of multi input XOR gate is 1 ~ 8, and when only having an input, single input XOR gate is actually direct-connected line.To sum up, sum array has u=8 input and 255 outputs, and its inside is made up of 255 multi input XOR gate, as shown in Figure 4.Fig. 5 gives the quantity of various multi input XOR gate, and they are equivalent to 769 two input XOR gate altogether.

Select expander M _l(1≤l≤c) is controlled by code check η, square formation exponent number b and sub-block first trip matrix F _ρsubscript ρ (1≤ρ≤x).ρ and vector (s _{1, k}, s _{2, k}..., s _u,k) pass of (1≤k≤bx) is that ρ=[(k-1)/b]+1(symbol [(k-1)/b] represents the maximum integer being not more than (k-1)/b).Select expander M _lon the basis of sum array operation result, complete vector (s according to code check η and square formation exponent number b _{1, k}, s _{2, k}..., s _u,k) (1≤k≤bx) and sub-block first trip matrix F _ρthe parallel multiplication of (1≤ρ≤x).Select expander M _lfrom the output of sum array, select a part and be extended to b, to form vector (s _{1, k}, s _{2, k}..., s _u,k) and sub-block first trip matrix F _ρthe l section b bit of product, selection mode depends on the sub-block first trip matrix F that efficient combination (η, b) is corresponding completely _ρbc column vector.

B position two inputs XOR gate A _l(1≤l≤c) is by vector (s _{1, k}, s _{2, k}..., s _u,k) (1≤k≤bx) and sub-block first trip matrix F _ρthe l section b bit of product is added to register R _a+lin.

The invention provides a kind of parallel encoding method of variable bit rate QC-LDPC code, in conjunction with the parallel encoder (as shown in Figure 3) of QC-LDPC code multiple in CCSDS deep space communication system, its coding step is described below:

1st step, input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t, and for selecting expander M _l(1≤l≤c) configures appropriate code check η and square formation exponent number b;

2nd step, register R ₁~ R _aserial moves to left 1 time, for sum array walks abreast input vector (s _{1, k}, s _{2, k}..., s _u,k) (1≤k≤bx), control end input ρ=[(the k-1)/b]+1 of all selection expanders, all selection expanders are selected a part respectively and are extended to b from the output of sum array, jointly form vector (s _{1, k}, s _{2, k}..., s _u,k) the sub-block first trip matrix F corresponding with efficient combination (η, b) _ρproduct, b position two inputs XOR gate A _l(1≤l≤c) is by the l section b bit of product and register R _a+lserial loop moves to left the results added of 1 time, and deposits back register R _a+l;

3rd step, with 1 for step-length increases progressively the value changing k, repeats the 2nd step bx time, after completing, and register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c);

4th step, parallel output code word v=(s, p).

Be not difficult to find out from above step, whole cataloged procedure needs bx+t clock cycle altogether, and this and the traditional u road SRAA method that walks abreast is identical.

Fig. 6 compares traditional u road and to walk abreast SRAA method and resource consumption of the present invention.Note, will the basic selected cell of expander be selected to be considered as one two input and door here.Can know from Fig. 6 and see, compared with parallel SRAA method, advantage of the present invention is without the need to memory, employ less register, XOR gate and with door, consumption is 17%, 13% and 13% of parallel SRAA method respectively.

As fully visible, walk abreast compared with SRAA method with traditional u road, the present invention maintains coding rate, have control simple, resource consumption is few, power consumption is little, low cost and other advantages.

Above-described embodiment, just the present invention's more preferably embodiment, the usual change that those skilled in the art carries out within the scope of technical solution of the present invention and replacement all should be included in protection scope of the present invention.

Claims (5)

1. one kind is suitable for the parallel encoder of 9 kinds of QC-LDPC codes that CCSDS deep space communication system adopts, CCSDS is the English abbreviation of international space data system Advisory Board, English full name is Consultative Committee for Space DataSystems, and the generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t and b is all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, and 3 kinds of different code check η are 1/2 respectively, 2/3, 4/5,7 kinds of square formation exponent number b are 32 respectively, 64, 128, 256, 512, 1024, 2048,9 kinds of efficient combination (η, b) are (4/5,32) respectively, (2/3,64), (1/2,128), (4/5,128), (2/3,256), (1/2,512), (4/5,512), (2/3,1024) and (1/2,2048), for these 9 kinds of QC-LDPC codes, all have c=12, and the parameter a that 3 kinds of different code checks are corresponding is 8 respectively, 16, 32,3 kinds of parametric t that different code check is corresponding are 20 respectively, 28, the greatest common divisor of 44,3 kinds of a is u=8, a=ux, and the parameter x that 3 kinds of different code checks are corresponding is 1 respectively, 2, 4, generator matrix G corresponding code word v=(s, p), that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification, and be one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), the i-th segment information vector s _i=(s _{i, 1}, s _{i, 2}..., s _i,b), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described encoder comprises following parts:

Register R ₁~ R _t, register R ₁~ R _afor cache information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tfor calculating and store the vectorial p=(p of verification ₁, p ₂..., p _c);

Sum array, to the u position information bit s of parallel input _{1, k}, s _{2, k}..., s _u,kcarry out combination summation, wherein, 1≤k≤bx;

Select expander M ₁~ M _c, on the basis of sum array operation result, complete vector (s according to code check η and square formation exponent number b _{1, k}, s _{2, k}..., s _u,k) and sub-block first trip matrix F _ρparallel multiplication, wherein, 1≤ρ≤x, ρ=[(k-1)/b]+1, symbol [(k-1)/b] represents and is not more than the maximum integer of (k-1)/b;

B position two inputs XOR gate A ₁~ A _c, A _lby vector (s _{1, k}, s _{2, k}..., s _u,k) and sub-block first trip matrix F _ρthe l section b bit of product is added to register R _a+lin, wherein, 1≤l≤c.

2. parallel encoder as claimed in claim 1, is characterized in that, described sub-block first trip matrix F _ρbe by the capable u × bc rank matrix formed of u (ρ-1)+1 ~ u ρ of block first trip matrix F, and block first trip matrix F is made up of the first trip of all circular matrixes in c block row after generator matrix G.

3. parallel encoder as claimed in claim 1, it is characterized in that, described sum array has u input and 255 outputs, and sum array is to the u position information bit s of parallel input _{1, k}, s _{2, k}..., s _u,kcarry out combination summation, all sub-block first trip matrixes have 255 different non-zero column vectors, they and vector (s _{1, k}, s _{2, k}..., s _u,k) corresponding 255 the summation expression formulas of inner product, these summation expression formulas 255 multi input XOR gate are realized.

4. parallel encoder as claimed in claim 1, is characterized in that, described selection expander M _laccording to code check η, square formation exponent number b and sub-block first trip matrix F _ρsubscript ρ from the output of sum array, select a part and be extended to b, to form vector (s _{1, k}, s _{2, k}..., s _u,k) and sub-block first trip matrix F _ρthe l section b bit of product, selection mode depends on the sub-block first trip matrix F that efficient combination (η, b) is corresponding completely _ρbc column vector.

5. one kind is suitable for the parallel encoding method of 9 kinds of QC-LDPC codes that CCSDS deep space communication system adopts, CCSDS is the English abbreviation of international space data system Advisory Board, English full name is Consultative Committee for SpaceData Systems, and the generator matrix G of QC-LDPC code is by a × t b × b rank circular matrix G _i,jthe array formed, wherein, a, t and b is all positive integer, t=a+c, 1≤i≤a, 1≤j≤t, and 3 kinds of different code check η are 1/2 respectively, 2/3, 4/5,7 kinds of square formation exponent number b are 32 respectively, 64, 128, 256, 512, 1024, 2048,9 kinds of efficient combination (η, b) are (4/5,32) respectively, (2/3,64), (1/2,128), (4/5,128), (2/3,256), (1/2,512), (4/5,512), (2/3,1024) and (1/2,2048), for these 9 kinds of QC-LDPC codes, all have c=12, and the parameter a that 3 kinds of different code checks are corresponding is 8 respectively, 16, 32,3 kinds of parametric t that different code check is corresponding are 20 respectively, 28, the greatest common divisor of 44,3 kinds of a is u=8, a=ux, and the parameter x that 3 kinds of different code checks are corresponding is 1 respectively, 2, 4, generator matrix G corresponding code word v=(s, p), that the front a block row of G are corresponding is information vector s, and that rear c block row are corresponding is the vectorial p of verification, and be one section with b bit, information vector s is divided into a section, i.e. s=(s ₁, s ₂..., s _a), the i-th segment information vector s _i=(s _{i, 1}, s _{i, 2}..., s _i,b), verify vectorial p and be divided into c section, be i.e. p=(p ₁, p ₂..., p _c), it is characterized in that, described coding method comprises the following steps:

1st step, input information vector s, is saved to register R ₁~ R _a, reset register R _a+1~ R _t, and for selecting expander to configure appropriate code check η and square formation exponent number b;

2nd step, register R ₁~ R _aserial moves to left 1 time, for sum array walks abreast input vector (s _{1, k}, s _{2, k}..., s _u,k), control end input ρ=[(the k-1)/b]+1 of all selection expanders, all selection expanders are selected a part respectively and are extended to b from the output of sum array, jointly form vector (s _{1, k}, s _{2, k}..., s _u,k) the sub-block first trip matrix F corresponding with efficient combination (η, b) _ρproduct, b position two inputs XOR gate A _lby the l section b bit of product and register R _a+lserial loop moves to left the results added of 1 time, and deposits back register R _a+l;

3rd step, with 1 for step-length increases progressively the value changing k, repeats the 2nd step bx time, after completing, and register R ₁~ R _athat store is information vector s=(s ₁, s ₂..., s _a), register R _a+1~ R _tthat store is the vectorial p=(p of verification ₁, p ₂..., p _c);

4th step, parallel output code word v=(s, p).