KR20080050957A - Apparatus and method of encoding/decoding block low density parity check codes in a communication system - Google Patents

Abstract

A method and an apparatus for encoding/decoding low density parity check codes in a communication system are provided to minimize complexity of an encoding/decoding portion by supporting various coding rates using a single parity check matrix. A signal transmitting apparatus includes an encoder(111), a modulator(113), and a transmitter(115). When an information vector to be transmitted is generated in the signal transmitting apparatus, the information vector is delivered to the encoder. The encoder encodes the information vector according to a predetermined encoding scheme and generates an LDPC(Low Density Parity Check) codeword. The LDPC codeword is outputted to the modulator. The modulator modulates the codeword vector according to the predetermined modulation scheme to generate a modulation vector. The modulation vector is outputted to the transmitter. The transmitter receives the modulation vector from the modulator, processes a transmission signal, and outputs the transmission signal through an antenna.

Description

Apparatus and method for block low density parity check code encoding / decoding in communication system {APPARATUS AND METHOD OF ENCODING / DECODING BLOCK LOW DENSITY PARITY CHECK CODES IN A COMMUNICATION SYSTEM}

1 is a view showing the structure of a signal transmission apparatus according to an embodiment of the present invention

2 is a diagram illustrating the structure of a signal receiving apparatus according to an embodiment of the present invention;

3 illustrates a parity check matrix structure of a block LDPC code according to an embodiment of the present invention.

4 is a diagram of dividing the parity check matrix of FIG. 3 into six partial blocks.

FIG. 5 shows a transpose matrix of the partial matrix B of FIG. 4, a partial matrix E, a partial matrix T, and an inverse matrix of the partial matrix T. FIG.

6 illustrates a structure of a parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention.

7 illustrates a parity check matrix structure of a second type semi-structured block LDPC code according to an embodiment of the present invention.

8 is a diagram illustrating a structure of a child parity check matrix generated based on a parent parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention.

9 is a diagram illustrating a structure of a child parity check matrix generated based on a parent parity check matrix of a second type semi-structured block LDPC code according to an embodiment of the present invention.

FIG. 10 is a block diagram illustrating an example of an internal structure of the encoder 111 of FIG. 1.

11 is a block diagram showing the internal structure of the decoder 215 of FIG.

12A to 12H illustrate an example of a matrix corresponding to each partial block included in a parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 1/2. drawing

13A to 13G illustrate another example of a matrix corresponding to each partial block included in a parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 1/2. drawing

14A to 14B illustrate an example of a matrix corresponding to each partial block included in a parity check matrix of a second type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 5/6. drawing

15A to 15C illustrate an example of a matrix corresponding to each partial block included in a parity check matrix of a second type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 11/12. drawing

16A and 16B illustrate an example of a matrix corresponding to each partial block included in a parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 1/2;

17 is a block diagram illustrating another example of an internal structure of the encoder 111 of FIG. 1.

The present invention relates to an apparatus and method for encoding / decoding a block low density parity check (LDPC) code in a communication system.

The next generation communication system has been developed in the form of a packet service communication system, and the packet service communication system transmits bursted packet data to a plurality of mobile stations (MSs). The system has been designed to be suitable for high-speed mass data transmission and reception. In particular, in next-generation communication systems, a hybrid automatic repeat request (HARQ) scheme and an adaptive modulation and coding (AMC) scheme are used to support high-speed large data transmission and reception. Various schemes, such as the "AMC" scheme, have been proposed. In order to use the schemes such as the HARQ scheme and the AMC scheme, various coding rates must be supported.

In addition, in the next-generation communication system, it is known that the performance gain is excellent in high-speed data transmission together with a turbo code, and it is possible to effectively correct errors caused by noise generated in a transmission channel to increase the reliability of data transmission. The use of a block LDPC code with

However, the block LDPC code has a disadvantage in terms of coding rate. That is, the block LDPC code is disadvantageous in that it is not free in terms of coding rate because the generated codeword has a relatively high coding rate. Most of the block LDPC codes currently proposed have a code rate of 1/2, and only a part has a code rate of 1/3. Thus, in the case of the block LDPC code, there is a limitation in terms of the coding rate, which makes it unsuitable for high speed data transmission.

Of course, in order to achieve a relatively low coding rate, the order distribution showing the optimal performance may be obtained by using a density evolution method, but the block LDPC code having the order distribution indicating the optimal performance may be obtained. This is difficult due to various constraints such as cycle structure and hardware implementation on a bipartite (hereinafter referred to as 'bipartite') graph.

As described above, in the case of a block LDPC code, there is a limitation in terms of coding rate. Therefore, in a communication system using the block LDPC code, a method for transmitting and receiving signals by supporting various code rates from low to high code rates is provided. There is a need for it.

Accordingly, the present invention proposes an apparatus and method for encoding / decoding a block LDPC code in a communication system.

In addition, the present invention proposes a method for generating a parity check matrix of a block LDPC code in a communication system.

Hereinafter, with reference to the accompanying drawings in accordance with the present invention will be described in detail. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

Parity check matrix generation method proposed in the present invention; A method for generating a parity check matrix of a block low density parity check (LDPC) code in a communication system, comprising: a first parity check matrix and a second parity check matrix used for encoding an information vector into a block LDPC code; Generating at least one, wherein the first parity check matrix is generated using a second parity check matrix, the second parity check matrix comprises a plurality of blocks, wherein the plurality of blocks is the information vector. Blocks corresponding to the information part corresponding to the first block, blocks corresponding to the first parity part corresponding to the first parity vector, blocks corresponding to the second parity part corresponding to the second parity vector, and third When the information vector includes a first information vector and a second information vector, the information is classified into blocks corresponding to a third parity part corresponding to a parity vector. The blocks corresponding to the beam part are classified into blocks corresponding to the first information part corresponding to the first information vector and blocks corresponding to the second information part corresponding to the second information vector. Blocks classified as parts are classified into blocks corresponding to the first partial block, blocks corresponding to the second partial block, and blocks corresponding to the third partial block, and are classified into the second information part. Are classified into blocks corresponding to the fourth partial block, blocks corresponding to the fifth partial block, and blocks corresponding to the sixth partial block, and the blocks classified as the first parity part are the seventh partial block. Blocks classified into blocks corresponding to the second partial block, blocks corresponding to the eighth partial block, and blocks corresponding to the ninth partial block are blocks corresponding to the tenth partial block. And the block corresponding to the eleventh partial block. The blocks classified into the blocks and the blocks corresponding to the twelfth partial block, and the blocks classified into the third parity part may include blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, and twelfth. The fifteenth partial block has a diagonal relationship with the eleventh partial block in block units, and an identity matrix is arranged in the blocks corresponding to the fifteenth partial block. do.

Another parity check matrix generation method proposed by the present invention includes; A method for generating a parity check matrix of a block low density parity check (LDPC) code in a communication system, comprising: a first parity check matrix and a second parity check matrix used for encoding an information vector into a block LDPC code; Generating at least one, wherein the first parity check matrix is generated using a second parity check matrix, the second parity check matrix comprises a plurality of blocks, wherein the plurality of blocks is the information vector. Blocks corresponding to the information part corresponding to the first block, blocks corresponding to the first parity part corresponding to the first parity vector, and blocks corresponding to the second parity part corresponding to the second parity vector, When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may include a first tablet corresponding to the first information vector. Blocks corresponding to the beam part and blocks corresponding to the second information part corresponding to the second information vector may be classified into blocks corresponding to the first partial block and blocks corresponding to the first partial block. The blocks classified into the two partial blocks and classified into the second information part are classified into blocks corresponding to the third partial block and blocks corresponding to the fourth partial block, and the first parity part. The blocks classified as are classified into blocks corresponding to the fifth partial block and blocks corresponding to the sixth partial block, and blocks classified into the second parity part are blocks corresponding to the seventh partial block and eighth. The block may be classified into blocks corresponding to the partial block.

First, in the next generation communication system, various methods, for example, hybrid automatic repeat request (HARQ) method and adaptive modulation and coding (AMC) method to support high-speed large data transmission and reception Various methods such as Adaptive Modulation and Coding (hereinafter, referred to as 'AMC') have been proposed, and various coding rates must be supported in order to use the HARQ method and the AMC method. However, a block low density parity check (LDPC) code, which is actively considered for use in a next generation communication system, has a limitation in terms of coding rate. Accordingly, the present invention proposes a signal transmission and reception apparatus and method for supporting various coding rates in a communication system using a block LDPC code.

1 is a diagram showing the structure of a signal transmission apparatus in a communication system according to an embodiment of the present invention.

)가 발생되면, 상기 정보 벡터(

)는 상기 부호화기(111)로 전달된다. 상기 부호화기(111)는 상기 정보 벡터(

)를 미리 설정되어 있는 부호화 방식으로 부호화하여 부호어 벡터(codeword vector)(

), 즉 LDPC 부호어로 생성한 후 상기 변조기(113)로 출력한다. 여기서, 상기 부호화 방식은 LDPC 부호화 방식이 되는 것이다. 상기 변조기(113)는 상기 부호어 벡터(

)를 미리 설정되어 있는 변조 방식으로 변조하여 변조 벡터(

)으로 생성하여 상기 송신기(115)로 출력한다. 상기 송신기(115)는 상기 변조기(113)에서 출력한 변조 벡터(

)를 입력하여 송신 신호 처리한 후 안테나를 통해 신호 수신 장치로 송신한다. Referring to FIG. 1, first, the signal transmission apparatus includes an encoder 111, a modulator 113, and a transmitter 115. First, an information vector to be transmitted by the signal transmission apparatus (

Is generated, the information vector (

) Is passed to the encoder 111. The encoder 111 stores the information vector (

) Is encoded using a predetermined coding scheme, so that a codeword vector (

), That is, the LDPC codeword is generated and output to the modulator 113. Here, the coding scheme is an LDPC coding scheme. The modulator 113 is the codeword vector (

) Modulates a modulation vector (

To generate and output to the transmitter 115. The transmitter 115 is a modulation vector (output from the modulator 113)

After inputting), the transmitter transmits the signal to the signal receiving apparatus through the antenna.

Next, a structure of a signal receiving apparatus of a communication system according to an exemplary embodiment of the present invention will be described with reference to FIG. 2.

2 is a diagram showing the structure of a signal receiving apparatus in a communication system according to an embodiment of the present invention.

)를 상기 복조기(213)로 출력한다. 상기 복조기(213)는 상기 수신기(211)에서 출력한 수신 벡터(

)를 입력하여 상기 신호 송신 장치의 변조기, 즉 변조기(113)에서 적용한 변조 방식에 상응하는 복조 방식으로 복조한 후 그 복조한 복조 벡터(

)를 상기 복호기(215)로 출력한다. 상기 복호기(215)는 상기 복조기(213)에서 출력한 복조 벡터(

)를 입력하여 상기 신호 송신 장치의 부호화기, 즉 부호화기(111)에서 적용한 부호화 방식에 상응하는 복호 방식으로 복호한 후 그 복호한 신호를 최종적으로 복원된 정보 벡터(

)로 출력한다. 여기서, 상기 복호 방식, LDPC 복호 방식은 일 예로 합곱(sum-product) 알고리즘(algorithm)에 기반한 반복 복호(iterative decoding) 알고리즘을 사용하는 방식이라고 가정하기로 한다. Referring to FIG. 2, the signal receiving apparatus includes a receiver 211, a demodulator 213, and a decoder 215. First, a signal transmitted from a signal transmission device is received through an antenna of the signal reception device, and a signal received through the antenna is transmitted to the receiver 211. The receiver 211 processes the received signal by receiving the received signal and processes the received signal (the received vector (

) Is output to the demodulator 213. The demodulator 213 is a reception vector (output from the receiver 211)

) Is demodulated by a demodulation method corresponding to the modulation scheme applied by the modulator of the signal transmission apparatus, that is, the modulator 113, and then the demodulated demodulation vector (

) Is output to the decoder 215. The decoder 215 is a demodulation vector output from the demodulator 213 (

) Is decoded by a decoding method corresponding to the encoding method applied by the encoder of the signal transmission apparatus, that is, the encoder 111, and the decoded signal is finally recovered.

) Here, it will be assumed that the decoding method and the LDPC decoding method use an iterative decoding algorithm based on a sum-product algorithm as an example.

Next, a parity check matrix of a block LDPC code according to an embodiment of the present invention will be described with reference to FIG. 3.

3 is a diagram illustrating a parity check matrix structure of a block LDPC code according to an embodiment of the present invention.

크기를 가진다. 상기 순열 행렬이라 함은 상기 순열 행렬을 구성하는 N_s개의 행(row)들 각각의 웨이트(weight)가 1이고, 상기 순열 행렬을 구성하는 N_s개의 열(column)들 각각의 웨이트 역시 1인 행렬을 나타낸다. Referring to FIG. 3, the parity check matrix of the block LDPC code includes a plurality of blocks, and a permutation matrix or a zero matrix corresponds to each of the plurality of blocks. Here, the permutation matrix and the zero matrix are

Has a size. The permutation matrix is a weight of each of the N _s rows constituting the permutation matrix, and the weight of each of the N _s columns constituting the permutation matrix is also one. Represents a matrix.

)로 생성할 경우 상기 정보 벡터(

)에 대응되는 상기 블록 LDPC 부호의 패리티 검사 행렬의 파트를 나타내며, 상기 패리티 파트는 패리티 벡터(

)에 대응되는 상기 블록 LDPC 부호의 패리티 검사 행렬의 파트를 나타낸다. 상기 정보 벡터(

)는 적어도 1개의 정보 비트를 포함하며, 상기 패리티 벡터(

)는 적어도 1개의 패리티 비트를 포함한다. The parity check matrix includes an information part and a parity part. Herein, the information part includes an information vector as a codeword vector (

), The information vector (

) Represents a part of a parity check matrix of the block LDPC code, and the parity part is a parity vector (

Part of the parity check matrix of the block LDPC code corresponding to " The information vector (

) Includes at least one information bit, and the parity vector (

) Includes at least one parity bit.

혹은 a_ij = ∞를 가진다. 상기 위첨자 a_ij는 순열 행렬 P가 항등 행렬 구조에서 위첨자 a_ij만큼 오른쪽으로 쉬프트(shift)된 형태의 구조를 가짐게 됨을 나타낸다. 여기서, i는 상기 정보 파트가 포함하는 행렬들의 행의 개수를 나타내며, j는 상기 정보 파트가 포함하는 행렬들의 열의 개수를 나타낸다. 상기 도 3에는 상기 i가 m(i = m)인 경우와, j가 n인 경우(j = n)가 도시되어 있는 것이다.In addition, the superscript a _ij of the permutation matrix P included in the information part in FIG.

Or a _ij = ∞. The superscript a _ij indicates that the permutation matrix P has a structure shifted to the right by the superscript a _ij in the identity matrix structure. Here, i represents the number of rows of matrices included in the information part, and j represents the number of columns of matrices included in the information part. 3 illustrates a case where i is m (i = m) and a case where j is n (j = n).

를 나타내며, 상기 순열 행렬 P의 위첨자 a_ij가 ∞일 때, 즉 순열 행렬 P^∞는 영 행렬 나타낸다. 또는 상기 순열 행렬 P의 위첨자 a_ij가 -1일 때, 즉 순열 행렬 P^{- 1}는 영 행렬 나타낸다. 또한, p와 q는 상기 패리티 검사 행렬에서 상기 정보 파트에 해당하는 블록들의 행과 열의 개수를 나타낸다. 또한, 상기 패리티 파트가 포함하는 순열 행렬 P의 위첨자 a_i, x, y 역시 순열 행렬 P의 지수를 나타내며, 다만 설명의 편의상 정보 파트와의 구분을 위해 상이하게 설정하였을 뿐이다. 즉, 상기 도 3에서

내지

역시 순열 행렬들이며, 상기 패리티 파트의 대각(diagonal) 부분에 위치하는 행렬들에 순차적으로 인덱스(index)를 부여한 것이다. 또한, 상기 도 3에서 P^x와 P^y 역시 순열 행렬들이며, 설명의 편의상 임의의 인덱스를 부여한 것이다. When the superscript a _ij of the permutation matrix P included in the information part is 0, that is, P ⁰ is an identity matrix

When the superscript a _ij of the permutation matrix P is ∞, that is, the permutation matrix P ^∞ represents a zero matrix. Or when the superscript a _ij of the permutation matrix P is -1, that is, the permutation matrix P ^{- 1} represents a zero matrix. In addition, p and q represent the number of rows and columns of blocks corresponding to the information part in the parity check matrix. In addition, the superscripts a _i , x, and y of the permutation matrix P included in the parity part also represent exponents of the permutation matrix P, but are merely set differently from the information part for convenience of description. That is, in FIG.

To

Also, they are permutation matrices, and indexes are sequentially assigned to matrices located in the diagonal portion of the parity part. In addition, in FIG. 3, P ^x and P ^{y are} also permutation matrices, which are given an arbitrary index for convenience of description.

Meanwhile, in order to facilitate the design of the parity check matrix of the block LDPC code and the encoding of the block LDPC code, it is assumed that the parity check matrix of the block LDPC code includes a plurality of partial-blocks. Can be. Here, the partial block includes at least one block. In this case, the parity check matrix may be represented as shown in FIG. 4.

4 is a diagram illustrating the parity check matrix of FIG. 3 divided into six partial blocks.

)에 대응되는 상기 패리티 검사 행렬의 파트를 나타낸다. 또한, 상기 제1패리티 파트와 제2패리티 파트는 상기 도 3에서 설명한 패리티 파트와 같이 상기 블록 LDPC 부호를 부호화하는 과정에서 실제 패리티 벡터(

)에 대응되는 상기 패리티 검사 행렬의 파트를 나타내며, 상기 패리티 파트를 2개의 파트들로 분할한 것이다. 즉, 상기 패리티 벡터(

)가 제1패리티 벡터(

)와 제2패리티 벡터(

)를 포함할 경우, 상기 제1패리티 파트는 상기 제1패리티 벡터(

)에 대응되며, 상기 제2패리티 파트는 상기 제2패리티 벡터(

)에 대응된다. Referring to FIG. 4, the parity check matrix of the block LDPC code illustrated in FIG. 3 is divided into an information part, a first parity part, and partial blocks of a second parity part. Herein, the information part is the same as the information part described with reference to FIG. 3 in the process of encoding a block LDPC code.

Part of the parity check matrix. In addition, the first parity part and the second parity part, as in the parity part described with reference to FIG.

The parity check matrix corresponds to a part of the parity check matrix, and the parity part is divided into two parts. That is, the parity vector (

) Is the first parity vector (

) And the second parity vector (

), The first parity part includes the first parity vector (

) And the second parity part corresponds to the second parity vector (

Corresponds to).

The partial blocks of the information part, that is, the matrixes corresponding to the partial block A 402 and the partial block C 404 are the partial matrix A and the partial matrix C, and the partial blocks of the first parity part, that is, the partial block B The matrices corresponding to 406 and the partial block D 408 are the partial matrix B and the partial matrix D, and correspond to the partial blocks of the second parity part, that is, the partial block T 410 and the partial block E 412. The matrices are partial matrix 0 and partial matrix T and partial matrix E. In FIG. 4, the parity check matrix is illustrated as being divided into seven partial blocks. However, O is not a separate partial block, but the partial matrix T corresponding to the partial block T 410 has a full lower triangular shape. It should be noted that the area in which the O (zero) matrix is arranged around the diagonal is only zero.

Meanwhile, the partial block B 406, the partial block E 412, and the partial block T 410 of the partial blocks included in the parity check matrix of the block LDPC code according to the embodiment described above with reference to FIG. 4, respectively. The partial matrix B corresponding to, and the partial matrix E and the partial matrix T are generated to have a structure as shown in FIG. 5 in order to minimize the coding complexity of the block LDPC code.

FIG. 5 is a diagram illustrating a transpose matrix, a partial matrix E, a partial matrix T, and an inverse matrix of the partial matrix T of the partial matrix B of FIG. 4.

FIG. 5 shows a matrix B ^T , which is a binomial matrix of the partial matrix B, a partial matrix E, a partial matrix T, and a matrix T ^{−1 which} is an inverse of the partial matrix T. The partial matrix T has a form similar to a full lower triangular matrix. That is, the partial matrix T allows an identity matrix to be mapped to blocks located on a diagonal, and permutation matrices are mapped to blocks having a dual diagonal structure with the diagonal. Herein, a matrix mapped to a block will be referred to as a 'block matrix', and for convenience of explanation, a block and a block matrix will be used interchangeably.

As described above, in order to support various code rates in a communication system using a block LDPC code, a parity check matrix supporting the various code rates must be supported. Accordingly, an embodiment of the present invention proposes a method of generating a parity check matrix that supports various coding rates. That is, according to an embodiment of the present invention, various encodings are performed by using a first parity check matrix, that is, a parent parity check matrix and a child parity check matrix generated based on the parent parity check matrix. Suggest ways to support the rate. That is, in order to support a code rate exceeding a code rate supported by the parent parity check matrix, a puncturing scheme is used for the parent parity check matrix, and a code rate less than a code rate supported by the parent parity check matrix is supported. To do this, the mother parity check matrix is used. Here, for convenience of description, the case where the child parity check matrix is generated based on the parent parity check matrix will be described. However, the parent parity check matrix and the child parity check matrix can be generated separately. The structure of the parent parity check matrix will now be described.

First, it is assumed that an embodiment of the present invention generates a parent parity check matrix as a parity check matrix of a semi-systematic block LDPC code. The semi-structured block LDPC code is a code having a structure in which a general block LDPC code and a single parity check code are concatenated.

In general, a systematic code in a linear block code represents a code in which a part of the codeword vector is composed of an information vector when transmitting a codeword vector. Therefore, when decoding the codeword vector transmitted by the signal transmission apparatus on the signal receiving apparatus side, only a portion of the codeword vector corresponding to the information vector needs to be decoded.

In contrast, non systematic code indicates a code for transmitting a codeword vector corresponding to the information vector by using an encoder without transmitting the information vector when transmitting the codeword vector. That is, in the unstructured code, unlike the structural code in which a part of the codeword vector is composed of the information vector, the information vector is not included in the codeword vector. In the semi-structured block LDPC code proposed in the present invention, the entire information vector is not included in the codeword vector like the structural code, but only a part of the information vector is included in the codeword vector, and the rest is a code in which the parity vector is included in the codeword vector Indicates.

In addition, the parity check matrix of the semi-structured block LDPC code proposed in the present invention is largely classified into two types. The parity check matrix of the first type semi-structured block LDPC code will be described with reference to FIG. 6. The parity check matrix of the second type semi-structured block LDPC code will be described with reference to FIG. 7.

6 is a diagram illustrating a structure of a parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention.

Before describing FIG. 6, when the parity check matrix of the semi-structured block LDPC code is generated based on the parity check matrix of the block LDPC code, the performance of the semi-structured block LDPC code becomes better. Accordingly, the parity check matrix of the semi-structured block LDPC code is generated based on the parity check matrix of the general block LDPC code.

Referring to FIG. 6, the parity check matrix of the first type semi-structured block LDPC code includes a partial block A1 600, a partial block C1 602, a partial block F 604, and a partial block A2 610. ), Partial block C2 612, partial block G 614, partial block B 620, partial block D 622, partial block 0 624, partial block T 640 , Partial block E 642, partial block 0 644, partial block 0 650, partial block 0 652, and partial block H 654.

In addition, the structure of the encoder for encoding the information vector using the parity check matrix of the first type semi-structured block LDPC code shown in FIG. 6 corresponds to two parts, that is, the parity check matrix of the general block LDPC code. It is divided into a part corresponding to a part and a part corresponding to newly added partial blocks. For convenience of description, a part corresponding to the parity check matrix of the general block LDPC code will be referred to as an existing part, and a part corresponding to newly added partial blocks will be referred to as a new part. In FIG. 6, the part indicated by (1) is an existing part, and the part indicated by (2) is a new part.

First, the existing part will be described.

The existing part includes a partial block A1 600, a partial block C1 602, a partial block A2 610, a partial block C2 612, a partial block B 620, and a partial block D 622. And a partial block T 640 and a partial block E 642. Meanwhile, the partial blocks included in the existing part shown in FIG. 6 have an association relationship with the partial blocks described with reference to FIG. 4, which will be described below.

The partial block A 402 includes the partial block A1 600 and the partial block A2 610, and the partial block C 404 includes the partial block C1 602 and the partial block C2 612. And the partial block B 406 is the same as the partial block B 620, the partial block D 408 is the same as the partial block B 622, and the partial block T 410 is the partial Same as block T 640, where partial block E 412 and partial block E 642 are identical.

Next, the new part will be described.

The new part is part block F (604), part block G (614), part block 0 (624), part block 0 (644), part block 0 (650), part block 0 (652). And partial block H 654. The partial block F 604 is partial blocks corresponding to information bits mapped to the partial block A1 600 and the partial block C1 602 of the information vector. Here, the degree of the column of the partial block A1 600 is 'l', the order of the column of the partial block C1 602 is 'm', and the order of the column of the partial block F 604 is 'n'. Assume that the order of the columns of the partial block including the partial block A1 600, the partial block C1 602, and the partial block F 604 is 'l + m + n'. The order 'l + m + n' of the column of the partial block including the partial block A1 600, the partial block C1 602, and the partial block F 604 is the partial block A2 620 and the partial block C2 ( 612 and the order 'k' of the column of the partial block including the partial block G 614.

Therefore, when the signal transmission apparatus needs to punch the information bits of some of the information vectors, the partial block including the partial block A1 600, the partial block C1 602, and the partial block F 604 is included. Perforate mapped information bits. In this case, the signal transmission apparatus may puncture relatively high order information bits in the information vector to improve the recovery performance in the signal reception apparatus. In general, since the higher order information bits generally have high reliability, the signal transmission device punctures the higher order information bits. However, if the information bits of higher order are unilaterally punctured, an error occurrence probability increases in the information bits of higher order, and thus the signal transmission apparatus additionally transmits parity bits to maintain reliability. For example, the puncturing may be performed sequentially from the first information bit among the information bits mapped to the partial block including the partial block A1 600, the partial block C1 602, and the partial block F 604.

Meanwhile, the partial block H 654 included in the new part is a partial block corresponding to a newly added parity bit, so that a matrix having an order of all columns 1, for example, an identity matrix. In addition, by making the new part include the partial block 0 624 and the partial block 0 644, the encoder of the general LDPC code and the encoder of the single parity check code can be concatenated. Here, since the parity portion of the general block LDPC code has an accumulator structure, parity generation can be simultaneously performed only in units of blocks. However, since the single parity check code portion has a structure in which only 1 of diagonal elements has a value of 1 ) Can be encoded at one time. As a result, the first type semi-structured block LDPC code proposed in the present invention can be encoded in substantially the same time as the general block LDPC code.

)에 대응되는 파트를 나타낸다. 여기서, 상기 정보 벡터(

)가 제1정보 벡터(

)와 제2정보 벡터(

)를 포함할 경우, 상기 제1정보 파트는 상기 제1정보 벡터(

)에 대응되며, 상기 제2정보 파트는 상기 제2정보 벡터(

)에 대응되는 파트를 나타낸다. In FIG. 6, the partial block A1 600, the partial block C1 602, and the partial block F 604 correspond to the first information part, and the partial block A2 610 and the partial block C2 612. ), The partial block G 614 corresponds to the second information part, the partial block B 620, the partial block D 622, and the partial block 0 624 correspond to the first parity part. The partial block T 640, the partial block E 642, and the partial block 0 644 correspond to the second parity part, the partial block 0 650, the partial block 0 652, and the partial block H. 654 corresponds to the third parity part. The third parity part is a third parity vector (

) Corresponding parts. Where the information vector (

) Is the first information vector (

) And the second information vector (

), The first information part includes the first information vector (

Corresponding to the second information part, the second information vector

) Corresponding parts.

)를 부호어 벡터(

), 즉 반구조적 블록 LDPC 부호어로 생성하는 동작에 대해 설명하기로 한다. Then, using the parity check matrix of the first type semi-structured block LDPC code,

) Is the signword vector (

), That is, an operation of generating a semi-structured block LDPC codeword will be described.

)에서 일부가 천공되어야할 경우 상기 제1정보 파트에 해당하는 정보 비트들, 즉 제1정보 벡터(

)이 천공된다. 따라서, 부호어 벡터(

)는 하기 수학식 1과 같이 나타낼 수 있다.First, since the information part includes a first information part and a second information part, and the degree of the first information part is larger than that of the second information part, the information vector (

In the case where a part of the first information part needs to be punctured, information bits corresponding to the first information part, that is, a first information vector (

) Is perforated. Therefore, the codeword vector (

) May be expressed as in Equation 1 below.

Meanwhile, in FIG. 6, the matrix 0 is divided into the partial block O 624, the partial block 0 644, the partial block 0 650, and the partial block 0 652 of the partial blocks corresponding to the third parity part. Although the corresponding case has been described as an example, a matrix other than the zero matrix may correspond to the partial block O 624, the partial block 0 644, and the partial block 0 650 and the partial block 0 652. Of course you can.

However, the parity check matrix of the first type semi-structured block LDPC code generally shows excellent performance when designing a code having a relatively low coding rate of 1/2 or less. Therefore, in order to generate a semi-structured block LDPC code having a relatively high coding rate, a parity check of a new parity check matrix different from the parity check matrix of the first type semi-structured block LDPC code, that is, the second type semi-structured block LDPC code You must use a matrix.

Next, a parity check matrix of the second type semi-structured block LDPC code will be described with reference to FIG. 7.

7 is a diagram illustrating a parity check matrix structure of a second type semi-structured block LDPC code according to an embodiment of the present invention.

Referring to FIG. 7, the parity check matrix of the second type semi-structured block LDPC code includes a partial block A1 700, a partial block C1 702, a partial block A2 710, and a partial block C2 712. ), A partial block B 720, a partial block D 722, a partial block T 740, and a partial block E 742.

Meanwhile, the partial blocks illustrated in FIG. 7 have an association relationship with the partial blocks described in FIG. 4, which will be described below.

The partial block A 402 includes the partial block A1 700 and the partial block A2 710, and the partial block C 404 includes the partial block C1 702 and the partial block C2 712. And the partial block B 406 is the same as the partial block B 720, the partial block D 408 is the same as the partial block B 722, and the partial block T 410 is the partial Same as block T 740, where partial block E 412 and partial block E 742 are identical.

Here, assuming that the order of the columns of the partial block A1 700 is 'l' and the order of the columns of the partial block C1 702 is 'm', the partial block A1 700 and the partial block C1 702 The order of the columns of the partial block including) becomes 'l + m', and the partial block including the partial block A1 700 and the partial block C1 702 includes the partial block A 402 and the partial block C. Include those with the highest order among the columns that the partial block comprising 404 includes.

)를 부호어 벡터(

), 즉 반구조적 블록 LDPC 부호어로 생성하는 동작에 대해 설명하기로 한다. Then, using the parity check matrix of the second type semi-structured block LDPC code,

) Is the signword vector (

), That is, an operation of generating a semi-structured block LDPC codeword will be described.

)에서 일부가 천공되어야할 경우 상기 제1정보 파트에 해당하는 정보 비트들, 즉 제1정보 벡터(

)이 천공된다. 따라서, 부호어 벡터(

)는 하기 수학식 2와 같이 나타낼 수 있다.First, since the information part includes a first information part and a second information part, and the degree of the first information part is larger than that of the second information part, the information vector (

In the case where a part of the first information part needs to be punctured, information bits corresponding to the first information part, that is, a first information vector (

) Is perforated. Therefore, the codeword vector (

) Can be expressed as in Equation 2 below.

As described above with reference to FIGS. 6 and 7, a parity check matrix is a parity check matrix of the first type semi-structured block LDPC code or a parity check matrix of a second type semi-structured block LDPC code and is based on the parent parity check matrix. This generates a parity check matrix. Then, when the parent parity check matrix is the parity check matrix of the first type semi-structured block LDPC code with reference to FIG. 8, the child parity generated based on the parent parity check matrix of the first type semi-structured block LDPC code. The check matrix will be described.

8 is a diagram illustrating a structure of a child parity check matrix generated based on a parent parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention. Hereinafter, for convenience of explanation, a child parity check matrix generated based on a parent parity check matrix of the first type semi-structured block LDPC code will be referred to as a 'first type ruler parity check matrix'. The parent parity check matrix of the block LDPC code will be referred to as a 'first type parent parity check matrix'.

Referring to FIG. 8, the first type J parity check matrix includes a partial block A1 800, a partial block C1 802, a partial block F 804, a partial block J 806, and a partial block. A2 810, partial block C2 812, partial block G 814, partial block K 816, partial block B 820, partial block D 822, partial block 0 ( 824, partial block 0 826, partial block T 840, partial block E 842, partial block 0 844, partial block 0 846, partial block 0 850. Partial block 0 852, partial block H 854, partial block 0 856, partial block 0 860, partial block 0 862, partial block 0 864, Partial block L 866 is included.

Here, the partial block A1 800, the partial block C1 802, the partial block F 804, the partial block A2 810, the partial block C2 812, the partial block G 814, , Partial block B 820, partial block D 822, partial block 0 824, partial block T 840, partial block E 842, partial block 0844, partial The block 0 850, the partial block 0 852, and the partial block H 854 include the partial block A1 600, the partial block C1 602, and the partial block F 604 described in FIG. 6. , Partial block A2 610, partial block C2 612, partial block G 614, partial block B 620, partial block D 622, partial block 0 624, partial It is the same as the block T 640, the partial block E 642, the partial block 0 644, the partial block 0 650, the partial block 0 652, and the partial block H 654.

)에 비해 더 낮은 부호화율을 가지는 부호어 벡터(

)를 생성하기 위해 상기 제1타입 모 패리티 검사 행렬에 새롭게 추가된 부분 블록들을 나타낸다. 상기 부분 블록 L(866)에는 모든 열의 차수가 1인 행렬, 일 예로 항등 행렬이 대응되도록 한다. 즉, 상기 모 패리티 검사 행렬이 지원하는 부호화율 미만의 부호화율을 지원하기 위해서는 모 패리티 검사 행렬을 사용하여 생성되는 모 부호어 벡터에 단일 패리티 부호(single parity check code)를 추가적으로 포함시키는 형태로 최종 부호어 벡터를 생성하면 된다. 따라서, 제1타입 자 패리티 검사 행렬을 사용하여 정보 벡터(

)를 부호화하여 부호어 벡터(

)를 생성할 경우 제1타입 모 패리티 검사 행렬을 사용하여 정보 벡터(

)를 부호화하여 부호어 벡터(

)를 생성하는 경우와 거의 동일한 시간이 소요된다. In addition, the partial block J 806, the partial block K 816, the partial block 0 826, the partial block 0 846, the partial block 0 856, the partial block 0 860, , A partial block 0 862, a partial block 0 864, and a partial block L 866 are codewords generated by the first type parent parity check matrix based on the first type parent parity check matrix. vector(

Codeword vector with lower coding rate

In this example, the partial blocks newly added to the first type parent parity check matrix are generated. The partial block L 866 corresponds to a matrix of order 1 of all columns, for example, an identity matrix. That is, in order to support a code rate lower than a code rate supported by the parent parity check matrix, a single parity check code is additionally included in a mother codeword vector generated using the parent parity check matrix. The codeword vector can be generated. Therefore, using the first type ruler parity check matrix, the information vector (

) And the codeword vector (

), Use the type 1 parity check matrix to generate the information vector (

) And the codeword vector (

) Takes almost the same amount of time.

Meanwhile, in FIG. 8, partial blocks corresponding to the third parity part, that is, partial block O 824, partial block 0 844, partial block 0 850, and partial block 0 852 are zero. A matrix corresponds, and the partial blocks corresponding to the fourth parity part, that is, partial block O 826, partial block 0 846, partial block 0 856, partial block 0 860, Although the case where the zero matrix corresponds to the partial block 0 862 and the partial block 0 864 has been described as an example, the partial block O 824, the partial block 0 844, and the partial block 0 850 are described. With partial block 0 852, partial block O 826, partial block 0 846, partial block 0 856, partial block 0 860, partial block 0 862, Of course, the non-zero matrix may correspond to the partial block 0 864.

On the other hand, the decoding of the LDPC code using the puncturing scheme is performed using the original parity check matrix by considering the punctured parity bits as an erasure. That is, if the log-likelihood ratio (LLR) input from the channel to the punctured parity bits is always assumed to be '0', it is possible to perform decoding of the LDPC code using the puncturing scheme using the original parity check matrix. do. Therefore, when the codeword bits corresponding to the columns of the parity check matrix having a degree of 1 are punctured, the punctured codeword node delivers only a value of '0' in the decoding process. Therefore, since the output signal of the check node connected to the punctured codeword is always '0', it is possible to delete the rows connected to the punctured codeword. That is, when puncturing newly added codeword bits to generate a codeword vector having a lower coding rate, the same effect as performing an encoding / decoding operation using only a parity check matrix can be obtained. That is, when generating an LDPC code having a high coding rate by using the self parity check matrix, an encoding / decoding operation may be performed using a mother parity check matrix except for an additional portion of the self parity check matrix. When generating an LDPC code having a low coding rate, all of the self parity check matrices can be used.

)가 우수한 성능을 보장받을 수 있도록 설계하고, 상기 제1타입 모 패리티 검사 행렬의 차수 분포를 그대로 사용하는 상태에서 상기 밀도 진화 방식을 사용하여 상기 제1타입 자 패리티 검사 행렬의 차수 분포를 설계한다. Meanwhile, the degree distribution of the first type self parity check matrix may be designed using a density evolution method based on the order distribution of the first type parent parity check matrix. In this case, the codeword vector generated by the first type mother parity check matrix using the density evolution method of the order distribution of the first type mother parity check matrix

) Is designed to ensure excellent performance, and the order distribution of the first type J parity check matrix is designed using the density evolution method while using the order distribution of the first type parent parity check matrix as it is. .

)를 부호어 벡터(

), 즉 반구조적 블록 LDPC 부호어로 생성하는 동작에 대해 설명하기로 한다. Then, using the first type ruler parity check matrix,

) Is the signword vector (

), That is, an operation of generating a semi-structured block LDPC codeword will be described.

)에서 일부가 천공되어야할 경우 상기 제1정보 파트에 해당하는 정보 비트들, 즉 제1정보 벡터(

)이 천공된다. 따라서, 부호어 벡터(

)는 하기 수학식 3과같이 나타낼 수 있다.First, since the information part includes a first information part and a second information part, and the degree of the first information part is larger than that of the second information part, the information vector (

In the case where a part of the first information part needs to be punctured, information bits corresponding to the first information part, that is, a first information vector (

) Is perforated. Therefore, the codeword vector (

) Can be expressed as in Equation 3 below.

Next, when the mother parity check matrix is a parity check matrix of the second type semi-structured block LDPC code, the parent parity generated based on the mother parity check matrix of the second type semi-structured block LDPC code. The test matrix will be described.

9 is a diagram illustrating a structure of a child parity check matrix generated based on a parent parity check matrix of a second type semi-structured block LDPC code according to an embodiment of the present invention. Hereinafter, for convenience of description, a child parity check matrix generated based on a parent parity check matrix of the second type semi-structured block LDPC code will be referred to as a 'second type ruler parity check matrix'. The parent parity check matrix of the LDPC code will be referred to as a 'second type parent parity check matrix'.

Referring to FIG. 9, the second type self parity check matrix includes a partial block A1 900, a partial block C1 902, a partial block F 904, a partial block A2 910, and a partial block. C2 912, partial block G 914, partial block B 920, partial block D 922, partial block 0 924, partial block T 940, partial block E ( 942, partial block 0 944, partial block 0 950, partial block 0 952, and partial block H 954.

Here, the partial block A1 900, the partial block C1 902, the partial block A2 910, the partial block C2 912, the partial block B 920, the partial block D 922, The partial block T 940 and the partial block E 942 include the partial block A1 700, the partial block C1 702, the partial block A2 710, and the partial block C2 712 described in FIG. 7. And the partial block B 720, the partial block D 722, the partial block T 740, and the partial block E 742 are the same.

)에 비해 더 낮은 부호화율을 가지는 부호어 벡터(

)를 생성하기 위해 상기 제2타입 모 패리티 검사 행렬에 새롭게 추가된 부분 블록들을 나타낸다. 상기 부분 블록 H(954)에는 모든 열의 차수가 1인 행렬, 일 예로 항등 행렬이 대응되도록 한다. 따라서, 제2타입 자 패리티 검사 행렬을 사용하여 정보 벡터(

)를 부호화하여 부호어 벡터(

)를 생성할 경우 제2타입 모 패리티 검사 행렬을 사용하여 정보 벡터(

)를 부호화하여 부호어 벡터(

)를 생성하는 경우와 거의 동일한 시간이 소요된다. The partial block F 904, the partial block G 914, the partial block 0 924, the partial block 0 944, the partial block 0 950, the partial block 0 952, The partial block H 954 is a codeword vector generated by the second type parent parity check matrix based on the second type parent parity check matrix.

Codeword vector with lower coding rate

In order to generate a), the partial blocks newly added to the second type parent parity check matrix are shown. The partial block H 954 corresponds to a matrix having an order of all columns 1, for example, an identity matrix. Therefore, using the second type ruler parity check matrix, the information vector (

) And the codeword vector (

), You can use the type 2 parity check matrix to

) And the codeword vector (

) Takes almost the same amount of time.

Meanwhile, in FIG. 9, a matrix 0 is included in the partial block O 924, the partial block 0 944, the partial block 0 950, and the partial block 0 952 of the partial blocks corresponding to the third parity part. Although the corresponding case has been described as an example, a matrix other than the zero matrix may correspond to the partial block O 924, the partial block 0 944, and the partial block 0 950 and the partial block 0 952. Of course you can.

Next, the internal structure of the encoder 111 of FIG. 1 will be described with reference to FIG. 10.

10 is a block diagram illustrating an example of an internal structure of the encoder 111 of FIG. 1.

Referring to FIG. 10, the encoder 111 includes a perforator 1011, a partial matrix A multiplier 1013, a partial matrix C multiplier 1015, a switch 1017, and a matrix ET ^-1. A multiplier 1019, an exclusive-OR operator 1021, a partial matrix B multiplier 1023, an exclusive-OR operator 1025, a matrix T- ¹ multiplier 1027, a single parity code encoder 1029, , An assembly machine 1031 and a controller (not shown).

First, the operation of the controller will be described.

)에서 천공할 정보 비트들이 존재하는지 여부와, 단일 패리티 부호를 생성할 필요가 있는지 여부 등을 판단한다.The controller selects a parent parity check matrix or a child parity check matrix corresponding to a coding rate to be used in the signal transmission apparatus, and corresponds to the partial matrix A, the partial matrix B, and the partial matrix T corresponding to the selected parity check matrix. , The partial matrix C, the partial matrix D, and the partial matrix E are determined. Here, the parent parity check matrix is one of a first type parent parity check matrix and a second type parent parity check matrix, and the child parity check matrix is one of a first type child parity check matrix and a second type child parity check matrix. . In addition, the controller corresponds to the information vector (corresponding to the selected parity check matrix).

), It is determined whether there are information bits to be punctured and whether it is necessary to generate a single parity code.

)가 입력되면, 상기 정보 벡터(

)는 상기 천공기(1011)와, 부분 행렬 A 곱셈기(1013)와, 부분 행렬 C 곱셈기(1015) 및 스위치(1017)로 전달된다. 상기 천공기(1011)는 상기 제어기의 제어에 따라 상기 정보 벡터(

)를 바이패스(bypass)하여 상기 정보 벡터(

) 그대로를 상기 조립기(1031)로 출력하거나, 혹은 상기 정보 벡터(

)에서 해당 정보 비트들을 천공하여 천공된 정보 벡터(

)로 생성한 후 상기 천공된 정보 벡터(

)를 상기 조립기(1031)로 출력한다. 여기서, 상기 제어기는 상기 선택된 패리티 검사 행렬에 상응하게 상 기 천공기(1011)가 상기 정보 벡터(

)를 그대로 출력하거나 혹은 해당 정보 비트들을 천공하여 천공된 정보 벡터(

)로 출력할지를 결정하는 것이다. First, the information vector to be encoded

) Is inputted, the information vector (

) Is passed to the puncturer 1011, the partial matrix A multiplier 1013, the partial matrix C multiplier 1015, and the switch 1017. The perforator 1011 is configured to control the information vector (3) under control of the controller.

) By bypassing the information vector (

) Is output as it is to the granulator 1031 or the information vector (

Perforated the corresponding information bits in the

And the perforated information vector (

) Is output to the granulator 1031. In this case, the controller determines that the puncturer 1011 corresponds to the information vector (corresponding to the selected parity check matrix).

) As it is or by drilling the corresponding information bits

Is to decide whether to output

The controller also controls the switch 1017 to be on or off in correspondence with the selected parity check matrix. That is, the controller turns off the switch 1017 when the selected parity check matrix is a parent parity check matrix, and turns on the switch 1019 when the selected parity check matrix is a child parity check matrix.

)와 부분 행렬 A를 곱셈한 후 상기 행렬 ET^-1 곱셈기(1019)와 배타적 논리합 연산기(1025)로 출력한다. 상기 행렬 ET^-1 곱셈기(1019)는 상기 부분 행렬 A 곱셈기(1013)에서 출력한 신호와 행렬 ET^-1를 곱셈한 후 상기 배타적 논리합 연산기(1021)로 출력한다. 상기 부분 행렬 C 곱셈기(1015)는 상기 정보 벡터(

)와 부분 행렬 C를 곱셈한 후 상기 배타적 논리합 연산기(1021)로 출력한다. 상기 배타적 논리합 연산기(1021)는 상기 행렬 ET^-1 곱셈기(1019)에서 출력한 신호와 상기 부분 행렬 C 곱셈기(1015)에서 출력한 신호를 배타적 논리합 연산한 후 상기 부분 행렬 B 곱셈기(1023)와 상기 조립기(1031)로 출력한다. 여기서, 상기 배타적 논리합 연산기(1021)에서 출력한 신호가 제1패리티 벡터(

)가 되는 것이다.The partial matrix A multiplier 1013 stores the information vector (

) And the partial matrix A are multiplied and output to the matrix ET ^-1 multiplier 1019 and the exclusive-OR operator 1025. The matrix ET ^-1 multiplier 1019 multiplies the signal output from the partial matrix A multiplier 1013 and the matrix ET ^-1 and outputs the result to the exclusive-OR operator 1021. The partial matrix C multiplier 1015 stores the information vector (

) And the partial matrix C are multiplied and output to the exclusive OR operator 1021. The exclusive OR operator 1021 performs an exclusive OR on the signal output from the matrix ET- ¹ multiplier 1019 and the signal output from the partial matrix C multiplier 1015, and then performs the partial matrix B multiplier 1023 and the Output to the granulator 1031. Here, the signal output from the exclusive-OR operator 1021 is a first parity vector (

)

)가 되는 것이다.The partial matrix B multiplier 1023 multiplies the signal output by the exclusive OR operator 1021 and the partial matrix B and outputs the multiplication matrix B to the exclusive OR operator 1025. The exclusive OR operator 1025 performs an exclusive OR operation on the signal output from the partial matrix A multiplier 1013 and the signal output from the partial matrix B multiplier 1023, and then outputs the result to the matrix ET ^-1 multiplier 1027. do. The matrix T- ¹ multiplier 1027 multiplies the signal output from the exclusive OR operator 1025 and the matrix T ^-1 and then outputs the multiplier to the assembly unit 1031. Here, the signal output from the matrix T- ¹ multiplier 1027 is a second parity vector (

)

)가 제3패리티 벡터(

) 혹은 상기 제3패리티 벡터(

) 및 제4패리티 벡터(

)를 생성할 필요가 있을 경우에만 상기 스위치(1017)를 온시켜 상기 정보 벡터(

)가 상기 단일 패리티 부호 부호화기(1029)로 입력되도록 제어한다. 상기 단일 패리티 부호 부호화기(1029)는 상기 스위치(1017)에서 출력한 신호를 부호화하여 단일 패리티 부호어, 즉 제3패리티 벡터(

) 혹은 상기 제3패리티 벡터(

) 및 제4패리티 벡터(

)로 생성한 후 상기 조립기(1031)로 출력한다. The switch 1017 performs a switching operation under the control of the controller, and the controller performs the information vector (

) Is the third parity vector (

) Or the third parity vector (

) And the fourth parity vector (

Only if it is necessary to generate the

) Is input to the single parity code encoder 1029. The single parity code encoder 1029 encodes a signal output from the switch 1017 to generate a single parity codeword, that is, a third parity vector (

) Or the third parity vector (

) And the fourth parity vector (

) And output to the granulator 1031.

)로 조립한 후 출력한다.The granulator 1031 inputs signals output from the puncturing machine 1011, the exclusive-OR operator 1021, the matrix T ⁻¹ multiplier 1027, and the single parity code encoder 1029 under the control of the controller. Codeword vector

After assembling, print it out.

) 혹은 천공된 정보 벡터(

)와, 제1패리티 벡터(

)와, 제2패리티 벡터(

)와, 제3패리티 벡터(

)와, 제4패리티 벡터(

)를 병렬적으로 생성한 후 조립하여 부호어 벡터(

)를 생성하도록 제어하는 경우를 일 예로 하여 설명하였으나, 상기 제어기가 그 부호화율에 상응하게 각 벡터, 즉 상기 정보 벡터(

) 혹은 천공된 정보 벡터(

)와, 제1패리티 벡터(

)와, 제2패리티 벡터(

)와, 제3패리티 벡터(

) 및 제4패리티 벡터(

)중 해당하는 벡터만을 순차적으로 생성하여 부호어 벡터(

)를 생성하도록 제어할 수도 있음은 물론이다.In FIG. 10, the controller corresponds to each vector, that is, the information vector (corresponding to its coding rate).

) Or perforated information vector (

) And the first parity vector (

) And the second parity vector (

) And the third parity vector (

) And the fourth parity vector (

) In parallel, and then assembled to codeword vectors (

In the following example, the control is generated to generate?), But the controller corresponds to each vector, that is, the information vector (corresponding to the coding rate).

) Or perforated information vector (

) And the first parity vector (

) And the second parity vector (

) And the third parity vector (

) And the fourth parity vector (

), Only the corresponding vectors are generated sequentially and the codeword vector (

Of course, you can control the creation of).

In addition, in FIG. 10, the case where the encoder 111 includes the perforator 1011 is described as an example. However, when the coding rate supported by the signal transmission apparatus is the mother coding rate or the child coding rate, the puncturer 1011 does not perform the puncturing operation. Therefore, when using only the mother code rate or the child code rate in the signal transmission apparatus, the encoder 111 may not include the puncturer 1011.

Next, the internal structure of the decoder 215 of FIG. 2 will be described with reference to FIG. 11.

11 is a block diagram illustrating an internal structure of the decoder 215 of FIG. 2.

Referring to FIG. 11, the decoder 215 includes a block controller 1111, a variable node decoder 1113, a switch 1115, an exclusive-OR operator 1117, and a de-interleaver. 1119, an interleaver 1121, a controller 1123, a memory 1125, an exclusive-OR operator 1127, a check node decoder 1129, and a hard decision unit 1131. It includes.

)의 크기에 상응하게 부호어 벡터(

)의 크기를 결정한다. 여기서, 상기 블록 제어기(1111)는 상기 신호 송신 장치에서 정보 벡터(

)중 특정 정보 비트들을 천공하여 송신하였을 경우, 상기 천공된 정보 비트들에 해당하는 비트들에 0을 삽입한 후 상기 변수 노드 복호기(1113)로 출력한다. 또한, 상기 블록 제어기(1111)는 상기 신호 송신 장치와 상기 신호 수신 장치간에 미리 규약된 모 패리티 검사 행렬 및 자 패리티 검사 행렬을 미리 저장하고 있으며, 또한 상기 신호 송신 장치에서 적용한 부호화율에 상응하는 정보 비트들의 천공 정보 등을 미리 저장하고 있다. 여기서, 상기 블록 제어기(1111)는 상기 해당 부호화율에 따라 천공되는 정보 비트들의 개수 뿐만 아니라 그 위치 정보까지도 미리 저장하고 있다.First, a demodulator, that is, a signal output from the demodulator 213 of FIG. 2, is transmitted to the block controller 1111, and the block controller 1111 inputs a signal output from the demodulator 213 to transmit a signal. Applied codeword vector (

Corresponding to the magnitude of)

) Determines the size. Here, the block controller 1111 is an information vector (signal) in the signal transmission apparatus.

In the case where specific information bits are transmitted by puncturing, 0 is inserted into bits corresponding to the punctured information bits and then outputted to the variable node decoder 1113. In addition, the block controller 1111 pre-stores a parent parity check matrix and a child parity check matrix previously prescribed between the signal transmitter and the signal receiver, and further includes information corresponding to a coding rate applied by the signal transmitter. The puncturing information of the bits is stored in advance. Here, the block controller 1111 pre-stores not only the number of information bits to be punctured but also its position information according to the corresponding coding rate.

The variable node decoder 1113 inputs the signal output from the block controller 1111 to calculate the probability values, updates the calculated probability values, and outputs the calculated probability values to the switch 1115 and the exclusive-OR operator 1117. do. Here, the variable node decoder 1113 connects the variable nodes corresponding to the parity check matrix preset in the decoder 215, and updates them with an input value and an output value equal to the number of 1 connected to the variable nodes. The operation is performed. The number of 1s connected to each of the variable nodes is equal to the weight of each of the columns constituting the parity check matrix. Therefore, the internal operation of the variable node decoder 1113 varies according to the weight of each of the columns constituting the parity check matrix.

The exclusive OR operator 1117 inputs a signal output from the variable node decoder 1113 and an output signal of the interleaver 1121 during a previous iterative decoding process, and in the variable node decoder 1113. The output signal of the interleaver 1121 in the previous iterative decoding process is subtracted from the output signal and then output to the deinterleaver 1119. Here, of course, when the decoding process is the first decoding process, the output signal of the interleaver 1121 should be regarded as 0.

The deinterleaver 1119 inputs the signal output from the exclusive OR operator 1117 and de-interleaves the deinterleaving method according to a preset deinterleaving scheme, and then the exclusive OR operator 1127 and the check node. Output to decoder 1129. Here, the internal structure of the deinterleaver 1127 has a structure corresponding to the parity check matrix, for the reason that the deinterleaver 1127 corresponds to the deinterleaver 1127 according to the position of elements having a value of 1 in the parity check matrix. This is because the output value with respect to the input value of the interleaver 1121 is different.

The exclusive OR operator 1127 inputs an output signal of the check node decoder 1129 and an output signal of the deinterleaver 1119 in a previous iterative decoding process, and outputs the check node decoder in the previous iterative decoding process. The output signal of the deinterleaver 1119 is subtracted from the output signal of 1129 and then output to the interleaver 1121. The check node decoder 1129 connects check nodes according to a parity check matrix preset in the decoder 215, and an update operation having an input value and an output value equal to 1 connected to the check nodes is performed. Is performed. The number of 1s connected to each of the check nodes is equal to the weight of each of the rows constituting the parity check matrix. Therefore, the internal operation of the check node decoder 1129 is different according to the weight of each of the rows constituting the parity check matrix.

Here, the interleaver 1121 interleaves the signal output from the exclusive-OR operator 1127 in a preset manner according to the control of the controller 1123, and then the exclusive-OR operator 1117 and the variable node. Output to decoder 1113. Herein, the controller 1123 reads information related to the interleaving scheme stored in the memory 1125 to control the interleaving scheme of the interleaver 1121. In addition, when the decoding process is the first decoding process, the output signal of the deinterleaver 1119 should be regarded as 0.

By repeatedly performing the above processes, reliable decoding is performed without errors, and after performing repeated decoding corresponding to a preset number of preset repetitions, the switch 1115 performs an exclusive OR with the variable node decoder 1113. After switching off between the operators 1117, the variable node decoder 1113 and the hard determiner 1131 are switched on to output a signal output from the variable node decoder 1113 to the hard determiner 1131. . The hard determiner 1131 inputs the signal output from the variable node decoder 1113 to make a hard decision, and then outputs the hard decision result, and the output value of the hard determiner 1131 is finally decoded. Will be.

Next, when the coding rate is 1/2 with reference to FIGS. 12A to 12H and 13A to 13G, each part included in the parity check matrix of the first type semi-structured block LDPC code according to an embodiment of the present invention. The partial matrix corresponding to the block will be described.

12A to 12H illustrate an example of a matrix corresponding to each partial block included in a parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 1/2. One drawing.

The numbers described in the blocks in the matrix illustrated in FIGS. 12A to 12H represent exponents of the permutation matrixes corresponding to the blocks. Here, the exponent is assuming that the permutation matrix is expressed as P ^a containing an exponent. If a = 0, this means that the permutation matrix, that is, P ⁰ is an identity matrix. As it increases, the permutation matrix has a structure shifted to the right from the identity matrix structure. In addition, when a = -1, this indicates that the permutation matrix, that is, P ^-1 is a '0' matrix, and all elements are '0'.

13A to 13G illustrate another example of a matrix corresponding to each partial block included in a parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 1/2. One drawing.

The numbers described in the blocks in the matrix shown in FIGS. 13A to 13G represent exponents of the permutation matrix corresponding to the blocks. Here, the exponent is assuming that the permutation matrix is expressed as P ^a containing an exponent. If a = 0, this means that the permutation matrix, that is, P ⁰ is an identity matrix. As it increases, the permutation matrix has a structure shifted to the right from the identity matrix structure. In addition, when a = -1, this indicates that the permutation matrix, that is, P ^-1 is a '0' matrix, and all elements are '0'.

Next, when the coding rate is 5/6 with reference to FIGS. 14A to 14B, for a matrix corresponding to each partial block included in a parity check matrix of a second type semi-structured block LDPC code according to an embodiment of the present invention, FIG. Let's explain.

14A to 14B illustrate an example of a matrix corresponding to each partial block included in a parity check matrix of a second type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 5/6. One drawing.

The numerals described in the blocks in the matrix illustrated in FIGS. 14A to 14B represent exponents of the permutation matrix corresponding to the blocks. Here, the exponent is assuming that the permutation matrix is expressed as P ^a containing an exponent. If a = 0, this means that the permutation matrix, that is, P ⁰ is an identity matrix. As it increases, the permutation matrix is shifted to the right from the identity matrix structure. In addition, when a = -1, this indicates that the permutation matrix, that is, P ^-1 is a '0' matrix, and all elements are '0'.

Next, when the coding rate is 11/12 with reference to FIGS. 15A to 15C, the partial matrix corresponding to each partial block included in the parity check matrix of the second type semi-structured block LDPC code according to the embodiment of the present invention is described. This will be described.

15A to 15C illustrate an example of a matrix corresponding to each partial block included in a parity check matrix of a second type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 11/12. One drawing. In addition, when a = -1, this indicates that the permutation matrix, that is, P ^-1 is a '0' matrix, and all elements are '0'.

The numbers described in the blocks in the matrix illustrated in FIGS. 15A to 15C represent exponents of the permutation matrixes corresponding to the blocks. Here, the exponent is assuming that the permutation matrix is expressed as P ^a containing an exponent. If a = 0, this means that the permutation matrix, that is, P ⁰ is an identity matrix. As it increases, the permutation matrix has a structure shifted to the right from the identity matrix structure.

In particular, the arrows indicated by the diagonal lines in FIGS. 15B and 15C indicate that the corresponding blocks are connected. That is, it should be noted that the partial block A2 and the partial block C2 in FIG. 15B are only divided for convenience of description in one drawing.

16A and 16B, when the coding rate is 1/12, the partial matrix corresponding to each partial block included in the parity check matrix of the first type semi-structured block LDPC code according to the embodiment of the present invention is described. This will be described.

16A and 16B illustrate examples of partial matrices corresponding to each partial block included in a parity check matrix of a first type semi-structured block LDPC code according to an embodiment of the present invention when the coding rate is 1/2. One drawing.

The numbers described in the blocks in the matrix shown in FIGS. 16A and 16B indicate the exponents of the permutation matrix corresponding to the blocks. Here, the exponent is assuming that the permutation matrix is expressed as P ^a containing an exponent. If a = 0, this means that the permutation matrix, that is, P ⁰ is an identity matrix. As it increases, the permutation matrix has a structure shifted to the right from the identity matrix structure. In addition, when a = -1, this indicates that the permutation matrix, that is, P ^-1 is a '0' matrix, and all elements are '0'.

Next, the internal structure of the encoder 111 of FIG. 1 will be described with reference to FIG. 17.

17 is a block diagram illustrating another example of an internal structure of the encoder 111 of FIG. 1.

Referring to FIG. 17, the encoder 111 includes a puncturer 1711, a partial matrix A multiplier 1713, a partial matrix C multiplier 1715, a switch 1725, and a matrix ET ⁻¹ multiplier 1725. ), An exclusive-OR operator 1721, a partial matrix B multiplier 1723, an exclusive-OR operator 1725, a matrix T- ¹ multiplier 1727, a single parity code encoder 1729, and an assembling unit 1731. ) And a controller (not shown).

First, the operation of the controller will be described.

)에서 천공할 정보 비트들이 존재하는지 여부와, 단일 패리티 부호를 생성할 필요가 있는지 여부 등을 판단한다.The controller selects a parent parity check matrix or a child parity check matrix corresponding to a coding rate to be used in the signal transmission apparatus, and corresponds to the partial matrix A, the partial matrix B, and the partial matrix T corresponding to the selected parity check matrix. , The partial matrix C, the partial matrix D, and the partial matrix E are determined. Here, the parent parity check matrix is one of a first type parent parity check matrix and a second type parent parity check matrix, and the child parity check matrix is one of a first type child parity check matrix and a second type child parity check matrix. . In addition, the controller corresponds to the information vector (corresponding to the selected parity check matrix).

), It is determined whether there are information bits to be punctured and whether it is necessary to generate a single parity code.

)가 입력되면, 상기 정보 벡터(

)는 상기 천공기(1711)와, 부분 행렬 A 곱셈기(1713)와, 부분 행렬 C 곱셈기(1715) 및 스위치(1717)로 전달된다. 상기 천공기(1711)는 상기 제어기의 제어에 따라 상기 정보 벡터(

)를 바이패스(bypass)하여 상기 정보 벡터(

) 그대로를 상기 조립기(1731)로 출력하거나, 혹은 상기 정보 벡터(

)에서 해당 정보 비트들을 천공하 여 천공된 정보 벡터(

)로 생성한 후 상기 천공된 정보 벡터(

)를 상기 조립기(1731)로 출력한다. 여기서, 상기 제어기는 상기 선택된 패리티 검사 행렬에 상응하게 상기 천공기(1711)가 상기 정보 벡터(

)를 그대로 출력하거나 혹은 해당 정보 비트들을 천공하여 천공된 정보 벡터(

)로 출력할지를 결정하는 것이다. First, the information vector to be encoded

) Is inputted, the information vector (

Is transmitted to the puncturer 1711, the partial matrix A multiplier 1713, the partial matrix C multiplier 1715, and the switch 1725. The puncturer 1711 is configured to control the information vector (3) under the control of the controller.

) By bypassing the information vector (

) As it is or is output to the granulator 1731, or the information vector (

Perforated the corresponding information bits in the

And the perforated information vector (

) Is output to the granulator 1731. Herein, the controller determines that the puncturer 1711 corresponds to the information vector (corresponding to the selected parity check matrix).

) As it is or by drilling the corresponding information bits

Is to decide whether to output

The controller also controls the switch 1725 to be on or off in correspondence with the selected parity check matrix. That is, the controller turns off the switch 1917 when the selected parity check matrix is a parent parity check matrix, and turns on the switch 1719 when the selected parity check matrix is a child parity check matrix.

)와 부분 행렬 A를 곱셈한 후 상기 행렬 ET^-1 곱셈기(1719)와 배타적 논리합 연산기(1725)로 출력한다. 상기 행렬 ET^-1 곱셈기(1719)는 상기 부분 행렬 A 곱셈기(1713)에서 출력한 신호와 행렬 ET^{- 1}를 곱셈한 후 상기 배타적 논리합 연산기(1721)로 출력한다. 상기 부분 행렬 C 곱셈기(1715)는 상기 정보 벡터(

)와 부분 행렬 C를 곱셈한 후 상기 배타적 논리합 연산기(1721)로 출력한다. 상기 배타적 논리합 연산기(1721)는 상기 행렬 ET^-1 곱셈기(1719)에서 출력한 신호와 상기 부분 행렬 C 곱셈기(1715)에서 출력한 신호를 배타적 논리합 연산한 후 상기 부분 행렬 B 곱셈기(1723)와 상기 천공기(1711)로 출력한다. 여기서, 상기 배타적 논리합 연산기(1721)에서 출력한 신호 가 제1패리티 벡터(

)가 되는 것이다. The partial matrix A multiplier 1713 stores the information vector (

) And the partial matrix A are multiplied and output to the matrix ET- ¹ multiplier 1725 and the exclusive-OR operator 1725. The matrix ET ^-1 multiplier 1917 multiplies the signal output from the partial matrix A multiplier 1713 and the matrix ET ^{- 1} and then outputs the result to the exclusive-OR operator 1721. The partial matrix C multiplier 1715 uses the information vector (

) And the partial matrix C are multiplied and output to the exclusive OR operator 1721. The exclusive OR operator 1721 performs an exclusive OR on the signal output from the matrix ET ⁻¹ multiplier 1725 and the signal output from the partial matrix C multiplier 1715, and then performs the partial matrix B multiplier 1723 and the Output to puncher 1711. Here, the signal output from the exclusive OR operator 1721 is a first parity vector (

)

)가 되는 것이다. 상기 행렬 ET^-1 곱셈기(1727)와 행렬 T^-1 곱셈기(1727)에서 T^-1 곱셈은 back substitution 방식을 사용하여 수행될 수 있음은 물론이다.The partial matrix B multiplier 1723 multiplies the signal output by the exclusive OR operator 1721 and the partial matrix B and outputs the multiplication matrix B to the exclusive OR operator 1725. The exclusive OR operator 1725 performs an exclusive OR on the signal output from the matrix A multiplier 1713 and the signal output from the partial matrix B multiplier 1723, and then outputs the result to the matrix ET ^-1 multiplier 1725. . The matrix T- ¹ multiplier 1725 multiplies the signal output from the exclusive OR operator 1725 and the matrix T ^{- 1} and outputs the result to the puncturer 1711. Here, the signal output from the matrix T- ¹ multiplier 1727 is a second parity vector (

) In the matrix ET- ¹ multiplier 1727 and the matrix T- ¹ multiplier 1727, T ^-1 multiplication may be performed using a back substitution method.

)와 제2패리티 벡터(

)를 바이패스하여 상기 제1패리티 벡터(

)와 제2패리티 벡터(

)를 그대로 상기 조립기(1731)로 출력하거나, 혹은 상기 제1패리티 벡터(

)와 제2패리티 벡터(

)중 적어도 어느 하나에서 해당 패리티 비트들을 천공하여 상기 조립기(1731)로 출력한다. 여기서, 상기 제어기는 상기 선택된 부호화율에 상응하게 상기 천공기(1711)가 상기 제1패리티 벡터(

)와 제2패리티 벡터(

)를 그대 로 상기 조립기(1731)로 출력하거나, 혹은 상기 제1패리티 벡터(

)와 제2패리티 벡터(

)중 적어도 어느 하나에서 해당 패리티 비트들을 천공하여 상기 조립기(1731)로 출력하도록 제어한다.The puncturer 1711 may control the first parity vector (3) under the control of the controller.

) And the second parity vector (

) By bypassing the first parity vector (

) And the second parity vector (

) Is output as it is to the granulator 1731, or the first parity vector (

) And the second parity vector (

The at least one of the parity bits are punctured and output to the assembly unit 1731. Herein, the controller determines that the puncturer 1711 corresponds to the first parity vector (corresponding to the selected coding rate).

) And the second parity vector (

) Is output to the assembly unit 1731, or the first parity vector (

) And the second parity vector (

Perforations of the parity bits in at least one of the control units and outputs the parity bits to the assembling unit 1731.

)가 제3패리티 벡터(

) 혹은 상기 제3패리티 벡터(

) 및 제4패리티 벡터(

)를 생성할 필요가 있을 경우에만 상기 스위치(1717)를 온시켜 상기 정보 벡터(

)가 상기 단일 패리티 부호 부호화기(1729)로 입력되도록 제어한다. 상기 단일 패리티 부호 부호화기(1729)는 상기 스위치(1717)에서 출력한 신호와 상기 제1패리티 벡터(

)와 제2패리티 벡터(

)를 입력한 후 부호화하여 단일 패리티 부호어, 즉 제3패리티 벡터(

) 혹은 상기 제3패리티 벡터(

) 및 제4패리티 벡터(

)로 생성한 후 상기 천공기(1711)로 출력한다. The switch 1917 performs a switching operation according to the control of the controller, and the controller performs the information vector (

) Is the third parity vector (

) Or the third parity vector (

) And the fourth parity vector (

Only when it is necessary to generate the

) Is input to the single parity code encoder 1729. The single parity code encoder 1729 includes a signal output from the switch 1725 and the first parity vector (

) And the second parity vector (

) And then encoded to encode a single parity codeword, that is, a third parity vector (

) Or the third parity vector (

) And the fourth parity vector (

And then output to the punching machine 1711.

) 및 제4패리티 벡터(

)를 바이패스하여 상기 제3패리티 벡터(

) 및 제4패리티 벡터(

)를 그대로 상기 조립기(1731)로 출력하거나, 혹은 상기 제3패리티 벡터(

) 및 제4패리티 벡터(

)중 적어도 하나에서 해당 패리티 비트들을 천공하여 상기 조립기(1731)로 출력한다. 여기서, 상기 제어기는 상기 선택된 부호화율에 상응하게 상기 천공기(1711)가 상기 제3패리티 벡터(

) 및 제4패리티 벡터(

)를 그대로 상기 조립기(1731)로 출력하거나, 혹은 제3패리티 벡터(

) 및 제4패리티 벡터(

)중 적어도 하나에서 해당 패리티 비트들을 천공하여 상기 조립기(1731)로 출력 하도록 제어한다. The puncturer 1711 may be configured as a third parity vector (3) under the control of the controller.

) And the fourth parity vector (

) By bypassing the third parity vector (

) And the fourth parity vector (

) Is output as it is to the granulator 1731, or the third parity vector (

) And the fourth parity vector (

The at least one parity bits are punctured and outputted to the assembly unit 1731. In this case, the controller determines that the puncturer 1711 corresponds to the third parity vector in accordance with the selected coding rate.

) And the fourth parity vector (

) Is output as it is to the granulator 1731, or the third parity vector (

) And the fourth parity vector (

At least one of the control unit to control to output the parity bits to the assembly unit (1731).

)로 조립한 후 출력한다.The granulator 1731 is configured to convert a signal output from the puncturer 1711 under a control of the controller into a codeword vector (

After assembling, print it out.

) 혹은 천공된 정보 벡터(

)와, 제1패리티 벡터(

)와, 제2패리티 벡터(

)와, 제3패리티 벡터(

)와, 제4패리티 벡터(

)를 병렬적으로 생성한 후 조립하여 부호어 벡터(

)를 생성하도록 제어하는 경우를 일 예로 하여 설명하였으나, 상기 제어기가 그 부호화율에 상응하게 각 벡터, 즉 상기 정보 벡터(

) 혹은 천공된 정보 벡터(

)와, 제1패리티 벡터(

)와, 제2패리티 벡터(

)와, 제3패리티 벡터(

) 및 제4패리티 벡터(

)중 해당하는 벡터만을 순차적으로 생성하여 부호어 벡터(

)를 생성하도록 제어할 수도 있음은 물론이다.In FIG. 17, the controller corresponds to each vector, that is, the information vector (corresponding to its coding rate).

) Or perforated information vector (

) And the first parity vector (

) And the second parity vector (

) And the third parity vector (

) And the fourth parity vector (

) In parallel, and then assembled to codeword vectors (

In the following example, the control is generated to generate?), But the controller corresponds to each vector, that is, the information vector (corresponding to the coding rate).

) Or perforated information vector (

) And the first parity vector (

) And the second parity vector (

) And the third parity vector (

) And the fourth parity vector (

), Only the corresponding vectors are generated sequentially and the codeword vector (

Of course, you can control the creation of).

In addition, in FIG. 17, the case where the encoder 111 includes the perforator 1711 is described as an example. However, when the coding rate supported by the signal transmission apparatus is the mother coding rate or the child coding rate, the puncturer 1711 does not perform the puncturing operation. Therefore, when using only the mother code rate or the child code rate in the signal transmission apparatus, the encoder 111 may not include the puncturer 1711.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

As described above, the present invention makes it possible to transmit and receive signals by supporting various coding rates in a communication system using a block LDPC code. In addition, the present invention makes it possible to support various coding rates even with only one parity check matrix, thereby minimizing the complexity of implementing an encoder and a decoder.

Claims (75)

A method for generating a parity check matrix of a block low density parity check (LDPC) code in a communication system, Generating at least one of a first parity check matrix and a second parity check matrix used for encoding the information vector into a block LDPC code, The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector, blocks corresponding to the second parity part corresponding to the second parity vector, and third parity parts corresponding to the third parity vector. Classified into corresponding blocks, When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block, blocks corresponding to the second partial block, blocks corresponding to the third partial block, The blocks classified as the second information part are classified into blocks corresponding to the fourth partial block, blocks corresponding to the fifth partial block, blocks corresponding to the sixth partial block, The blocks classified as the first parity part are classified into blocks corresponding to a seventh partial block, blocks corresponding to an eighth partial block, blocks corresponding to a ninth partial block, The blocks classified as the second parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. And the fifteenth partial block has a diagonal relationship with the eleventh partial block in block units, and an identity matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 1, A non-zero matrix is arranged in blocks corresponding to the third partial block and blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, and blocks corresponding to a twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 1, Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in corresponding blocks and blocks corresponding to the fourteenth partial block. The method of claim 1, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, blocks corresponding to the third parity part, and blocks corresponding to a fourth parity part corresponding to a fourth parity vector. Classified, The blocks classified as the first information part are classified into blocks corresponding to the first to third partial blocks and blocks corresponding to a sixteenth partial block. The blocks classified as the second information part are classified into blocks corresponding to the fourth to sixth partial blocks and blocks corresponding to the seventeenth partial block. The blocks classified as the first parity part are classified into blocks corresponding to the seventh to ninth partial blocks and blocks corresponding to the eighteenth partial block. The blocks classified as the second parity part are classified into blocks corresponding to the tenth to 12th partial blocks and blocks corresponding to the nineteenth partial block. The blocks classified as the third parity part are classified into blocks corresponding to the thirteenth to fifteenth partial blocks and blocks corresponding to the twentieth partial block. The blocks classified as the fourth parity part may include blocks corresponding to a twenty-first partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-third partial block, and blocks corresponding to a twenty-fourth partial block. Classified into The twenty-fourth partial block has a diagonal relationship with the fifteenth partial block in block units, and an identity matrix is arranged in blocks corresponding to the twenty-fourth partial block. The method of claim 4, wherein Nonzero matrixes are arranged in blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a sixteenth partial block, and blocks corresponding to a seventeenth partial block. Blocks corresponding to the ninth partial block, blocks corresponding to the twelfth partial block, blocks corresponding to the thirteenth partial block, blocks corresponding to the fourteenth partial block, and eighteenth partial block Blocks corresponding to the twenty-first partial block, blocks corresponding to a nineteenth partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-first partial block, And a zero matrix is arranged in blocks corresponding to the twenty-third block. The method of claim 4, wherein Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. Corresponding blocks and blocks corresponding to the fourteenth partial block, blocks corresponding to the sixteenth partial block, blocks corresponding to the seventeenth partial block, blocks corresponding to the eighteenth partial block, Blocks corresponding to the 19th partial block, blocks corresponding to the 20th partial block, blocks corresponding to the 21st partial block, blocks corresponding to the 22nd partial block, and corresponding to the 23rd partial block Parity check matrix generation method characterized in that the blocks are arranged in a non-zero matrix. The method of claim 1, And the order of the columns of the first information part is different from the order of the columns of the second information part. A method for generating a parity check matrix of a block low density parity check (LDPC) code in a communication system, Generating at least one of a first parity check matrix and a second parity check matrix used for encoding the information vector into a block LDPC code, The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector and blocks corresponding to the second parity part corresponding to the second parity vector. When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and blocks corresponding to the second partial block. Blocks classified as the second information part are classified into blocks corresponding to a third partial block and blocks corresponding to a fourth partial block. The blocks classified as the first parity part are classified into blocks corresponding to a fifth partial block and blocks corresponding to a sixth partial block. And the blocks classified as the second parity part are classified into blocks corresponding to a seventh partial block and blocks corresponding to an eighth partial block. The method of claim 8, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, and blocks corresponding to a third parity part corresponding to a third parity vector, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and the second partial block, blocks corresponding to the ninth partial block, The blocks classified as the second information part are classified into blocks corresponding to the third partial block and the fourth partial block, blocks corresponding to the tenth partial block, The blocks classified as the first parity part are classified into blocks corresponding to the fifth partial block and the sixth partial block, and blocks corresponding to the eleventh partial block. The blocks classified as the second parity part are classified into blocks corresponding to the seventh and eighth partial blocks and blocks corresponding to the twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a thirteenth partial block, blocks corresponding to a fourteenth partial block, and blocks corresponding to a fifteenth partial block. The fifteenth partial block has a diagonal relationship with the eighth partial block in block units, and an identity matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 8, A non-zero matrix is arranged in blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, and blocks corresponding to the twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 8, Blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, blocks corresponding to the twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in corresponding blocks and blocks corresponding to the fourteenth partial block. In the method for encoding a block low density parity check (LDPC) code in a signal transmission apparatus, Generating a first block LDPC codeword by encoding an information vector using the first parity check matrix when the code rate to be used in the signal transmission apparatus is a first code rate that is a code rate of a first parity check matrix; Generating a second block LDPC codeword by encoding the information vector using the second parity check matrix when the code rate to be used in the signal transmission apparatus is a second code rate that is a code rate of a second parity check matrix. , The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector, blocks corresponding to the second parity part corresponding to the second parity vector, and third parity parts corresponding to the third parity vector. Classified into corresponding blocks, When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block, blocks corresponding to the second partial block, blocks corresponding to the third partial block, The blocks classified as the second information part are classified into blocks corresponding to the fourth partial block, blocks corresponding to the fifth partial block, blocks corresponding to the sixth partial block, The blocks classified as the first parity part are classified into blocks corresponding to a seventh partial block, blocks corresponding to an eighth partial block, blocks corresponding to a ninth partial block, The blocks classified as the second parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. The fifteenth partial block has a diagonal relationship with the eleventh partial block in block units, and an equality matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 12, A non-zero matrix is arranged in blocks corresponding to the third partial block and blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, and blocks corresponding to a twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 12, Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in the corresponding blocks and the blocks corresponding to the fourteenth partial block. The method of claim 12, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, blocks corresponding to the third parity part, and blocks corresponding to a fourth parity part corresponding to a fourth parity vector. Classified, The blocks classified as the first information part are classified into blocks corresponding to the first to third partial blocks and blocks corresponding to a sixteenth partial block. The blocks classified as the second information part are classified into blocks corresponding to the fourth to sixth partial blocks and blocks corresponding to the seventeenth partial block. The blocks classified as the first parity part are classified into blocks corresponding to the seventh to ninth partial blocks and blocks corresponding to the eighteenth partial block. The blocks classified as the second parity part are classified into blocks corresponding to the tenth to 12th partial blocks and blocks corresponding to the nineteenth partial block. The blocks classified as the third parity part are classified into blocks corresponding to the thirteenth to fifteenth partial blocks and blocks corresponding to the twentieth partial block. The blocks classified as the fourth parity part may include blocks corresponding to a twenty-first partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-third partial block, and blocks corresponding to a twenty-fourth partial block. Classified into The twenty-fourth partial block has a diagonal relationship with the fifteenth partial block in block units, and an identity matrix is arranged in blocks corresponding to the twenty-fourth partial block. The method of claim 15, Nonzero matrixes are arranged in blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a sixteenth partial block, and blocks corresponding to a seventeenth partial block. Blocks corresponding to the ninth partial block, blocks corresponding to the twelfth partial block, blocks corresponding to the thirteenth partial block, blocks corresponding to the fourteenth partial block, and eighteenth partial block Blocks corresponding to the 19th partial block, blocks corresponding to the 20th partial block, blocks corresponding to the 21st partial block, blocks corresponding to the 22nd partial block, and And a zero matrix is arranged in blocks corresponding to a twenty-third partial block. The method of claim 15, Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. Corresponding blocks and blocks corresponding to the fourteenth partial block, blocks corresponding to the sixteenth partial block, blocks corresponding to the seventeenth partial block, blocks corresponding to the eighteenth partial block, Blocks corresponding to the 19th partial block, blocks corresponding to the 20th partial block, blocks corresponding to the 21st partial block, blocks corresponding to the 22nd partial block, and corresponding to the 23rd partial block And a non-zero matrix is arranged in the blocks. The method of claim 12, And the order of the columns of the first information part is different from the order of the columns of the second information part. The method of claim 18, If the order of the columns of the first information part is greater than the order of the columns of the second information part, If the code rate to be used in the signal transmission apparatus is a third code rate less than the second code rate, the second block LDPC codeword punctures the first information vector corresponding to the third code rate to perform a third block LDPC. A method of encoding a block LDPC code, comprising generating a codeword. The method of claim 18, If the order of the columns of the first information part is greater than the order of the columns of the second information part, When the coding rate to be used in the signal transmission apparatus is less than the first coding rate and a fourth coding rate exceeding a second coding rate, the first information corresponding to the fourth coding rate in the first block LDPC codeword A method of encoding a block LDPC code comprising puncturing a vector to generate a fourth block LDPC codeword. In the method for encoding a block low density parity check (LDPC) code in a signal transmission apparatus, Generating a first block LDPC codeword by encoding an information vector using the first parity check matrix when the code rate to be used in the signal transmission apparatus is a first code rate that is a code rate of a first parity check matrix; Generating a second block LDPC codeword by encoding the information vector using the second parity check matrix when the code rate to be used in the signal transmission apparatus is a second code rate that is a code rate of a second parity check matrix. , The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector and blocks corresponding to the second parity part corresponding to the second parity vector. When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and blocks corresponding to the second partial block. Blocks classified as the second information part are classified into blocks corresponding to a third partial block and blocks corresponding to a fourth partial block. The blocks classified as the first parity part are classified into blocks corresponding to a fifth partial block and blocks corresponding to a sixth partial block. The blocks classified as the second parity part are classified into blocks corresponding to a seventh partial block and blocks corresponding to an eighth partial block. The method of claim 21, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, and blocks corresponding to a third parity part corresponding to a third parity vector, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and the second partial block, blocks corresponding to the ninth partial block, The blocks classified as the second information part are classified into blocks corresponding to the third partial block and the fourth partial block, blocks corresponding to the tenth partial block, The blocks classified as the first parity part are classified into blocks corresponding to the fifth partial block and the sixth partial block, and blocks corresponding to the eleventh partial block. The blocks classified as the second parity part are classified into blocks corresponding to the seventh and eighth partial blocks and blocks corresponding to the twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a thirteenth partial block, blocks corresponding to a fourteenth partial block, and blocks corresponding to a fifteenth partial block. The fifteenth partial block has a diagonal relationship with the eighth partial block in block units, and an equality matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 21, A non-zero matrix is arranged in blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, and blocks corresponding to the twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 21, Blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, blocks corresponding to the twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in the corresponding blocks and the blocks corresponding to the fourteenth partial block. The method of claim 21, And the order of the columns of the first information part is different from the order of the columns of the second information part. The method of claim 25, If the order of the columns of the first information part is greater than the order of the columns of the second information part, If the code rate to be used in the signal transmission apparatus is a third code rate less than the second code rate, the second block LDPC codeword punctures the first information vector corresponding to the third code rate to perform a third block LDPC. Encoding method of block LDPC code including generating codeword The method of claim 25, If the order of the columns of the first information part is greater than the order of the columns of the second information part, When the coding rate to be used in the signal transmission apparatus is less than the first coding rate and a fourth coding rate exceeding a second coding rate, the first information corresponding to the fourth coding rate in the first block LDPC codeword A method of encoding a block LDPC code comprising puncturing a vector to generate a fourth block LDPC codeword. An apparatus for encoding a block low density parity check (LDPC) code in a signal transmission apparatus, When the code rate to be used in the signal transmission apparatus is a first code rate that is a code rate of a first parity check matrix, an information vector is encoded by using the first parity check matrix to generate a first block LDPC codeword, and the signal transmission. A coder for generating a second block LDPC codeword by encoding the information vector using the second parity check matrix when the code rate to be used in the apparatus is a code rate of a second parity check matrix; The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector, blocks corresponding to the second parity part corresponding to the second parity vector, and third parity parts corresponding to the third parity vector. Classified into corresponding blocks, When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block, blocks corresponding to the second partial block, blocks corresponding to the third partial block, The blocks classified as the second information part are classified into blocks corresponding to the fourth partial block, blocks corresponding to the fifth partial block, blocks corresponding to the sixth partial block, The blocks classified as the first parity part are classified into blocks corresponding to a seventh partial block, blocks corresponding to an eighth partial block, blocks corresponding to a ninth partial block, The blocks classified as the second parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. The fifteenth partial block has a diagonal relationship with the eleventh partial block in block units, and an identity matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 28, A non-zero matrix is arranged in blocks corresponding to the third partial block and blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, and blocks corresponding to a twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 28, Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in the corresponding blocks and the blocks corresponding to the fourteenth partial block. The method of claim 28, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, blocks corresponding to the third parity part, and blocks corresponding to a fourth parity part corresponding to a fourth parity vector. Classified, The blocks classified as the first information part are classified into blocks corresponding to the first to third partial blocks and blocks corresponding to a sixteenth partial block. The blocks classified as the second information part are classified into blocks corresponding to the fourth to sixth partial blocks and blocks corresponding to the seventeenth partial block. The blocks classified as the first parity part are classified into blocks corresponding to the seventh to ninth partial blocks and blocks corresponding to the eighteenth partial block. The blocks classified as the second parity part are classified into blocks corresponding to the tenth to 12th partial blocks and blocks corresponding to the nineteenth partial block. The blocks classified as the third parity part are classified into blocks corresponding to the thirteenth to fifteenth partial blocks and blocks corresponding to the twentieth partial block. The blocks classified as the fourth parity part may include blocks corresponding to a twenty-first partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-third partial block, and blocks corresponding to a twenty-fourth partial block. Classified into The twenty-fourth partial block has a diagonal relationship with the fifteenth partial block in block units, and an identity matrix is arranged in blocks corresponding to the twenty-fourth partial block. The method of claim 31, wherein Nonzero matrixes are arranged in blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a sixteenth partial block, and blocks corresponding to a seventeenth partial block. Blocks corresponding to the ninth partial block, blocks corresponding to the twelfth partial block, blocks corresponding to the thirteenth partial block, blocks corresponding to the fourteenth partial block, and eighteenth partial block Blocks corresponding to the twenty-first partial block, blocks corresponding to a nineteenth partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-first partial block, and blocks corresponding to a twenty-second partial block And a zero matrix is arranged in blocks corresponding to a twenty-third block. The method of claim 31, wherein Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. Corresponding blocks and blocks corresponding to the fourteenth partial block, blocks corresponding to the sixteenth partial block, blocks corresponding to the seventeenth partial block, blocks corresponding to the eighteenth partial block, Blocks corresponding to the 19th partial block, blocks corresponding to the 20th partial block, blocks corresponding to the 21st partial block, blocks corresponding to the 22nd partial block, and corresponding to the 23rd partial block And a non-zero matrix is arranged in the blocks. The method of claim 28, And the order of the columns of the first information part is different from the order of the columns of the second information part. The method of claim 34, wherein The encoder; The second block LDPC codeword when the coding rate to be used by the signal transmission apparatus is a third coding rate less than the second coding rate when the order of the columns of the first information part is greater than the order of the columns of the second information part. And a third block LDPC codeword is generated by puncturing the first information vector according to the third code rate. The method of claim 34, wherein The encoder; When the order of the columns of the first information part is larger than the order of the columns of the second information part, when the coding rate to be used in the signal transmission apparatus is less than the first coding rate and the fourth coding rate exceeds the second coding rate And generating a fourth block LDPC codeword by puncturing the first information vector corresponding to the fourth code rate from the first block LDPC codeword. An apparatus for encoding a block low density parity check (LDPC) code in a signal transmission apparatus, When the code rate to be used in the signal transmission apparatus is a first code rate that is a code rate of a first parity check matrix, an information vector is encoded by using the first parity check matrix to generate a first block LDPC codeword, and the signal transmission. A coder for generating a second block LDPC codeword by encoding the information vector using the second parity check matrix when the code rate to be used in the apparatus is a code rate of a second parity check matrix; The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector and blocks corresponding to the second parity part corresponding to the second parity vector. When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and blocks corresponding to the second partial block. Blocks classified as the second information part are classified into blocks corresponding to a third partial block and blocks corresponding to a fourth partial block. The blocks classified as the first parity part are classified into blocks corresponding to a fifth partial block and blocks corresponding to a sixth partial block. The blocks classified as the second parity part are classified into blocks corresponding to a seventh partial block and blocks corresponding to an eighth partial block. The method of claim 21, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, and blocks corresponding to a third parity part corresponding to a third parity vector, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and the second partial block, blocks corresponding to the ninth partial block, The blocks classified as the second information part are classified into blocks corresponding to the third partial block and the fourth partial block, blocks corresponding to the tenth partial block, The blocks classified as the first parity part are classified into blocks corresponding to the fifth partial block and the sixth partial block, and blocks corresponding to the eleventh partial block. The blocks classified as the second parity part are classified into blocks corresponding to the seventh and eighth partial blocks and blocks corresponding to the twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a thirteenth partial block, blocks corresponding to a fourteenth partial block, and blocks corresponding to a fifteenth partial block. And the fifteenth partial block has a diagonal relationship with the eighth partial block in block units, and an identity matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 37, A non-zero matrix is arranged in blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, and blocks corresponding to the twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 37, Blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, blocks corresponding to the twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in the corresponding blocks and the blocks corresponding to the fourteenth partial block. The method of claim 37, And the order of the columns of the first information part is different from the order of the columns of the second information part. The method of claim 41, wherein The encoder; The second block LDPC code, if the coding rate to be used in the signal transmission apparatus is a third coding rate less than the second coding rate, when the order of the columns of the first information part is greater than the order of the columns of the second information part. And a third block LDPC codeword is generated by puncturing the first information vector corresponding to the third code rate. The method of claim 41, wherein The encoder; When the order of the columns of the first information part is larger than the order of the columns of the second information part, when the coding rate to be used in the signal transmission apparatus is less than the first coding rate and the fourth coding rate exceeds the second coding rate And a fourth block LDPC codeword is generated by puncturing the first information vector according to the fourth code rate from the first block LDPC codeword. In the method for decoding a block low density parity check (LDPC) code in the signal receiving apparatus, Detecting the information vector by decoding the received signal using the first parity check matrix when the code rate used in the signal transmission apparatus is a first code rate that is a code rate of the first parity check matrix; Detecting the information vector by decoding the information vector using the second parity check matrix when the code rate used in the signal transmission apparatus is a second code rate that is a code rate of a second parity check matrix. The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector, blocks corresponding to the second parity part corresponding to the second parity vector, and third parity parts corresponding to the third parity vector. Classified into corresponding blocks, When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block, blocks corresponding to the second partial block, blocks corresponding to the third partial block, The blocks classified as the second information part are classified into blocks corresponding to the fourth partial block, blocks corresponding to the fifth partial block, blocks corresponding to the sixth partial block, The blocks classified as the first parity part are classified into blocks corresponding to a seventh partial block, blocks corresponding to an eighth partial block, blocks corresponding to a ninth partial block, The blocks classified as the second parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. And the fifteenth partial block has a diagonal relationship with the eleventh partial block in block units, and an identity matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 44, A non-zero matrix is arranged in blocks corresponding to the third partial block and blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, and blocks corresponding to a twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 44, Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in corresponding blocks and blocks corresponding to the fourteenth partial block. The method of claim 44, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, blocks corresponding to the third parity part, and blocks corresponding to a fourth parity part corresponding to a fourth parity vector. Classified, The blocks classified as the first information part are classified into blocks corresponding to the first to third partial blocks and blocks corresponding to a sixteenth partial block. The blocks classified as the second information part are classified into blocks corresponding to the fourth to sixth partial blocks and blocks corresponding to the seventeenth partial block. The blocks classified as the first parity part are classified into blocks corresponding to the seventh to ninth partial blocks and blocks corresponding to the eighteenth partial block. The blocks classified as the second parity part are classified into blocks corresponding to the tenth to 12th partial blocks and blocks corresponding to the nineteenth partial block. The blocks classified as the third parity part are classified into blocks corresponding to the thirteenth to fifteenth partial blocks and blocks corresponding to the twentieth partial block. The blocks classified as the fourth parity part may include blocks corresponding to a twenty-first partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-third partial block, and blocks corresponding to a twenty-fourth partial block. Classified into The twenty-fourth partial block has a diagonal relationship with the fifteenth partial block in block units, and an equality matrix is arranged in blocks corresponding to the twenty-fourth partial block. The method of claim 47, Nonzero matrixes are arranged in blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a sixteenth partial block, and blocks corresponding to a seventeenth partial block. Blocks corresponding to the ninth partial block, blocks corresponding to the twelfth partial block, blocks corresponding to the thirteenth partial block, blocks corresponding to the fourteenth partial block, and eighteenth partial block Blocks corresponding to the twenty-first partial block, blocks corresponding to a nineteenth partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-first partial block, and blocks corresponding to a twenty-second partial block; And a zero matrix is arranged in the blocks corresponding to the twenty-third block. The method of claim 47, Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. Corresponding blocks and blocks corresponding to the fourteenth partial block, blocks corresponding to the sixteenth partial block, blocks corresponding to the seventeenth partial block, blocks corresponding to the eighteenth partial block, Blocks corresponding to the 19th partial block, blocks corresponding to the 20th partial block, blocks corresponding to the 21st partial block, blocks corresponding to the 22nd partial block, and corresponding to the 23rd partial block And a non-zero matrix is arranged in the blocks. The method of claim 44, And the order of the columns of the first information part is different from the order of the columns of the second information part. 51. The method of claim 50, If the order of the columns of the first information part is greater than the order of the columns of the second information part, Inserting 0 into a predetermined position of the received signal when the coding rate used by the signal transmission apparatus is a third subcoding rate less than the second coding rate; And decoding the zero-inserted signal by using the second parity check matrix to detect an information vector. 51. The method of claim 50, If the order of the columns of the first information part is greater than the order of the columns of the second information part, Inserting 0 into a predetermined position of the received signal when the coding rate used in the signal transmission apparatus is less than the first coding rate and a fourth coding rate exceeding a second coding rate; And decoding the zero-inserted signal by using the first parity check matrix to detect an information vector. In the method for decoding a block low density parity check (LDPC) code in the signal receiving apparatus, Detecting the information vector by decoding the received signal using the first parity check matrix when the code rate used in the signal transmission apparatus is a first code rate that is a code rate of the first parity check matrix; Detecting the information vector by decoding the information vector using the second parity check matrix when the code rate used in the signal transmission apparatus is a second code rate that is a code rate of a second parity check matrix. The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector and blocks corresponding to the second parity part corresponding to the second parity vector. When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and blocks corresponding to the second partial block. Blocks classified as the second information part are classified into blocks corresponding to a third partial block and blocks corresponding to a fourth partial block. The blocks classified as the first parity part are classified into blocks corresponding to a fifth partial block and blocks corresponding to a sixth partial block. The blocks classified as the second parity part are classified into blocks corresponding to a seventh partial block and blocks corresponding to an eighth partial block. The method of claim 53, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, and blocks corresponding to a third parity part corresponding to a third parity vector, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and the second partial block, blocks corresponding to the ninth partial block, The blocks classified as the second information part are classified into blocks corresponding to the third partial block and the fourth partial block, blocks corresponding to the tenth partial block, The blocks classified as the first parity part are classified into blocks corresponding to the fifth partial block and the sixth partial block, and blocks corresponding to the eleventh partial block. The blocks classified as the second parity part are classified into blocks corresponding to the seventh and eighth partial blocks and blocks corresponding to the twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a thirteenth partial block, blocks corresponding to a fourteenth partial block, and blocks corresponding to a fifteenth partial block. The fifteenth partial block has a diagonal relationship with the eighth partial block in block units, and an equality matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 53, A non-zero matrix is arranged in blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, and blocks corresponding to the twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 53, Blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, blocks corresponding to the twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in corresponding blocks and blocks corresponding to the fourteenth partial block. The method of claim 53, And the order of the columns of the first information part is different from the order of the columns of the second information part. The method of claim 57, If the order of the columns of the first information part is greater than the order of the columns of the second information part, Inserting 0 into a predetermined position of the received signal when the encoding rate used by the signal transmission apparatus is a third encoding rate less than the second encoding rate; And decoding the zero-inserted signal by using the second parity check matrix to detect an information vector. The method of claim 57, If the order of the columns of the first information part is greater than the order of the columns of the second information part, Inserting 0 into a predetermined position of the received signal when the coding rate used in the signal transmission apparatus is less than the first coding rate and a fourth coding rate exceeding a second coding rate; And decoding the zero-inserted signal by using the first parity check matrix to detect an information vector. In the apparatus for decoding a block low density parity check (LDPC) code in the signal receiving apparatus, If the code rate used by the signal transmission apparatus is the first code rate that is the code rate of the first parity check matrix, the information vector is detected by decoding the received signal using the first parity check matrix, and the code rate used by the signal transmission apparatus is used. And a decoder for detecting the information vector by decoding the information vector using the second parity check matrix when the second code rate is the coding rate of the second parity check matrix. The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector, blocks corresponding to the second parity part corresponding to the second parity vector, and third parity parts corresponding to the third parity vector. Classified into corresponding blocks, When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block, blocks corresponding to the second partial block, blocks corresponding to the third partial block, The blocks classified as the second information part are classified into blocks corresponding to the fourth partial block, blocks corresponding to the fifth partial block, blocks corresponding to the sixth partial block, The blocks classified as the first parity part are classified into blocks corresponding to a seventh partial block, blocks corresponding to an eighth partial block, blocks corresponding to a ninth partial block, The blocks classified as the second parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a tenth partial block, blocks corresponding to an eleventh partial block, and blocks corresponding to a twelfth partial block. And the fifteenth partial block has a diagonal relationship with the eleventh partial block in block units, and an identity matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 60, A non-zero matrix is arranged in blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, and blocks corresponding to a twelfth partial block. And a zero matrix is arranged in the blocks, the blocks corresponding to the thirteenth partial block, and the blocks corresponding to the fourteenth partial block. The method of claim 60, Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in the corresponding blocks and the blocks corresponding to the fourteenth partial block. The method of claim 60, The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, blocks corresponding to the third parity part, and blocks corresponding to a fourth parity part corresponding to a fourth parity vector. Classified, The blocks classified as the first information part are classified into blocks corresponding to the first to third partial blocks and blocks corresponding to a sixteenth partial block. The blocks classified as the second information part are classified into blocks corresponding to the fourth to sixth partial blocks and blocks corresponding to the seventeenth partial block. The blocks classified as the first parity part are classified into blocks corresponding to the seventh to ninth partial blocks and blocks corresponding to the eighteenth partial block. The blocks classified as the second parity part are classified into blocks corresponding to the tenth to 12th partial blocks and blocks corresponding to the nineteenth partial block. The blocks classified as the third parity part are classified into blocks corresponding to the thirteenth to fifteenth partial blocks and blocks corresponding to the twentieth partial block. The blocks classified as the fourth parity part may include blocks corresponding to a twenty-first partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-third partial block, and blocks corresponding to a twenty-fourth partial block. Classified into And the twenty-fourth partial block has a diagonal relationship with the fifteenth partial block in units of blocks, and an identity matrix is arranged in blocks corresponding to the twenty-fourth partial block. The method of claim 63, wherein Nonzero matrixes are arranged in blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a sixteenth partial block, and blocks corresponding to a seventeenth partial block. Blocks corresponding to the ninth partial block, blocks corresponding to the twelfth partial block, blocks corresponding to the thirteenth partial block, blocks corresponding to the fourteenth partial block, and eighteenth partial block Blocks corresponding to the twenty-first partial block, blocks corresponding to a nineteenth partial block, blocks corresponding to a twenty-second partial block, blocks corresponding to a twenty-first partial block, And a zero matrix is arranged in blocks corresponding to a twenty-third block. The method of claim 53, Blocks corresponding to the third partial block, blocks corresponding to a sixth partial block, blocks corresponding to a ninth partial block, blocks corresponding to a twelfth partial block, and a thirteenth partial block. Corresponding blocks and blocks corresponding to the fourteenth partial block, blocks corresponding to the sixteenth partial block, blocks corresponding to the seventeenth partial block, blocks corresponding to the eighteenth partial block, Blocks corresponding to the 19th partial block, blocks corresponding to the 20th partial block, blocks corresponding to the 21st partial block, blocks corresponding to the 22nd partial block, and corresponding to the 23rd partial block And a non-zero matrix is arranged in the blocks. The method of claim 60, And the order of the columns of the first information part is different from the order of the columns of the second information part. The method of claim 66, The decoder; A predetermined position of the received signal when the coding rate used in the signal transmission apparatus is a third coding rate less than the second coding rate when the order of the columns of the first information part is greater than the order of the columns of the second information part And an information vector is detected by inserting 0 into the decoder and decoding the zero-inserted signal using the second parity check matrix. The method of claim 66, The decoder; When the order of the columns of the first information part is greater than the order of the columns of the second information part, the coding rate used by the signal transmission apparatus is less than the first coding rate and the fourth coding rate is greater than the second coding rate. And inserting 0 at a predetermined position of the received signal, and detecting the information vector by decoding the zero-inserted signal by using the first parity check matrix. In the apparatus for decoding a block low density parity check (LDPC) code in the signal receiving apparatus, If the code rate used by the signal transmission apparatus is the first code rate that is the code rate of the first parity check matrix, the information vector is detected by decoding the received signal using the first parity check matrix, and the code rate used by the signal transmission apparatus is used. And a decoder for detecting the information vector by decoding the information vector using the second parity check matrix when the second code rate is the coding rate of the second parity check matrix. The first parity check matrix is generated using a second parity check matrix, and the second parity check matrix includes a plurality of blocks, wherein the plurality of blocks corresponds to information parts corresponding to the information vector. And blocks corresponding to the first parity part corresponding to the first parity vector and blocks corresponding to the second parity part corresponding to the second parity vector. When the information vector includes a first information vector and a second information vector, blocks corresponding to the information part may be included in blocks corresponding to the first information part corresponding to the first information vector and the second information vector. Classified into blocks corresponding to the corresponding second information part, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and blocks corresponding to the second partial block. Blocks classified as the second information part are classified into blocks corresponding to a third partial block and blocks corresponding to a fourth partial block. The blocks classified as the first parity part are classified into blocks corresponding to a fifth partial block and blocks corresponding to a sixth partial block. The blocks classified as the second parity part are classified into blocks corresponding to a seventh partial block and blocks corresponding to an eighth partial block. The method of claim 69, wherein The first parity check matrix includes the second parity check matrix, wherein the first parity check matrix includes blocks corresponding to the first information part, blocks corresponding to the second information part, and the first parity check matrix. Blocks corresponding to one parity part, blocks corresponding to the second parity part, and blocks corresponding to a third parity part corresponding to a third parity vector, The blocks classified as the first information part are classified into blocks corresponding to the first partial block and the second partial block, blocks corresponding to the ninth partial block, The blocks classified as the second information part are classified into blocks corresponding to the third partial block and the fourth partial block, blocks corresponding to the tenth partial block, The blocks classified as the first parity part are classified into blocks corresponding to the fifth partial block and the sixth partial block, and blocks corresponding to the eleventh partial block. The blocks classified as the second parity part are classified into blocks corresponding to the seventh and eighth partial blocks and blocks corresponding to the twelfth partial block. The blocks classified as the third parity part are classified into blocks corresponding to a thirteenth partial block, blocks corresponding to a fourteenth partial block, and blocks corresponding to a fifteenth partial block. The fifteenth partial block has a diagonal relationship with the eighth partial block in block units, and an equality matrix is arranged in blocks corresponding to the fifteenth partial block. The method of claim 69, wherein A non-zero matrix is arranged in blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, and blocks corresponding to the twelfth partial block. And a zero matrix is arranged in the blocks corresponding to the thirteenth partial block and the blocks corresponding to the fourteenth partial block. The method of claim 69, wherein Blocks corresponding to the ninth partial block, blocks corresponding to the tenth partial block, blocks corresponding to the eleventh partial block, blocks corresponding to the twelfth partial block, and a thirteenth partial block. And a non-zero matrix is arranged in the corresponding blocks and the blocks corresponding to the fourteenth partial block. The method of claim 69, wherein And the order of the columns of the first information part is different from the order of the columns of the second information part. The method of claim 73, The decoder; A predetermined position of the received signal when the coding rate used in the signal transmission apparatus is a third coding rate less than the second coding rate when the order of the columns of the first information part is greater than the order of the columns of the second information part And an information vector is detected by inserting 0 into the decoder and decoding the zero-inserted signal using the second parity check matrix. The method of claim 73, The decoder; When the order of the columns of the first information part is greater than the order of the columns of the second information part, the coding rate used by the signal transmission apparatus is less than the first coding rate and the fourth coding rate is greater than the second coding rate. And inserting 0 at a predetermined position of the received signal, and detecting the information vector by decoding the zero-inserted signal by using the first parity check matrix.

Images