CN102752038B - Satellite responder - Google Patents
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- CN102752038B CN102752038B CN201210222833.3A CN201210222833A CN102752038B CN 102752038 B CN102752038 B CN 102752038B CN 201210222833 A CN201210222833 A CN 201210222833A CN 102752038 B CN102752038 B CN 102752038B
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Abstract
The invention relates to a satellite responder, and belongs to the technical field of satellite measurement and control. The satellite responder comprises a reception channel part, a digital processing part, a transmission channel part and a frequency synthesizer, wherein the reception channel part comprises a lower frequency mixer A, a filter and a lower frequency mixer B; the digital processing part comprises an analogue-digital converter (A/D), a digital direct synthesizer DDS 1, a digital direct synthesizer DDS2 and a field programmable gate array (FPGA); the transmission channel part comprises a modulator; and the frequency synthesizer comprises a frequency doubling phase lock A, a frequency doubling phase lock B, a frequency doubling phase lock C, a frequency doubling phase lock D, a frequency shift phase lock A, a frequency shift phase lock B, a clock source selector and an upper mixer. By the digital technology provided by the invention, coherent forwarding functions and non-coherent forwarding functions are realized; spectrum purity and stability of a transmitter are improved; the satellite responder can be directly switched to an external high-stable clock source without converting frequency and generating phase noise loss; the phase nose characteristics of radio frequency are better; and costs are low.
Description
Technical field
The present invention relates to a kind of satellite transponder, belong to satellite survey control technology field.
Background technology
China has carried out the detector that development is upgraded at present, for remoter celestial body is surveyed, comprises Venus, Mars, Jupiter etc.The moon is to approximately 400,000 kilometers of the maximum distances of the earth, and Mars is to approximately 400,000,000 kilometers of the maximum distances of the earth, and distance has been expanded 1000 times.So remote distance, has higher requirement to the sensitivity of answering machine on star.According to budget, need to be better than-150dBm of the sensitivity of answering machine on star.And the only reached-125dBm of receiving sensitivity of the upper answering machine of the moonik CE-1/2 having flown at present.
Summary of the invention
The object of the invention is, in order to overcome the deficiencies in the prior art, to propose a kind of satellite transponder.
The object of the invention is to be achieved through the following technical solutions.
A kind of satellite transponder of the present invention, comprises receive path part, digital processing part, transmission channel part and frequency synthesizer;
Receive path part comprises down-conversion mixer A, filter and down-conversion mixer B; Up radiofrequency signal and the local oscillation signal 1 that the phase-locked A of frequency multiplication sends from frequency synthesizer pass through the low frequency signal that is mixed to form of down-conversion mixer A, low frequency signal after filtering device filters, the signal that device filters after filtering and the local oscillation signal 2 that the phase-locked A of shift frequency sends from frequency synthesizer, through the mixing of down-conversion mixer B, form intermediate-freuqncy signal and input to digital processing part;
Digital processes is divided and is comprised analog digital converter A/D, digital frequency synthesizer DDS1, digital frequency synthesizer DDS2 and FPGA; Analog digital converter A/D receives the intermediate-freuqncy signal passing over from receive path part, signal is carried out to A/D sampling, intermediate-freuqncy signal is become to digital signal, then digital signal is flowed to FPGA, FPGA carries out Doppler tracking locking and demodulation to the digital signal receiving, extract Doppler's composition, control figure frequency synthesizer DDS1 and DDS2, generate respectively Doppler's reference signal 1 and Doppler's reference signal 2 and flow to respectively the phase-locked A of shift frequency and the phase-locked B of shift frequency; Doppler's reference signal 1 is relevant with the Doppler frequency composition in up radiofrequency signal, completes coherent carrier and catches and follow the tracks of; FPGA produces Doppler's reference signal 2 by numerical calculation; When the frequency content of Doppler's reference signal 2 and Doppler's reference signal 1 are when relevant, and meet predetermined ratio k, realize the relevant function of transmitting-receiving of system requirements; In the time that Doppler's reference signal 2 and Doppler's reference signal 1 are irrelevant, realize the incoherent function of transmitting-receiving of system requirements;
Transmission channel part comprises modulator; Modulator receives the local oscillation signal 3 sending out from frequency synthesizer, local oscillation signal 3 use base band datas is modulated to output downlink radio-frequency signal; Local oscillation signal 3 is radiofrequency signals that down-Doplet reference signal that the high frequency clock signal that sends of the phase-locked B of frequency multiplication and the phase-locked B of shift frequency send forms after upper frequency mixer carries out mixing;
Frequency synthesizer comprises the phase-locked A of frequency multiplication, the phase-locked B of frequency multiplication, the phase-locked C of frequency multiplication, the phase-locked D of frequency multiplication, the phase-locked A of shift frequency, the phase-locked B of shift frequency, clock source selection device and upper frequency mixer; Clock source selection device is selected in inner temperature compensating crystal oscillator TCXO clock and the steady clock of outside superelevation, the clock reference using the clock of choosing as frequency synthesizer; The phase-locked A of frequency multiplication, the phase-locked B of frequency multiplication, the phase-locked C of frequency multiplication, the phase-locked D of frequency multiplication form high frequency clock signal by clock reference frequency multiplication respectively; The high frequency clock signal of formation is sent to the phase-locked A of shift frequency by the phase-locked C of frequency multiplication, and the high frequency clock signal receiving and Doppler's reference signal 1 are carried out shift frequency by the phase-locked A of shift frequency, forms local oscillation signal 2; The high frequency clock signal of formation is sent to the phase-locked B of shift frequency by the phase-locked D of frequency multiplication, and the high frequency clock signal receiving and Doppler's reference signal 2 are carried out shift frequency by the phase-locked B of shift frequency, forms down-Doplet reference signal.
Beneficial effect
Digital technology of the present invention realizes coherent forwarding function and incoherent forwarding capability, has the characteristic of " software exchange ", has strengthened flexibility; Utilize numerical frequency complex art, produce needed working frequency points, can realize different RF spots according to mission requirements, expanded function; Transmitter spectrum purity and stability are improved; Can be directly switch to outside high steady clock source, without through frequency inverted, not produce the loss of making an uproar mutually, the radio frequency characteristic of making an uproar is mutually better; Cost is low.
Brief description of the drawings
Fig. 1 is the composition schematic diagram of satellite transponder of the present invention;
Fig. 2 is the composition schematic diagram of the phase-locked A of frequency multiplication;
Fig. 3 is the composition schematic diagram of the phase-locked C of frequency multiplication;
Fig. 4 is the composition schematic diagram of the phase-locked A of shift frequency;
Fig. 5 is the composition schematic diagram of the phase-locked B of frequency multiplication;
Fig. 6 is the composition schematic diagram of the phase-locked D of frequency multiplication;
Fig. 7 is the composition schematic diagram of the phase-locked B of shift frequency.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.
Embodiment
Taking X frequency range transmitting-receiving answering machine as example, the forwarding of system requirements is than frequency=880/749 of the frequency of K=downlink radio-frequency signal/up radiofrequency signal; The frequency that designs up radiofrequency signal is 7115.5MHz, and the frequency that requires downlink radio-frequency signal is 8360MHz, wherein 8360/7115.5=K.Under Coherence Mode, if there is certain Doppler frequency deviation fd=74.9KHz in the frequency of the up radiofrequency signal that answering machine receives, the frequency of up radiofrequency signal becomes 7115.5MHz+fd=7115.5749MHz, the frequency of the downlink radio-frequency signal of answering machine transmitting should become 8360.088MHz thereupon so, remains the frequency=K of the frequency/up radiofrequency signal of downlink radio-frequency signal.And under incoherent pattern, the downstream frequency of answering machine transmitting should remain 8360MHz.
Satellite transponder, as shown in Figure 1, comprises receive path part, digital processing part, transmission channel part and frequency synthesizer;
Internal clock source design TCXO Frequency Design is 100MHz, and the steady clock source frequency of outside superelevation is 10MHz.In the time that reference clock selector is selected TCXO as clock reference, obtain following design parameter.
The Frequency Design of the local oscillation signal 1 of the phase-locked A output of frequency multiplication is 7000MHz, and the composition schematic diagram of the phase-locked A of frequency multiplication as shown in Figure 2; The course of work of the phase-locked A of frequency multiplication is: the input clock of the phase-locked A of frequency multiplication is from frequency source selector, and frequency is 100MHz; Input clock is through 10 frequency dividers of software control, and frequency drops to 10MHz; The initial output signal frequency of voltage controlled oscillator (VCO) is at 7000MHz, and through 700 frequency dividers, frequency drops to 10MHz; This two-way 10MHz signal enters phase discriminator (PD), generates phase demodulation error signal, carries out low-pass filtering through loop filter (Loop Filter), and filtered error signal is for regulating the output frequency of VCO; Through the phase-locked A circuit of this frequency multiplication, make the output frequency of VCO and 100MHz clock keep locking, obtain the local oscillation signal 1 of 7000MHz;
The composition schematic diagram of the phase-locked C of frequency multiplication as shown in Figure 3; Output clock frequency is 90MHz, and its course of work is with the phase-locked A of frequency multiplication.
The composition schematic diagram of the phase-locked A of shift frequency as shown in Figure 4; The course of work of the phase-locked A of shift frequency is: being 90MHz from the frequency of the phase-locked C of frequency multiplication, is 10M+fd from the frequency of DDS1; The initial output frequency of VCO, at 100MHz, carries out after lower mixing with the 90MHz clock from the phase-locked C of frequency multiplication, forms the low frequency signal of 10MHz.This low frequency signal enters phase discriminator (PD) with the 10M+fd signal that comes from DDS1, the error signal that phase demodulation generates is carried out low-pass filtering through loop filter (Loop Filter), and filtered error signal is for regulating the output frequency of VCO.Through shift frequency phase-locked A circuit, make the output frequency of VCO equal the output frequency sum of the phase-locked C of frequency multiplication and DDS1, obtain frequency=100M+fd of the phase-locked C of frequency+frequency multiplication of the frequency=DDS1 of local oscillation signal 2;
Receive path part comprises down-conversion mixer A, filter and down-conversion mixer B; Up radiofrequency signal and the local oscillation signal 1 that the phase-locked A of frequency multiplication sends from frequency synthesizer pass through the low frequency signal that is mixed to form of down-conversion mixer A, low frequency signal after filtering device filters, the signal that device filters after filtering and the local oscillation signal 2 that the phase-locked A of shift frequency sends from frequency synthesizer, through the mixing of down-conversion mixer B, form intermediate-freuqncy signal and input to digital processing part;
Digital processes is divided and is comprised analog digital converter A/D, digital frequency synthesizer DDS1, digital frequency synthesizer DDS2 and FPGA; Analog digital converter A/D receives the intermediate-freuqncy signal passing over from receive path part, signal is carried out to A/D sampling, intermediate-freuqncy signal is become to digital signal, then digital signal is flowed to FPGA, FPGA carries out Doppler tracking locking and demodulation to the digital signal receiving, extract Doppler's composition, control figure frequency synthesizer DDS1 and DDS2, generate respectively Doppler's reference signal 1 and Doppler's reference signal 2 and flow to respectively the phase-locked A of shift frequency and the phase-locked B of shift frequency; Doppler's reference signal 1 is relevant with the Doppler frequency composition in the up radiofrequency signal receiving, and completes coherent carrier and catches and follow the tracks of; FPGA produces Doppler's reference signal 2 by numerical calculation;
The frequency of Doppler's reference signal 1 is 10MHz+fd.Wherein fd=74.9KHz, the actual frequency of Doppler's reference signal 1 is 10.0749MHz.
Under Coherence Mode, the frequency of Doppler's reference signal 2 is 10MHz+fd*K, wherein K=880/749, and the actual frequency of Doppler's reference signal 2 is 10.088MHz.And under incoherent pattern, the output frequency of Doppler's reference signal 2 is fixed as 10MHz.
Transmission channel part comprises modulator; Modulator receives the local oscillation signal 3 sending out from frequency synthesizer, local oscillation signal 3 use base band datas is modulated to output downlink radio-frequency signal; Local oscillation signal 3 is radiofrequency signals that down-Doplet reference signal that the high frequency clock signal that sends of the phase-locked B of frequency multiplication and the phase-locked B of shift frequency send forms after upper frequency mixer carries out mixing;
Frequency synthesizer comprises the phase-locked A of frequency multiplication, the phase-locked B of frequency multiplication, the phase-locked C of frequency multiplication, the phase-locked D of frequency multiplication, the phase-locked A of shift frequency, the phase-locked B of shift frequency, clock source selection device and upper frequency mixer; Clock source selection device is selected in inner temperature compensating crystal oscillator TCXO clock and the steady clock of outside superelevation, the clock reference using the clock of choosing as frequency synthesizer; Clock reference frequency multiplication is formed high frequency clock signal by frequency-doubled signal; The high frequency clock signal of formation is sent to the phase-locked A of shift frequency by the phase-locked C of frequency multiplication, and the high frequency clock signal receiving and Doppler's reference signal 1 are carried out shift frequency by the phase-locked A of shift frequency, forms local oscillation signal 2; The high frequency clock signal of formation is sent to the phase-locked B of shift frequency by the phase-locked D of frequency multiplication, and the high frequency clock signal receiving and Doppler's reference signal 2 are carried out shift frequency by the phase-locked B of shift frequency, forms down-Doplet reference signal;
The output high power clock frequency of the phase-locked B of frequency multiplication is designed to 8000MHz, and the composition schematic diagram of the phase-locked B of frequency multiplication as shown in Figure 5; Its course of work is with the phase-locked A of frequency multiplication;
The output high power clock frequency of the phase-locked D of frequency multiplication is designed to 350MHz, and the composition schematic diagram of the phase-locked D of frequency multiplication as shown in Figure 6; Its course of work is with the phase-locked A of frequency multiplication;
The incoming frequency of the phase-locked B of shift frequency is that the composition schematic diagram of the phase-locked B of shift frequency as shown in Figure 7 from the 350MHz of the phase-locked D of frequency multiplication with from Doppler's reference signal 2 of DDS2; Its course of work is with the phase-locked A of shift frequency;
And the frequency of local oscillation signal 3 is the mixing results of 8000MHz and 360MHz+fd*K, therefore the frequency of local oscillator 3 is 8360MHz+fd*K.Under Coherence Mode, if fd=74.9KHz, the frequency of local oscillation signal 3 is 8360.088MHz.Under incoherent pattern, because the frequency of DDS2 output is fixed as 10MHz, therefore the frequency of local oscillation signal 3 is 8360MHz.
In the time that frequency synthesizer is selected the TCXO of 100MHz as clock reference, the phase-locked A of frequency multiplication, the phase-locked B of frequency multiplication, the phase-locked C of frequency multiplication, the phase-locked D of frequency multiplication, running parameter.As required, by software control, on star, answering machine can be switched to clock source outside 10MHz source at any time, and each frequency multiplication is phase-locked by software instruction simultaneously, changes 10 frequency dividers of its inside into straight-through (not frequency division).The phase-locked output frequency of each frequency multiplication is constant like this, but overall frequency all keeps Phase-Locked Synchronous with the high steady source of outside 10MHz of input.
Claims (3)
1. a satellite transponder, is characterized in that: comprise receive path part, digital processing part, transmission channel part and frequency synthesizer;
Receive path part comprises down-conversion mixer A, filter and down-conversion mixer B; Up radiofrequency signal and the local oscillation signal 1 that the phase-locked A of frequency multiplication sends from frequency synthesizer pass through the low frequency signal that is mixed to form of down-conversion mixer A, low frequency signal after filtering device filters, the signal that device filters after filtering and the local oscillation signal 2 that the phase-locked A of shift frequency sends from frequency synthesizer, through the mixing of down-conversion mixer B, form intermediate-freuqncy signal and input to digital processing part;
Digital processes is divided and is comprised analog digital converter A/D, digital frequency synthesizer DDS1, digital frequency synthesizer DDS2 and FPGA; Analog digital converter A/D receives the intermediate-freuqncy signal passing over from receive path part, signal is carried out to A/D sampling, intermediate-freuqncy signal is become to digital signal, then digital signal is flowed to FPGA, FPGA carries out Doppler tracking locking and demodulation to the digital signal receiving, extract Doppler's composition, control figure frequency synthesizer DDS1 and DDS2, generate respectively Doppler's reference signal 1 and Doppler's reference signal 2 and flow to respectively the phase-locked A of shift frequency and the phase-locked B of shift frequency; Doppler's reference signal 1 is relevant with the Doppler frequency composition in up radiofrequency signal, completes coherent carrier and catches and follow the tracks of; FPGA produces Doppler's reference signal 2 by numerical calculation; When the frequency content of Doppler's reference signal 2 and Doppler's reference signal 1 are when relevant, and meet predetermined ratio k, realize the relevant function of transmitting-receiving of system requirements; In the time that Doppler's reference signal 2 and Doppler's reference signal 1 are irrelevant, realize the incoherent function of transmitting-receiving of system requirements;
Under Coherence Mode, if there is certain Doppler frequency deviation fd in the frequency of the up radiofrequency signal that answering machine receives, the frequency of up radiofrequency signal increases fd, the frequency of the downlink radio-frequency signal of answering machine transmitting increases k × fd so, remains the frequency=k of the frequency/up radiofrequency signal of downlink radio-frequency signal; And under incoherent pattern, the downstream frequency of answering machine transmitting remains constant;
Transmission channel part comprises modulator; Modulator receives the local oscillation signal 3 sending out from frequency synthesizer, local oscillation signal 3 use base band datas is modulated to output downlink radio-frequency signal; Local oscillation signal 3 is radiofrequency signals that down-Doplet reference signal that the high frequency clock signal that sends of the phase-locked B of frequency multiplication and the phase-locked B of shift frequency send forms after upper frequency mixer carries out mixing;
Frequency synthesizer comprises the phase-locked A of frequency multiplication, the phase-locked B of frequency multiplication, the phase-locked C of frequency multiplication, the phase-locked D of frequency multiplication, the phase-locked A of shift frequency, the phase-locked B of shift frequency, clock source selection device and upper frequency mixer; Clock source selection device is selected in inner temperature compensating crystal oscillator TCXO clock and the steady clock of outside superelevation, the clock reference using the clock of choosing as frequency synthesizer; The phase-locked A of frequency multiplication, the phase-locked B of frequency multiplication, the phase-locked C of frequency multiplication, the phase-locked D of frequency multiplication form high frequency clock signal by clock reference frequency multiplication respectively; The high frequency clock signal of formation is sent to the phase-locked A of shift frequency by the phase-locked C of frequency multiplication, and the high frequency clock signal receiving and Doppler's reference signal 1 are carried out shift frequency by the phase-locked A of shift frequency, forms local oscillation signal 2; The high frequency clock signal of formation is sent to the phase-locked B of shift frequency by the phase-locked D of frequency multiplication, and the high frequency clock signal receiving and Doppler's reference signal 2 are carried out shift frequency by the phase-locked B of shift frequency, forms down-Doplet reference signal.
2. a kind of satellite transponder according to claim 1, is characterized in that: the phase-locked A of frequency multiplication comprises frequency divider A, frequency divider B, phase discriminator, voltage controlled oscillator and loop filter; The input clock of the phase-locked A of frequency multiplication obtains the signal that frequency is A after frequency divider A; The initial output signal of voltage controlled oscillator obtains the signal that frequency is B after frequency divider B, frequency is that the signal of A and signal that frequency is B generate phase demodulation error signal after phase discriminator, this error signal is carried out low-pass filtering through loop filter, filtered error signal is for regulating the output frequency of voltage controlled oscillator, this output frequency and input clock keep locking, obtain local oscillation signal 1.
3. a kind of satellite transponder according to claim 1, is characterized in that: the phase-locked A of shift frequency comprises phase discriminator, loop filter, voltage controlled oscillator and down-conversion mixer; The initial output frequency of voltage controlled oscillator with carry out forming low frequency signal after lower mixing from the clock of the phase-locked C of frequency multiplication; This low frequency signal enters phase discriminator with together with signal from DDS1; The error signal that phase demodulation generates is carried out low-pass filtering through loop filter, and filtered error signal is for regulating the output frequency of voltage controlled oscillator, i.e. local oscillation signal 2; The frequency of local oscillation signal 2 equals the output frequency sum of the phase-locked C of frequency multiplication and DDS1.
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| CN102916692B (en) * | 2012-10-28 | 2015-01-14 | 中国电子科技集团公司第十研究所 | Digital phase parameter transmission method based on any transmission ratio |
| CN104092478B (en) * | 2014-06-27 | 2017-04-05 | 上海航天电子通讯设备研究所 | A kind of multi-functional answering machine of spaceborne X band Dual Channels |
| CN106781374A (en) * | 2016-12-01 | 2017-05-31 | 广东技术师范学院 | A kind of self adaptation frequency corrects wireless remote controller |
| CN106877887B (en) * | 2017-01-20 | 2019-05-07 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multistation alien frequencies response receives system |
| CN109245797A (en) * | 2018-08-22 | 2019-01-18 | 西安空间无线电技术研究所 | A kind of unified carrier system signal coherence forwarding realization method and system |
| CN112947521B (en) * | 2021-02-10 | 2022-10-28 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Multifunctional simulation platform of spacecraft measurement and control system |
| CN113067599B (en) * | 2021-03-12 | 2022-07-15 | 上海航天电子有限公司 | Semi-digital USB responder device based on anti-fuse FPGA |
| CN113791556A (en) * | 2021-08-31 | 2021-12-14 | 上海卫星工程研究所 | Method and system for autonomously detecting and switching internal and external clocks of responder |
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