CN102332975A - Method and device for self-adaptively sampling interface - Google Patents

Abstract

The invention provides a method and device for self-adaptively sampling an interface. The method comprises the following steps of: detecting the cycle of a receiving clock; detecting a corresponding relation value of the receiving clock and receiving data; calculating the generation time of a sampling enabling signal according to the relation between the cycle and a phase relation value; and generating the sampling enabling signal within the generation time of the sampling enabling signal and sampling a receiving data signal according to the sampling enabling signal. According to the invention, the problem that the sampling is mistaken because whether the clock and the data are matched cannot be accurately judged in the prior art is solved; and the data can be ensured to be unchanged within the front and back cycles of sampling points, and further the effect of accurately sampling is achieved.

Description

A kind of interface adaptive method of sampling and device

Technical field

The present invention relates to the communications field, particularly a kind of interface adaptive method of sampling and device.

Background technology

As depicted in figs. 1 and 2, d type flip flop is also referred to as and keeps-block the edge d type flip flop, the major function of d type flip flop be and only in the moment of rising edge of clock signal (clock signal becomes 1 from 0), data output is delivered in the data input.

This function of d type flip flop also can be called the sampling to input signal.Basically all systems are being connected with external system, or carry out signal when transmitting between each chip of internal system, all are at first through d type flip flop signal to be sampled, and then send into that internal system handles.

In practical application, signal becomes 1 or become 0 from 1 and all need the regular hour from 0, and is as shown in Figure 3, and signal becomes time of 1 from 0 and is called the rise time, and signal becomes time of 0 from 1 and is called fall time.

D type flip flop is at the rising edge sampled input signal of clock, if input signal is 0, then exporting signal is 0, and input signal is 1, and output also is 1.

When the clock rising edge, in (promptly in rise time or fall time) between 0 to 1, output is unsettled to input signal, possibly export 0, also possibly export 1 just, also might be in the state in the middle of 0 and 1.

Therefore,, need certain requirement be arranged to settling time and retention time for d type flip flop, promptly must be greater than the numerical value of certain setting.

Settling time (setup time): when rising edge clock arrived, signal stabilization was in the time of a certain state (0 or 1), i.e. 1 among Fig. 4.

Retention time (hold time): after rising edge clock, signal still is stable at the time of a certain state (0 or 1), i.e. 2 among Fig. 4.

Sequential in the digital circuit is meant the relation of two or more signals on time and phase place, and promptly sequential refers to settling time and retention time between signal and the clock emphatically in this explanation.

Sequential satisfies: the settling time between signal and the clock and retention time are satisfied d type flip flop to the requirement of foundation and retention time, and promptly more than or equal to the numerical value of this setting, d type flip flop is sampled signal correctly, and system works is normal.

Sequential does not satisfy: the settling time between signal and the clock and retention time are not satisfied d type flip flop to the requirement of foundation and retention time, and promptly less than the numerical value of this setting, d type flip flop is sampled signal correctly, the system works mistake.

Sequential is critical: though settling time between signal and the clock and retention time are satisfied the requirement of d type flip flop, surplus is very little, is easy to because the variation of environment or other factors causes sequential not satisfy.

In the operational environment of reality, the recipient is also indeterminate to the sequential that transmit leg sends, and the length of cable of each interface; Postpone all to be not quite similar; The variation of ambient temperature also can influence timing sequence generating, recipient's the ungratified situation of sequential often takes place, so be necessary to design a kind of method of practicality; Adjustment recipient's sequential is perhaps sampled in data stabilization constantly.

Existing way normally adopts high frequency clock to detect the clock and the data-signal of interface, when clock and data change simultaneously, sample circuit is exported in the clock negate.Such way has following shortcoming:

To clock and data whether with when judging, judge easily inaccurate, thereby may shorten the usefulness of sampling inadequately with the sampling time settling time this moment, then can directly cause subsequent sampling to be made mistakes, therefore this way instability; Simultaneously, this way data sampling still adopts outside input clock, therefore is unfavorable for the Synchronous Processing that signal is follow-up.

Summary of the invention

Whether main purpose of the present invention is to provide a kind of interface adaptive method of sampling and device, judge inaccurate and problem that cause sampling and make mistakes with the edge to solve in the prior art to clock and data.

According to an aspect of the present invention, a kind of interface adaptive method of sampling is provided, this method comprises: the cycle of detecting receive clock; Detect receive clock and the phase relation value that receives data; According to the relation of cycle and phase relation value, calculating sampling enable signal generation time; Produce sample enable signal at the sample enable signal generation time, sample to receiving data-signal according to sample enable signal.

The step of calculating sampling enable signal generation time comprises: when receive clock and the phase relation value that receives data during less than the sampling offset sum of the sampling time value of receive clock and receive clock, the sample enable signal generation time is that phase relation value and sampling time value sum deduct the sampling offset; When receive clock and the phase relation value that receives data during more than or equal to the sampling offset sum of the sampling time value of receive clock and receive clock, the sample enable signal generation time is that the difference of phase relation value and sampling time value deducts the sampling offset.

Before the step in the cycle of detection receive clock; The interface adaptive method of sampling also comprises: adopt high frequency clock that receive clock is carried out the sampling of two-stage register; Export first receive clock and second receive clock respectively; The logical AND processing is carried out in the second receive clock negate and the first receive clock signal, obtained the rising edge of receive clock; Adopt high frequency clock will receive data and carry out the sampling of two-stage register, export first respectively and receive data and second and receive data, receive data with second and carry out the XOR processing, obtain receiving the variation edge of data with the first reception data-signal.

The step that detects the cycle of receive clock comprises: the cycle of detecting receive clock according to the rising edge of receive clock.

The step that detects receive clock and receive the phase relation value between the data comprises: according to the rising edge of receive clock and the variation that receives data along detecting receive clock and receiving the phase relation value between the data.

According to a further aspect in the invention, a kind of interface adaptive sampling apparatus is provided, this device comprises: first detecting unit is used to detect cycle of receive clock; Second detecting unit is used to detect receive clock and the phase relation value that receives data; Computing unit is used for the relation according to cycle and phase relation value, calculating sampling enable signal generation time; Sampling unit is used for producing sample enable signal at the sample enable signal generation time, samples to receiving data-signal according to sample enable signal.

Computing unit is calculating sampling enable signal generation time in the following manner: when receive clock and the phase relation value that receives data during less than the sampling offset sum of the sampling time value of receive clock and receive clock, the sample enable signal generation time is that phase relation value and sampling time value sum deduct the sampling offset; When receive clock and the phase relation value that receives data during more than or equal to the sampling offset sum of the sampling time value of receive clock and receive clock, the sample enable signal generation time is that the difference of phase relation value and sampling time value deducts the sampling offset.

The interface adaptive sampling apparatus also comprises: processing unit; Be used to adopt high frequency clock that receive clock is carried out the sampling of two-stage register; Export first receive clock and second receive clock respectively; The logical AND processing is carried out in the second receive clock negate and the first receive clock signal, obtained the rising edge of receive clock; And adopt high frequency clock will receive data and carry out the sampling of two-stage register, export first respectively and receive data and second and receive data, receive data with second and carry out the XOR processing with the first reception data-signal, obtain receiving the variation edge of data.

First detecting unit specifically is used for detecting according to the rising edge of receive clock the cycle of receive clock.

Second detecting unit specifically is used for based on the rising edge of receive clock and the variation that receives data along detecting receive clock and receiving the phase relation value between the data.

Through the present invention; Employing is obtained sample enable signal according to the phase relation between receive clock and the reception data; And sample according to this sample enable signal, solved in the prior art clock and data whether with along judging inaccurate and problem that cause sampling and make mistakes, guarantee that front and back at sampled point are in the cycle; Data can not change, and then have reached the effect of correct sampling.

Description of drawings

Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:

Fig. 1 is the d type flip flop sketch map according to correlation technique;

Fig. 2 is the d type flip flop functional schematic according to correlation technique;

Fig. 3 is rise time, the fall time sketch map according to correlation technique;

Fig. 4 is settling time, the retention time sketch map according to correlation technique;

Fig. 5 is a kind of preferred structure block diagram according to the interface adaptive sampling apparatus of the embodiment of the invention;

Fig. 6 is the another kind of structured flowchart according to the interface adaptive sampling apparatus of the embodiment of the invention;

Fig. 7 is a kind of preferred flow charts according to the interface adaptive method of sampling of the embodiment of the invention;

Fig. 8 is the another kind of flow chart according to the interface adaptive method of sampling of the embodiment of the invention;

Fig. 9 is the enable signal generation sketch map according to the interface adaptive method of sampling of the embodiment of the invention;

Figure 10 is another structured flowchart according to the interface adaptive sampling apparatus of the embodiment of the invention;

Figure 11 is the timing diagram according to the RXC rising edge extraction of the embodiment of the invention;

Figure 12 is the RXC cycle detection sketch map according to the embodiment of the invention;

Figure 13 is the timing diagram that changes the edge extraction according to the RXD of the embodiment of the invention;

Figure 14 is the phase extraction sketch map according to the RXC of the embodiment of the invention and RXD.

Figure 15 is a kind of sample enable signal output sketch map according to the embodiment of the invention;

Figure 16 is the another kind of sample enable signal output sketch map according to the embodiment of the invention;

Figure 17 is the data sampling sketch map according to the embodiment of the invention.

Embodiment

Hereinafter will and combine embodiment to specify the present invention with reference to accompanying drawing.Need to prove that under the situation of not conflicting, embodiment and the characteristic among the embodiment among the application can make up each other.

Embodiment 1

Fig. 5 has shown a kind of preferred structure block diagram of interface adaptive sampling apparatus; Referring to Fig. 5; This device comprises: connect first detecting unit 502 second detecting unit 504, connect the computing unit 506 of first detecting unit 502 and second detecting unit 504; The sampling unit 508 that connects computing unit 506, wherein:

First detecting unit 502 detects the cycle of receive clock;

Second detecting unit 504 detects receive clock and the phase relation value that receives data;

Computing unit 506 is according to the relation of cycle and phase relation value, calculating sampling enable signal generation time;

Sampling unit 508 produces sample enable signal at the sample enable signal generation time, samples to receiving data-signal according to sample enable signal.

In this preferred embodiment; Employing is obtained sample enable signal according to the phase relation between receive clock and the reception data; And sample according to this sample enable signal, solved in the prior art clock and data whether with along judging inaccurate and problem that cause sampling and make mistakes, guarantee that front and back at sampled point are in the cycle; Data can not change, and then have reached the effect of correct sampling.

Wherein, Computing unit 506 is calculating sampling enable signal generation time in the following manner: when receive clock and the phase relation value that receives data during less than the sampling offset sum of the sampling time value of receive clock and receive clock, the sample enable signal generation time is that phase relation value and sampling time value sum deduct the sampling offset; When receive clock and the phase relation value that receives data during more than or equal to the sampling offset sum of the sampling time value of receive clock and receive clock, the sample enable signal generation time is that the difference of phase relation value and sampling time value deducts the sampling offset.

Sampling time value is illustrated in cycle of receive clock and when samples, and for example: when sampling as sampled point with the centre position of the pulsewidth that receives data, this sampling time value is cycle half the of receive clock, i.e. cycle/2 of receive clock.

Based on Fig. 5; Fig. 6 has shown the another kind of structured flowchart of interface adaptive sampling apparatus, and wherein, the interface adaptive sampling apparatus also comprises: the processing unit 510 that connects first detecting unit 502 and second detecting unit 504; Processing unit 510 adopts high frequency clock that receive clock is carried out the sampling of two-stage register; Export first receive clock and second receive clock respectively, the logical AND processing is carried out in the second receive clock negate and the first receive clock signal, obtain the rising edge of receive clock; And adopt high frequency clock will receive data and carry out the sampling of two-stage register, export first respectively and receive data and second and receive data, receive data with second and carry out the XOR processing with the first reception data-signal, obtain receiving the variation edge of data.

Wherein, first detecting unit 502 specifically is used for detecting according to the rising edge of receive clock the cycle of receive clock.Second detecting unit 504 specifically is used for according to the rising edge of receive clock and the variation that receives data along detecting receive clock and receiving the phase relation value between the data.

For example: computing unit 506 is calculating sampling enable signal generation time in the following manner:

When $\mathrm{Rxc}\_\mathrm{Rxd}\_\mathrm{Inval}<\frac{\mathrm{Rxc}\_\mathrm{<figure-callout\; id="2"\; label="Perior"\; filenames="HDA0000066319320000052.png,HDA0000066319320000071.png"\; state="\{\{state\}\}">Perior</figure-callout>}}{2}+2$ The time,

$\mathrm{rxc}\_\mathrm{shift}\_\mathrm{val}=\mathrm{rxc}\_\mathrm{rxd}\_\mathrm{inval}+\frac{\mathrm{rxc}\_\mathrm{perior}}{2}-2;$

When $\mathrm{Rxc}\_\mathrm{Rxd}\_\mathrm{Inval}\&GreaterEqual;\frac{\mathrm{Rxc}\_\mathrm{<figure-callout\; id="2"\; label="Perior"\; filenames="HDA0000066319320000052.png,HDA0000066319320000071.png"\; state="\{\{state\}\}">Perior</figure-callout>}}{2}+2$ The time,

$\mathrm{rxc}\_\mathrm{shift}\_\mathrm{val}=\mathrm{rxc}\_\mathrm{rxd}\_\mathrm{inval}-\frac{\mathrm{rxc}\_\mathrm{perior}}{2}-2;$

Wherein, When rxc_perior is uneven number; Its 1/2 value is got its integer part, and rxc_perior is the cycle of detected receive clock, and rxc_rxd_inval is detected receive clock and the phase relation value that receives data; Rxc_shift_val is the sample enable signal generation time, adds 2 or to subtract 2 are compensation to two-stage register sampling in the formula.

Wherein, the cycle of receive clock is: the count value of the counter of employing and high frequency clock same frequency between the rising edge of two adjacent receive clocks;

The phase relation value of receive clock and reception data is: the rising edge of adjacent receive clock is to the count value of the counter of employing between the variation edge that receives data and high frequency clock same frequency;

The time that sample enable signal produces is: during the value of the time that the sample enable signal that equals to calculate in the rolling counters forward value that adopts with the high frequency clock same frequency produces, and the output sample enable signal.

Below only be to be employed in the middle part that receives data pulse widths to calculate,, also can adopt other positions that receive data pulse widths to calculate as sampled point under the prerequisite of spirit of the present invention as sampled point.

Embodiment 2

Fig. 7 has shown a kind of preferred flow charts of the interface adaptive method of sampling, and referring to Fig. 7, this method comprises:

S702, the cycle of detection receive clock;

S704 detects receive clock and the phase relation value that receives data;

S706, according to the relation of cycle and phase relation value, calculating sampling enable signal generation time;

S708 produces sample enable signal at the sample enable signal generation time, samples to receiving data-signal based on sample enable signal.

In this preferred embodiment; Employing is obtained sample enable signal according to the phase relation between receive clock and the reception data; And sample according to this sample enable signal, solved in the prior art clock and data whether with along judging inaccurate and problem that cause sampling and make mistakes, guarantee that front and back at sampled point are in the cycle; Data can not change, and then have reached the effect of correct sampling.

Wherein when step S706, through following mode calculating sampling enable signal generation time:

When receive clock and the phase relation value that receives data during less than the sampling offset sum of the sampling time value of receive clock and receive clock, the sample enable signal generation time is that phase relation value and sampling time value sum deduct the sampling offset; When receive clock and the phase relation value that receives data during more than or equal to the sampling offset sum of the sampling time value of receive clock and receive clock, the sample enable signal generation time is that the difference of phase relation value and sampling time value deducts the sampling offset.

Based on Fig. 7, Fig. 8 has shown the another kind of flow chart of the interface adaptive method of sampling, wherein, step S702, before the step in the cycle of detection receive clock, the interface adaptive method of sampling also comprises:

Step S701 adopts high frequency clock that receive clock is carried out the sampling of two-stage register, exports first receive clock and second receive clock respectively, and the logical AND processing is carried out in the second receive clock negate and the first receive clock signal, obtains the rising edge of receive clock; And adopt high frequency clock will receive data and carry out the sampling of two-stage register, export first respectively and receive data and second and receive data, receive data with second and carry out the XOR processing with the first reception data-signal, obtain receiving the variation edge of data.

Wherein, S702, the step that detects the cycle of receive clock comprises: the cycle of detecting receive clock according to the rising edge of receive clock.

S704, the step that detects receive clock and receive the phase relation value between the data comprises: according to the rising edge of receive clock and the variation that receives data along detecting receive clock and receiving the phase relation value between the data.

For example: through following mode calculating sampling enable signal generation time:

When $\mathrm{Rxc}\_\mathrm{Rxd}\_\mathrm{Inval}<\frac{\mathrm{Rxc}\_\mathrm{<figure-callout\; id="2"\; label="Perior"\; filenames="HDA0000066319320000052.png,HDA0000066319320000071.png"\; state="\{\{state\}\}">Perior</figure-callout>}}{2}+2$ The time,

$\mathrm{rxc}\_\mathrm{shift}\_\mathrm{val}=\mathrm{rxc}\_\mathrm{rxd}\_\mathrm{inval}+\frac{\mathrm{rxc}\_\mathrm{perior}}{2}-2;$

When $\mathrm{Rxc}\_\mathrm{Rxd}\_\mathrm{Inval}\&GreaterEqual;\frac{\mathrm{Rxc}\_\mathrm{<figure-callout\; id="2"\; label="Perior"\; filenames="HDA0000066319320000052.png,HDA0000066319320000071.png"\; state="\{\{state\}\}">Perior</figure-callout>}}{2}+2$ The time,

$\mathrm{rxc}\_\mathrm{shift}\_\mathrm{val}=\mathrm{rxc}\_\mathrm{rxd}\_\mathrm{inval}-\frac{\mathrm{rxc}\_\mathrm{perior}}{2}-2;$

Wherein, When rxc_perior is uneven number; Its 1/2 value is got its integer part, and rxc_perior is the cycle of detected receive clock, and rxc_rxd_inval is detected receive clock and the phase relation value that receives data; Rxc_shift_val is the sample enable signal generation time, adds 2 or to subtract 2 are compensation to two-stage register sampling in the formula.

Wherein, the cycle of receive clock is: the count value of the counter of employing and high frequency clock same frequency between the rising edge of two adjacent receive clocks;

The phase relation value of receive clock and reception data is: the rising edge of adjacent receive clock is to the count value of the counter of employing between the variation edge that receives data and high frequency clock same frequency;

The time that sample enable signal produces is: during the value of the time that the sample enable signal that equals to calculate in the rolling counters forward value that adopts with the high frequency clock same frequency produces, and the output sample enable signal.

Below only be to be employed in the middle part that receives data pulse widths to calculate,, also can adopt other positions that receive data pulse widths to calculate as sampled point under the prerequisite of spirit of the present invention as sampled point.

Embodiment 3

Present embodiment provides the instantiation of interface adaptive sampling, and in the present embodiment, the enable signal that Fig. 9 has shown the interface adaptive method of sampling produces sketch map; Visible by Fig. 9, because the data of the opposite end that receives are to send according to the edge of receive clock RXC, that is to say; Receive clock RXC rising edge comes once, and data can be sent in the opposite end, just receives data RXD and can change once; Therefore, can confirm to receive the pulsewidth of data RXD according to the cycle of outside receive clock RXC.According to receive clock RXC and the phase relation that receives data RXD, can select the position of enable signal rxc_en again, promptly get the middle part that receives data RXD data pulse widths and carry out data sampling.Because data do not change before and after the sampled point, so generally be optimum data sampling point in the centre position of this data pulse widths.

According to principle shown in Figure 9, Figure 10 has shown another structured flowchart of interface adaptive sampling apparatus, and this device comprises:

The RXC cycle detection module that connects RXC rising edge extraction module; Connecting RXC rising edge extraction module and RXD changes along the phase extraction module of the RXC and the RXD of extraction module; The sampling that connects the phase extraction module of RXC cycle detection module and RXC and RXD enables output module, and connects the data sampling module that sampling enables output module.

Wherein:

Referring to Figure 11, RXC rising edge extraction module: adopt high frequency clock that RXC is carried out the sampling of two-stage register, export rxc_1d and rxc_2d respectively, again the logical AND processing is carried out in rxc_2d negate and rxc_1d signal, obtain the rising edge rxc_rise of receive clock.Wherein, clk_hi representes high frequency clock, and this high frequency clock need be 8 times on rxc clock, and is perhaps higher.Be 100M with the clk_hi frequency among the figure, the rxc frequency is that 10M is the illustration meaning.

Referring to Figure 12, RXC cycle detection module: when detecting the rxc rising edge, when promptly the rxc_rise signal is high level; Begin counting by rxc_cnt simultaneously, when detecting next rising edge of rxc, the value of preserving this counter rxc_cnt; The value of this counter rxc_cnt is the periodicity of outside input clock, and note is the cycle rxc_perior of receive clock, certainly; In the middle of reality realizes, can be after to counter rxc_cnt counting, when the rising edge of rxc; Again this counter rxc_cnt is counted, preserve the value of this counter rxc_cnt, and the value of all countings is averaged; Clk_hi representes high frequency clock signal among the figure; Rxc_cnt representes the cycle rate counter to rxc; Rxc_perior representes the period register of rxc;

Referring to Figure 13, RXD changes along extraction module: adopt high frequency clock that RXD is carried out the sampling of two-stage register, export rxd_1d and rxd_2d respectively, again rxd_2d and rxd_1d signal are carried out the XOR processing, the variation that obtains receiving data is along rxd_change.

Referring to Figure 14, the phase extraction module of RXC and RXD: when detecting the rxc_rise high level, shift_cnt begins counting, when detecting the rxd_change high level, stops counting; Preserve the value of shift_cnt when detecting the rxc_rise high level again, note is receive clock and the phase relation value rxc_rxd_inval that receives data, and shift_cnt is counted again.

At this moment,, count down to always next time that the rxd_change high level does not all appear in the rxc_rise high level if behind the rxc_rise high level, then think count this moment invalid.

Referring to Figure 15, sampling enables output module: sample enable signal is that the value according to rxc_perior and rxc_rxd_inval calculates sample enable signal generation time rxc_shift_val value.And when output clock count value rxc_cnt equaled rxc_shift_val, output sample enable signal rxc_en was used for data sampling module and samples.

Figure 15 provides the computational methods of a kind of rxc_shift_val:

This method is sampled as the optional sampling point in the middle of the pulsewidth.

When rxc_rxd_inval satisfies condition $\mathrm{Rxc}\_\mathrm{Rxd}\_\mathrm{Inval}<\frac{\mathrm{Rxc}\_\mathrm{<figure-callout\; id="2"\; label="Perior"\; filenames="HDA0000066319320000052.png,HDA0000066319320000071.png"\; state="\{\{state\}\}">Perior</figure-callout>}}{2}+2$ The time,

$\mathrm{rxc}\_\mathrm{shift}\_\mathrm{val}=\mathrm{rxc}\_\mathrm{rxd}\_\mathrm{inval}+\frac{\mathrm{rxc}\_\mathrm{perior}}{2}-2;$

When rxc_rxd_inval satisfies condition $\mathrm{Rxc}\_\mathrm{Rxd}\_\mathrm{Inval}\&GreaterEqual;\frac{\mathrm{Rxc}\_\mathrm{<figure-callout\; id="2"\; label="Perior"\; filenames="HDA0000066319320000052.png,HDA0000066319320000071.png"\; state="\{\{state\}\}">Perior</figure-callout>}}{2}+2$ The time,

$\mathrm{rxc}\_\mathrm{shift}\_\mathrm{val}=\mathrm{rxc}\_\mathrm{rxd}\_\mathrm{inval}-\frac{\mathrm{rxc}\_\mathrm{perior}}{2}-2.$

When rxc_perior was uneven number, its 1/2 value was got its integer part.For example rxc_perior is 9 o'clock, and then the rxc_perior/2 value is 4.

Wherein, add 2 or to subtract 2 are compensation to two-stage register sampling in the formula.

Shown in figure 15, for example: 2 clk_hi clock cycle gaps are arranged between rxd and the rxc, then need export sample enable signal (rxc_en) by the 5th clock after rxc_rise.

Figure 16 provides the computational methods of another kind of rxc_shift_val:

This method is located data are sampled in one of 1/3 of pulsewidth.

When rxc_rxd_inval satisfies condition $\mathrm{Rxc}\_\mathrm{Rxd}\_\mathrm{Inval}<\frac{\mathrm{Rxc}\_\mathrm{<figure-callout\; id="3"\; label="Perior"\; filenames="HDA0000066319320000072.png,HDA0000066319320000073.png"\; state="\{\{state\}\}">Perior</figure-callout>}}{3}+2$ The time,

$\mathrm{rxc}\_\mathrm{shift}\_\mathrm{val}=\mathrm{rxc}\_\mathrm{rxd}\_\mathrm{inval}+\frac{\mathrm{rxc}\_\mathrm{perior}}{3}-2;$

When rxc_rxd_inval satisfies condition $\mathrm{Rxc}\_\mathrm{Rxd}\_\mathrm{Inval}\&GreaterEqual;\frac{\mathrm{Rxc}\_\mathrm{<figure-callout\; id="3"\; label="Perior"\; filenames="HDA0000066319320000072.png,HDA0000066319320000073.png"\; state="\{\{state\}\}">Perior</figure-callout>}}{3}+2$ The time,

$\mathrm{rxc}\_\mathrm{shift}\_\mathrm{val}=\mathrm{rxc}\_\mathrm{rxd}\_\mathrm{inval}-\frac{\mathrm{rxc}\_\mathrm{perior}}{3}-2.$

Wherein, 1/3 value of rxc_perior is got its integer part.For example when rxc_perior was 10, the rxc_perior/3 value was 3; Wherein add 2 or to subtract 2 are compensation to two-stage register sampling.

Shown in figure 16, for example: 2 clk_hi clock cycle gaps are arranged between rxd and the rxc, then need export sample enable signal (rxc_en) by the 3rd clock after rxc_rise.

Certainly,, be chosen in 1/3 pulsewidth and still be the sampling of 1/2 pulsewidth place and do not do limitation,, can also 1/4 perhaps select other sampled points to sample under the prerequisite of spirit of the present invention in order to avoid data being sampled in the timing conflict zone.

Referring to Figure 17, data sampling module: data sampling module is to sample to receiving data rxd.This module specifically can adopt a d type flip flop of band Enable Pin to carry out sampling operation.For example: the input of this d type flip flop is imported high frequency clock clk_hi respectively; Receive data rxd; And sample enable signal rxc_en, come the reception data rxd of this d type flip flop is sampled the data rxd_s after the output sampling according to sample enable signal rxc_en.

Through the sampled point of adjusted time series data is to sample in the centre that receives data rxd pulsewidth, so just can guarantee front and back at sampled point in the cycle, and data can not change.Thereby can not occur owing to data are set up and the not enough sample error that occurs of retention time.

Certainly, hardware circuit of the present invention can also specifically be realized through following modes:

(1) since programmable logic device abundant logical resource and register resources are arranged, but thereby can on the journey logical device, realize;

(2) the present invention can also go up realization at application-specific integrated circuit (ASIC) (ASIC) again.

Adopt adaptively sampled mode on the interface of the present invention, guaranteed the correctness of data sampling, improved the compatibility of system interface; Owing to adopted high frequency clock that data are sampled, made things convenient for the Synchronization Design of follow-up data processing simultaneously, thereby the stability of system is provided.

From above description; Can find out that the present invention has realized following technique effect: adopt according to the phase relation between receive clock and the reception data and obtain sample enable signal, and sample according to this sample enable signal; Whether solved in the prior art judges inaccurate and problem that cause sampling and make mistakes with the edge to clock and data; Guarantee front and back at sampled point in the cycle, data can not change, and then have reached the effect of correct sampling.

Obviously, it is apparent to those skilled in the art that above-mentioned each module of the present invention or each step can realize with the general calculation device; They can concentrate on the single calculation element; Perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element; Thereby; Can they be stored in the storage device and carry out, and in some cases, can carry out step shown or that describe with the order that is different from here by calculation element; Perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.Like this, the present invention is not restricted to any specific hardware and software combination.

The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. an interface adaptive method of sampling is characterized in that, comprising:

Detect the cycle of receive clock;

Detect receive clock and the phase relation value that receives data;

According to the relation of said cycle and said phase relation value, calculating sampling enable signal generation time;

Produce sample enable signal at said sample enable signal generation time, sample to receiving data-signal according to said sample enable signal.

2. method according to claim 1 is characterized in that, the step of said calculating sampling enable signal generation time comprises:

When the phase relation value of said receive clock and said reception data during less than the sampling offset sum of the sampling time value of said receive clock and said receive clock, the sample enable signal generation time is that said phase relation value and said sampling time value sum deduct said sampling offset;

When the phase relation value of said receive clock and said reception data during more than or equal to the sampling offset sum of the sampling time value of said receive clock and said receive clock, the sample enable signal generation time is that the difference of said phase relation value and said sampling time value deducts said sampling offset.

3. method according to claim 1 is characterized in that, before the step in the cycle of said detection receive clock, also comprises:

Adopt high frequency clock that receive clock is carried out the sampling of two-stage register, export first receive clock and second receive clock respectively, the logical AND processing is carried out in the second receive clock negate and the first receive clock signal, obtain the rising edge of receive clock;

Adopt high frequency clock will receive data and carry out the sampling of two-stage register, export first respectively and receive data and second and receive data, receive data with second and carry out the XOR processing, obtain receiving the variation edge of data with the first reception data-signal.

4. method according to claim 3 is characterized in that, the step in the cycle of said detection receive clock comprises:

Detect the cycle of receive clock according to the rising edge of said receive clock.

5. method according to claim 3 is characterized in that, the step of the phase relation value between said detection receive clock and the reception data comprises:

Based on the variation of the rising edge of said receive clock and said reception data along detecting receive clock and receiving the phase relation value between the data.

6. an interface adaptive sampling apparatus is characterized in that, comprising:

First detecting unit is used to detect cycle of receive clock;

Second detecting unit is used to detect receive clock and the phase relation value that receives data;

Computing unit is used for the relation according to said cycle and said phase relation value, calculating sampling enable signal generation time;

Sampling unit is used for producing sample enable signal at said sample enable signal generation time, samples to receiving data-signal according to said sample enable signal.

7. device according to claim 6 is characterized in that, said computing unit is calculating sampling enable signal generation time in the following manner:

When the phase relation value of said receive clock and said reception data during less than the sampling offset sum of the sampling time value of said receive clock and said receive clock, the sample enable signal generation time is that said phase relation value and said sampling time value sum deduct said sampling offset;

When the phase relation value of said receive clock and said reception data during more than or equal to the sampling offset sum of the sampling time value of said receive clock and said receive clock, the sample enable signal generation time is that the difference of said phase relation value and said sampling time value deducts said sampling offset.

8. device according to claim 6 is characterized in that, also comprises:

Processing unit; Be used to adopt high frequency clock that receive clock is carried out the sampling of two-stage register; Export first receive clock and second receive clock respectively, the logical AND processing is carried out in the second receive clock negate and the first receive clock signal, obtain the rising edge of receive clock; And adopt high frequency clock will receive data and carry out the sampling of two-stage register, export first respectively and receive data and second and receive data, receive data with second and carry out the XOR processing with the first reception data-signal, obtain receiving the variation edge of data.

9. device according to claim 8 is characterized in that, said first detecting unit specifically is used for detecting according to the rising edge of said receive clock the cycle of receive clock.

10. device according to claim 8 is characterized in that, said second detecting unit specifically is used for according to the variation of the rising edge of said receive clock and said reception data along detecting receive clock and receiving the phase relation value between the data.

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