CN102651685B

CN102651685B - Signal delay device and method

Info

Publication number: CN102651685B
Application number: CN201110048137.0A
Authority: CN
Inventors: 李文佳; 高同海; 文敢
Original assignee: Ericsson China Communications Co Ltd
Current assignee: Ericsson China Communications Co Ltd
Priority date: 2011-02-24
Filing date: 2011-02-24
Publication date: 2016-07-27
Anticipated expiration: 2031-02-24
Also published as: CN102651685A

Abstract

Disclose a kind of signal delay device and method, signal delay device can by input signal delay scheduled time slot, including: the first synchronous circuit, it is thus achieved that the input signal after reference clock synchronization, as the first synchronizing signal being delayed by for the first period relative to input signal；Counting circuit, it is determined that the first period, and second and the 3rd period is calculated according to scheduled time slot and the first period；First delay circuit, by the first second period of sync signal delay, and exports the first delay signal；And second delay circuit, postpone signal delay the 3rd period by first, it is thus achieved that input signal is delayed the signal after scheduled time slot.Postpone the bigger delay circuit based on the clock cycle of yardstick according to the present invention it is possible to combine and postpone the advantage of the less delay chain of yardstick, reaching precision and relatively low realize cost higher time delay simultaneously.Additionally propose the correction to local reference clock in deferring procedure, further increase precision.

Description

Signal delay device and method

Technical field

The present invention relates to communication technical field, be specifically related to signal delay device and method.

Background technology

In communication applications, in order to realize signal synchronization or time alignment, it usually needs signal is postponed.For the communication system based on time division multiple acess (TDMA), TDMA is precise synchronization system, and for this system, China Mobile develops the precise synchronization interface being called 1PPS+TOD interface.But, 1PPS+TOD interface specification is not the unified interface specification for all synchro systems.In order to other interfaces (such as GPS, the broadsync interface developed specially by Broadcom company) compatible, interface protocol conversion must be carried out, and interface conversion can bring the time caused due to conversion processing time to wait, this causes in some cases, 1PPS pulse is not directed at the time point of integer second, now should be postponed by 1PPS, so that 1PPS is directed at integer second time point.TOD information can carry time migration, for instance, if TOD value is 2.05s, i.e. the rising edge of 1PPS is at 2.05s, it should 1PPS is deferred to 3.00s.

Have been proposed for the certain methods that 1PPS signal is postponed.A kind of method is based on local clock cycles to re-create 1PPS signal, i.e. counted postponing duration by local or reference clock, to postpone original 1PPS signal, obtains the 1PPS signal postponed.This Method And Principle is simple, and time delay, yardstick can be relatively big, but time delay, precision was inadequate, generally can exist ± error of a clock cycle, because time precision depends entirely on frequency accuracy and the stability of local reference clock in this case.Another kind of method is to adopt programmable delay chain, and 1PPS signal is passed through delay chain, and the length of delay of this delay chain can be subject to the control of the control word from TOD information acquisition simultaneously, thus realizing required delay.Owing to delay units delay value each in delay chain can be about 150ps, higher precision time delay therefore can be realized.Now, delay resolution is limited by the propagation delay of delay cell, and time delay, yardstick was less.But, if required time delay is longer, then need substantial amounts of delay cell cascade, along with cascaded stages number increases, time delay, error can be accumulated, and causes the circuit structure of complexity and bigger delay error.

Accordingly, it would be desirable to a kind of signal delay technology, it is possible to avoid now methodical deficiency, it is achieved the high accuracy of signal is postponed.

Summary of the invention

According to embodiments of the present invention, it is proposed that a kind of signal delay device, it is possible to inputting signal delay scheduled time slot, this signal delay device includes:

First synchronous circuit, utilizes reference clock signal that input signal is synchronized, and exports the input signal after synchronization, and as the first synchronizing signal, described first synchronizing signal was delayed by for the first period relative to input signal；

Counting circuit, it is determined that the first period, and calculate second and the 3rd period according to scheduled time slot and the first period, wherein, the first period, the second period with the 3rd period sum equal to scheduled time slot；

First delay circuit, by the first second period of sync signal delay, and exports the first synchronizing signal after delay, postpones signal as first；And

Second delay circuit, postpones signal delay the 3rd period by first, it is thus achieved that second postpones signal, as inputting the signal after signal delays scheduled time slot.

According to embodiments of the present invention, signal delay device also includes:

Correcting circuit, utilizes input signal that the cycle of reference clock signal is corrected, and the cycle after output calibration, as calibration cycle；

Wherein, counting circuit receives the calibration cycle from correcting circuit output, and utilizes described calibration cycle in the calculation.

According to embodiments of the present invention, it is proposed that a kind of signal delay method, it is possible to inputting signal delay scheduled time slot, this signal delay method comprises the steps:

A. utilizing reference clock signal that input signal is synchronized, and export the input signal after synchronization as the first synchronizing signal, described first synchronizing signal was delayed by for the first period relative to input signal；

B. determining for the first period, and calculate the second period and the 3rd period according to scheduled time slot and the first period, wherein, the first period, the second period are equal to scheduled time slot with the 3rd period sum；

C. by the first second period of sync signal delay, and export the first synchronizing signal after delay, postpone signal as first；And

D. signal delay the 3rd period is postponed by first, it is thus achieved that second postpones signal, as inputting the signal after signal delays scheduled time slot.

Accompanying drawing explanation

By the preferred embodiments of the present invention being described below in conjunction with accompanying drawing, the above-mentioned of the present invention and other objects, features and advantages will be made clearly, wherein:

Fig. 1 is the schematic block diagram of signal delay device according to embodiments of the present invention；

Fig. 2 is the schematic block diagram of the first synchronous circuit in signal delay device shown in Fig. 1；

Fig. 3 is the schematic block diagram of the counting circuit in signal delay device shown in Fig. 1；

Fig. 4 is the schematic block diagram of signal delay device according to another embodiment of the present invention；

Fig. 5 is the schematic block diagram of the correcting circuit in signal delay device shown in Fig. 4；

Fig. 6 is the schematic diagram of 1PPS+TOD time interface signal；

Fig. 7 is the principle schematic that 1PPS signal delay is described；

Fig. 8 is the concrete exemplary block diagram of signal delay device according to embodiments of the present invention；

Fig. 9 be the embodiment of the present invention signal delay device in adopt bilateral along time-to-digital conversion circuit；

Figure 10 is the programmable delay chain adopted in the signal delay device of the embodiment of the present invention；

Figure 11 is the principle schematic illustrating to adopt 1PPS signal that reference clock is corrected；

Figure 12 is the concrete exemplary block diagram of correction unit according to embodiments of the present invention；

Figure 13 is the exemplary block diagram of Syn_Start circuit in correction unit shown in Figure 11；

Figure 14 a and 14b respectively illustrates the oscillogram of each coherent signal when adopting the trailing edge of reference clock signal and rising edge that 1PPS signal is sampled；

Figure 15 is the exemplary block diagram of Syn_End circuit in correction unit shown in Figure 12；

Figure 16 a-16d respectively illustrates the oscillogram of each coherent signal in the four kinds of situations adopting the trailing edge of reference clock signal and rising edge 1PPS_Start and 1PPS_End signal to be sampled and obtains；

Figure 17 is the schematic flow diagram of signal delay method according to embodiments of the present invention；And

Figure 18 is the schematic flow diagram carrying out reference clock correction according to another embodiment of the present invention in signal delay method.

Detailed description of the invention

Inventor have noticed that can by based on local clock cycles signal delay and adopt delay chain signal delay combine, by signal delay scheduled time slot.Such as, the given predetermined delay period is Time_Delay, after utilizing local clock pulses that the signal to postpone is synchronized, the delay period synchronizing to cause is Time_Syn, then may determine that in Duration1=Time_Delay-Time_Syn and comprise how many local clock cycles.Thus, it is possible to the signal delay technology based on local clock cycles bigger initially with postponing yardstick, by signal delay integer cycle T, for instance N number of cycle, N is greater than being equal to the integer of 1.Then, difference according to Duration1 and N*T is (generally speaking, shorter than a reference clock cycle), adopt and postpone the delay chain that yardstick is less, signal after postponing is postponed Duration2=Duration1-N*T again, thus, through synchronizing and two-stage delay, it becomes possible to obtain required delay signal.As such, it is possible to reach precision and relatively low realize cost higher time delay, it is to avoid the error an of ± clock cycle, and avoid the error that delay cell cascade too much in delay chain brings.

Additionally, inventor have noticed that when the signal to postpone is precision frequency signal as contour in 1PPS+TOD interface, it is possible to adopt this signal that local clock carries out frequency or cycle correction, and use the local clock cycles of correction during signal delay.Such that make local clock not have accurate frequency or cycle, it is possible to use this high accuracy frequency signal corrects local clock cycles.Thus, utilizing local clock as reference clock in typical case, it is to avoid time precision depends entirely on frequency accuracy and this drawback of stability of local clock, further increases precision time delay.

It is explained above the basic thought of the present invention.Referring to accompanying drawing, the example embodiment of the present invention is described in detail, the invention is not restricted to following example embodiment.In order to know the basic thought describing the present invention, accompanying drawing illustrate only and the closely-related parts of technical scheme, function or step, and eliminate the specific descriptions to known technology, function, parts or step in being described below.

In the following description, first the signal of signal delay device according to embodiments of the present invention is constituted and illustrate, then for 1PPS+TOD interface, the concrete exemplary construction of signal delay device is described.But, the embodiment of the present invention is not limited to this concrete example, but as required, can be applied to delay and the time alignment of multi-signal.

Additionally, the schematic block diagram in accompanying drawing there is shown the element relevant with the embodiment of the present invention, structure and annexation with circuit structure, eliminate element well known to those skilled in the art, structure and annexation, to clearly show that the embodiment of the present invention.

Fig. 1 is the schematic block diagram of signal delay device according to embodiments of the present invention, and input signal In_Sig can be postponed scheduled time slot Delay by this signal delay device.As it is shown in figure 1, this signal delay device includes the first synchronous circuit 10, counting circuit the 12, first delay circuit 14 and the second delay circuit 16.

First synchronous circuit 10 utilizes reference clock signal Ref_Clk that input signal In_Sig is synchronized, and exports the input signal after synchronization, as the first synchronizing signal Syn_Sig1.Such as, the first synchronizing signal 10 can utilize the rising edge of reference clock signal Ref_Clk or trailing edge that input signal In_Sig is synchronized, and thus obtains the signal Tong Bu with the rising edge of reference clock signal Ref_Clk or trailing edge.Depending on the first synchronous circuit 10, the first synchronizing signal Syn_Sig1 is delayed by the first period T0 relative to input signal In_sig.So, the first synchronous circuit 10 can be any applicable synchronous circuit well known to those skilled in the art.

The first synchronizing signal Syn_Sig1 delay relative to input signal In_Sig determined by counting circuit 12, i.e. the first period T0, and calculates the second period T1 and the three period T2 according to scheduled time slot Delay and the first period T0.Here, the first period, the second period are equal to scheduled time slot with the 3rd period sum, i.e. Delay=T0+T1+T2.According to embodiments of the present invention, counting circuit 12 can adopt any applicable time-to-digital conversion circuit (TDC) well known to those skilled in the art to determine the first period T0.

The second period T1 that first delay circuit 14 calculates according to counting circuit 12, postpones the first synchronizing signal Syn_Sig1 the second period T1, and exports the first synchronizing signal after delay, postpones signal Dly_Sig1 as first.The 3rd period T2 that second delay circuit 16 calculates according to counting circuit 12, postpones signal Dly_Sig1 by first and postpones the 3rd period T2, it is thus achieved that second postpones signal Dly_Sig2, thus input signal In_Sig is delayed scheduled time slot Delay.

According to embodiments of the present invention, the first delay circuit 14 can be based on the delay circuit of reference clock cycle.In embodiments of the present invention, can be any applicable delay circuit well known to those skilled in the art based on the delay circuit of clock cycle.Such as, the second period T1 can be the integral multiple of the cycle T of such as reference clock signal, for instance T1=CNT*T, CNT are greater than being equal to the integer of 1.First delay circuit 14 utilizes enumerator, count with reference clock cycle T for interval, when reaching CNT, and the just T1 by signal delay.

According to embodiments of the present invention, the second delay circuit 16 can be delay chain, for instance be programmable delay chain.In embodiments of the present invention, delay chain can be any applicable delay chain well known to those skilled in the art.According to the 3rd period T2, delay chain is programmed, so that the signal after the first delay circuit 14 postpones is postponed T2 further.

According to embodiments of the present invention, based on formula Delay=T0+T1+T2, by first synchronous circuit the 10, first delay circuit 14 and second this path of delay circuit 16, input signal In_Sig can be postponed required scheduled time slot Delay by signal delay device.First delay circuit 14 and the second delay circuit 16 are needed the period postponed to be calculated by counting circuit 12, and distribute to corresponding delay circuit.Such as, when utilizing the delay circuit based on the clock cycle and delay chain, it is possible to calculate the duration of integer the clock cycle comprised in Delay-T0, the duration of the part less than a clock cycle is then calculated.So, the delay circuit based on the clock cycle that delay yardstick is relatively big, precision is relatively low is first by signal delay integer the clock cycle.Then, for the remaining part less than a clock cycle, adopt the delay delay chain that yardstick is less, precision is higher to be postponed again by signal after delay.As such, it is possible to reach precision and relatively low realize cost higher time delay simultaneously, it is to avoid the error an of ± clock cycle, and avoid the error that delay cell cascade too much in delay chain brings.

Traditional synchronous circuit never solves metastable problem well, and metastable state can cause the randomness of output synchronized result, so the accuracy of synchronized result will reduce.This is also one of circuit measuring and the not high reason of synchronization accuracy.As well known to the skilled person, in synchronous circuit, input signal is as data, reference clock signal is as clock, only when the requirement of the foundation (setup) of the trigger used by both sides relation meets synchronized sampling and maintenance (hold) time, just can ensure that and metastable issues will not occur when the rising edge utilizing reference clock signal or trailing edge synchronize.But, generally it is difficult to meet this requirement, this is because input signal and reference clock signal frequency are generally inconsistent, and reference clock is usually local clock, with the input signal of externally input without any phase information.If input time of arrival (toa) point in the metastable state window of the trigger used by sampling and synchronization, then can cause sampling uncertainty, this uncertainty is likely to frequency of injury certainty of measurement.

In order to avoid the problems referred to above, it is proposed that the first synchronous circuit 10 according to embodiments of the present invention, it adopts synchronous regime detection and the bilateral uncertainty avoiding metastable state to cause along sampling.Fig. 2 illustrates the schematic block diagram of the first synchronous circuit 10 according to embodiments of the present invention, and the first synchronous circuit 10 includes the first synchronous regime testing circuit 20 and the first synchronizing signal obtains circuit 22.First synchronous regime testing circuit 20 adopts input signal In_Sig that the reference clock signal Ref_Clk through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and obtains indicating the rising edge that should use reference clock or trailing edge to carry out the first synchronous indicating signal Syn_Sel1 synchronized.First synchronizing signal obtains circuit 22 and utilizes the rising edge of reference clock signal Ref_Clk and trailing edge that input signal In_Sig is synchronized, and when the first synchronous indicating signal Syn_Sel1 indicates the rising edge of reference clock signal Ref_Clk, select the input signal after being synchronized by the rising edge of reference clock signal Ref_Clk, as the first synchronizing signal Syn_Sig1, and when the first synchronous indicating signal indicates the trailing edge of reference clock signal Ref_Clk, select the input signal after being synchronized by the trailing edge of reference clock signal, as the first synchronizing signal Syn_Sig1.In other words, according to embodiments of the present invention, first synchronous circuit 10 uses input signal In_Sig to sample through the reference clock of predetermined phase shift (such as, 90 degree), to determine the relation between the input signal In_Sig time of advent and the edge of reference clock signal Ref_Clk.First synchronous circuit 10 uses 180 degree of inversion clocks of Ref_Clk and Ref_Clk to carry out sampled input signal In_Sig simultaneously, and according to determined edge relation, selects the rising edge of reference clock signal or the signal of trailing edge synchronization.Such that just rising edge finds that sampling there occurs metastable state, it is possible to use the result of trailing edge sampling, vice versa.After a while will with reference to concrete example, the exemplary circuit structure of detailed description the first synchronous circuit 10 according to embodiments of the present invention.

Synchronous regime detection is adopted and bilateral along sampling corresponding to the first synchronous circuit 10, counting circuit 12 is also adopted by bilateral along time-to-digital conversion circuit (TDC) when determining the first period T0, thus avoiding metastable issues in trigger sampling process further.As shown in Figure 3, it is shown that the schematic block diagram of the counting circuit 12 in signal delay device shown in Fig. 1.Counting circuit 12 includes first, second, and third period counting circuit 30,32 and 34.As mentioned above, first period counting circuit 30 adopts bilateral along time figure switch technology, determine rising edge and the trailing edge delay relative to input signal In_Sig of reference clock signal Ref_Clk, and according to the first synchronous indicating signal Syn_Sel1, select the rising edge of reference clock signal Ref_Clk or the trailing edge delay In_Sig relative to input signal as the first period T0.Specifically, when the first synchronous indicating signal Syn_Sel1 instruction uses the rising edge of reference clock signal Ref_Clk to synchronize, indicating the first synchronizing signal Syn_Sig1 is that the rising edge using reference clock signal Ref_Clk synchronizes, thus the first period counting circuit 30 selects the delay relative to input signal In_Sig of the rising edge of reference clock signal Ref_Clk as the first period T0.When the first synchronous indicating signal Syn_Sel1 instruction uses the trailing edge of reference clock signal Ref_Clk to synchronize, indicating the first synchronizing signal Syn_Sig1 is that the trailing edge using reference clock signal Ref_Clk synchronizes, thus the first period counting circuit 30 selects the delay relative to input signal In_Sig of the trailing edge of reference clock signal Ref_Clk as the first period T0.Second period counting circuit 32, receives the first period T0, the second period T1 calculated as below:

T1=FLOOR ((Delay-T0)/T) * T, (1)

Wherein, FLOOR is downward rounding operation symbol.

3rd period counting circuit 34 receives the first period T0 and the second period T1, the 3rd period T2 calculated as below:

T2=Delay-(T0+T1).(2)

Second and the 3rd period counting circuit 32,34 any applicable computing circuit well known to those skilled in the art or counting circuit can be adopted to realize.After a while will with reference to concrete example, the exemplary circuit structure of detailed description counting circuit 12 according to embodiments of the present invention.

Fig. 4 is the schematic block diagram of signal delay device according to another embodiment of the present invention.Compared to signal delay device shown in Fig. 1, the signal delay device of Fig. 4 also includes correcting circuit 40, utilizes input signal In_Sig that the cycle T of reference clock signal Ref_Clk is corrected, and the cycle after output calibration, as calibration cycle T_real.Shown in counting circuit 42 and Fig. 1, the counting circuit 12 of signal delay device is different in that, receives the calibration cycle T_real from correcting circuit 42 output, and utilizes this calibration cycle T_real in the calculation.Specifically, the second period counting circuit of counting circuit 42 second period T1 ' calculated as below:

T1 '=FLOOR ((Delay-T0)/T_real) * T_real, (3)

Wherein, FLOOR is downward rounding operation symbol.

3rd period counting circuit the 3rd period T2 ' calculated as below:

T2 '=Delay-(T0+T1 ').(4)

Other circuit parts of the signal delay device of Fig. 4 are essentially identical with the related circuit part of signal delay device shown in Fig. 1, omit detailed description at this.

Embodiment illustrated in fig. 4 is mainly in view of the frequency to local reference clock or the correction of circular error, to improve precision time delay further.As it has been described above, when the signal to postpone is precision frequency signal as contour in 1PPS+TOD interface, it is possible to adopt this signal that local reference clock carries out frequency or cycle correction, and during signal delay, use the reference clock cycle of correction.Such that make local reference clock not have accurate frequency or cycle, it is possible to use this high accuracy frequency signal carrys out fair copy ground reference clock cycle.Thus, it is to avoid time precision depends entirely on frequency accuracy and stability this drawback of local reference clock, further increases precision time delay.

Such as, for 1PPS+TOD interface signal, according to 1PPS+TOD timing specification, in signal, the timing value of TOD field indicates the precise time of the rising edge of 1PPS.Difference (being labeled as Delta_TOD) between two adjacent TOD indicates the precise time between two adjacent rising edges of 1PPS, as shown in figure 11.Use reference clock to 1PPS signal sampling, and start enumerator when sampling the rising edge of 1PPS, and stop enumerator when sampling the rising edge of next 1PPS.When sampling process terminates, obtaining the value of CNT*T, CNT represents count value.The time delay T3 considering to utilize reference clock signal Ref_Clk that the rising edge of 1PPS signal is sampled and cause and the time delay T4 next rising edge of 1PPS signal being sampled and causing, according to Delta_TOD=CNT*T+T3-T4, it is possible to obtain calibration cycle T_real=(Delta_TOD-T3+T4)/CNT.Thus, deferring procedure is based on actual measured value T_real, rather than the value of labelling, thus not only correcting frequency shift, also eliminates frequency in time or the frequency shift (FS) that causes of the change of temperature.

Fig. 5 illustrates the schematic block diagram of the correcting circuit 40 in signal delay device shown in Fig. 4.Correcting circuit 40 includes: the second synchronous circuit 50, utilizes reference clock signal Ref_Clk that input signal In_Sig is synchronized, and exports the input signal after synchronization, as the second synchronizing signal Syn_Sig2；3rd synchronous circuit 52, utilize reference clock signal Ref_Clk to input signal In_Sig2 to second to synchronize, and export the second input signal after synchronization, as the 3rd synchronizing signal Syn_Sig3, second input signal In_Sig2 is the signal after input signal In_Sig carries out predetermined delay (such as, Delta_TOD)；4th period counting circuit 54, calculates the second synchronizing signal Syn_Sig2 delay relative to input signal In_Sig as the 4th period T3；5th period counting circuit 56, calculates the 3rd synchronizing signal Syn_Sig3 and inputs the delay of signal In_Sig2 relative to second, as the 5th period T4；Number of cycles obtains circuit 58, in response to the second synchronizing signal Syn_Sig2, start in units of the cycle T of reference clock signal Ref_Clk, enumerator is utilized to count, and in response to the 3rd synchronizing signal Syn_Sig3, stop the counting of enumerator the count value CNT that output counter obtains, as number of cycles；And calibration cycle counting circuit 59, utilize the second input signal In_Sig2 relative to the input predetermined delay of signal In_Sig, the 4th and the five or six period T3, T4 and number of cycles CNT, calculate calibration cycle T_real.

According to embodiments of the present invention, the second input signal In_Sig2 is the signal after input signal In_Sig carries out predetermined delay.For obtaining the second input signal In_Sig2, it is possible to adopt the knife switch circuit of 1 turn 2, on-off circuit will be sent at input signal In_Sig2.At current time, the output of this switch is to the second synchronous circuit 50, and in the next clock cycle, the output of switch, to the 3rd synchronous circuit 52, resulting in tandem pulse.The control of this on-off circuit can be realized by logic well known to those skilled in the art.

According to embodiments of the present invention, second can be identical with the first synchronous circuit 10 with the 3rd synchronous circuit 50,52, and the 4th can be identical with the first period counting circuit 30 with the 5th period counting circuit 54,56.This way it is possible to avoid the metastable issues in trigger sampling process.But, bilateral along sampling and bilateral along time figure switch technology owing to have employed, the 4th and the 5th period T3, T4 that the 4th and the 5th period counting circuit 54,56 is determined respectively would be likely to occur following situation: 1) input signal In_Sig and the second input signal In_Sig2 is all that the rising edge adopting reference clock signal Ref_Clk synchronizes；2) input signal In_Sig and the second input signal In_Sig2 is all that the trailing edge adopting reference clock signal Ref_Clk synchronizes；3) input signal In_Sig is that the rising edge adopting reference clock signal Ref_Clk synchronizes, and the second input signal In_Sig2 is that the trailing edge adopting reference clock signal Ref_Clk synchronizes；4) input signal In_Sig is that the trailing edge adopting reference clock signal Ref_Clk synchronizes, and the second input signal In_Sig2 is that the rising edge adopting reference clock signal Ref_Clk synchronizes.Thus, compared to situation 1) and 2), in situation 3) and 4) under, also differ further half clock cycle between T3 and T4.Specifically, in situation 3) under, Delta_TOD=CNT*T+T3-T4+T/2, in situation 4) under, Delta_TOD=CNT*T+T3-T4-T/2.

Therefore, according to embodiments of the present invention, the calculating of calibration cycle T_real includes three kinds of situations:

In above-mentioned situation 1) and 2) under,

T_real=(Delta_TOD-T3+T4)/CNT, (5)

In above-mentioned situation 3) under,

T_real=(Delta_TOD-T3+T4)/(CNT+0.5), (6)

In above-mentioned situation 4) under,

T_real=(Delta_TOD-T3+T4)/(CNT-0.5), (7)

After a while will with reference to concrete example, the exemplary circuit structure of detailed description correcting circuit 12 according to embodiments of the present invention.

Above the signal delay device of the embodiment of the present invention of Fig. 1 and Fig. 4 is carried out the description in principle.Below using 1PPS+TOD time interface signal as input signal, specifically describe the exemplary circuit configuration of signal delay device according to embodiments of the present invention.But, the embodiment of the present invention is not limited to this example, but can as required and application, for existing and any applicable signal in the future are postponed.Additionally, the detailed description that eliminate well known to those skilled in the art function, element etc. is described below, with the correlated characteristic of the prominent embodiment of the present invention.

Fig. 6 is the schematic diagram of 1PPS+TOD time interface signal.According to existing specification, 1PPS+TOD time interface signal includes two kinds of signals: 1PPS signal and serial data signal.As it can be seen, 1 pulse per second of 1PPS signal, and the rising edge of 1PPS signal is used as clock edge and drives output serial data, and the rise time of this clock should less than 50ns, and pulse width should be 20ms～200ms.Serial data signal carries TOD (time in one day) message.TOD message is with an initial bits (high effectively), a stopping bit (low effectively) and 8 data bit transfer.Default transmission baud rate is 9600bps.TOD message should be transmitted by 1ms after the rising edge of 1PPS again, and should starting to complete in 500ms transmission from the rising edge of 1PPS.The time of the rising edge the latest of the persond eixis carried by TOD 1PPS.

Being as noted previously, as and must carry out interface protocol conversion, interface conversion can bring the time caused due to conversion processing time to wait, this causes in some cases, 1PPS pulse is not directed at the time point of integer second, now should be postponed by 1PPS, so that 1PPS is directed at integer second time point.TOD information can carry time migration, for instance, if TOD value is 2.05s, i.e. the rising edge of 1PPS is at 2.05s, it should 1PPS is deferred to 3.00s.Fig. 7 illustrates the principle schematic of 1PPS signal delay.As it can be seen, Ref_ClK is local reference clock, for the time cycle is counted.Original_1PPS is original 1PPS signal, does not align with the integer second.According to TOD value, it is possible to obtain by the length of delay of Delay labelling.Delay is divided into 3 parts: T0, T1=CNT*T, T2.

According to embodiments of the present invention, by synchronous circuit, signal Original_1PPS being synchronized, the time delay synchronizing to cause is T0.Then adopt the delay circuit based on reference clock cycle that the signal Syn after synchronizing is postponed CNT clock cycle, i.e. T1, obtain Temp_1PPS.Finally, adopt programmable delay chain, Temp_1PPS is postponed T2 again, thus obtains 1PPS_Delay.

Fig. 8 illustrates the concrete exemplary circuit structure of signal delay device according to embodiments of the present invention, in conjunction with Fig. 1-3, it can be seen that the first synchronous regime testing circuit 20 is embodied as phase shifter Shift_90 and the first Parasites Fauna on the right side of it.Phase shifter Shift_90 receives reference clock signal Ref_Clk and by its phase shift 90 degree.First Parasites Fauna includes first, second, and third depositor of series connection, the clock input input signal 1PPS of the first depositor, data input pin receives from the reference clock signal Ref_Clk_90 after the phase shift of phase shifter, and outfan is connected to the data input pin of the second depositor.The reference clock signal Ref_Clk_180 that the clock input of the second depositor is anti-phase, outfan is connected to the data input pin of the 3rd depositor, the clock input reference clock signal Ref_Clk of the 3rd depositor, outfan exports the first synchronous indicating signal Clk_Sel.First synchronizing signal obtains circuit 22 and is embodied as bilateral along register circuit with MUX.Bilateral second and the 3rd Parasites Fauna including parallel connection along register circuit, second Parasites Fauna includes the 4th and the 5th depositor of series connection, wherein, the input end of clock of the 4th and the 5th depositor all receives reference clock signal Ref_Clk, the data input pin of the 4th depositor receives input signal 1PPS, outfan is connected to the data input pin of the 5th depositor, one of outfan selection input being connected to MUX of the 5th depositor.3rd Parasites Fauna includes the 6th and the 7th depositor of series connection, wherein, the reference clock signal Ref_Clk_180 that the clock input of the 6th depositor is anti-phase, the data input pin of the 6th depositor receives input signal 1PPS, outfan is connected to the data input pin of the 7th depositor, the clock input reference clock signal Ref_Clk of the 7th depositor, outfan is connected to another selection input of MUX.The first synchronous indicating signal Clk_Sel selecting to control termination receipts from the first synchronous regime testing circuit 20 of MUX, outfan exports the first synchronizing signal Syn.Later with reference to the identical synchronous circuit used in correcting circuit, the work process of synchronous circuit is described in detail.

First period counting circuit 30 is embodied as bilateral along time-to-digital conversion circuit with MUX MUX, bilateral along time-to-digital conversion circuit reception reference clock signal Ref_Clk and input signal 1PPS, and export bilateral two kind of first period T0_0 and the T0_180 determined after the sampling data input section to MUX.The first synchronous indicating signal Clk_Sel selecting to control termination receipts from the first synchronous regime testing circuit 20 of MUX MUX, outfan output is according to Clk_Sel the first period T0 selected.Specifically, the time difference of the T0_0 instruction rising edge from the rising edge of 1PPS to Ref_Clk, the time difference of the T0_180 instruction trailing edge from the rising edge of 1PPS to Ref_Clk.Select one of two time values as T0 according to Clk_Sel.

Fig. 9 illustrates the bilateral exemplary circuit structure along time-to-digital conversion circuit in Fig. 8.As it can be seen, the bilateral delay chain including the first and second Parasites Fauna and centre along time-to-digital conversion circuit.Each group of n the depositor including parallel connection in first Parasites Fauna and the second Parasites Fauna, delay chain includes n-1 delay cell of series connection, and n is greater than being equal to the integer of 1.N can be arranged according to application demand.One of outfan selection input being connected to MUX of each depositor in first Parasites Fauna and the second Parasites Fauna, the clock input reference clock signal Ref_Clk of first depositor in first Parasites Fauna, data input pin receives input signal 1PPS, the reference clock signal Ref_Clk_180 that in second Parasites Fauna, the clock input of first depositor is anti-phase, data input pin receives input signal 1PPS, and the input of first delay cell of delay chain receives input signal 1PPS.In each group of first Parasites Fauna and the second Parasites Fauna, the data input pin of m-th depositor is connected to the outfan of m-1 delay cell of delay chain, and m is the integer more than 1 and less than or equal to n.The selecting of MUX controls termination and receives from the first synchronous indicating signal Clk_Sel of the first synchronous circuit, and outfan is connected to computing engines (second and the 3rd period counting circuit be embodied as computing engines).With reference to Fig. 9 bilateral, along TDC circuit, 1PPS signal propagates through delay chain, utilizes the first and second Parasites Fauna simultaneously, and 1PPS is sampled by trailing edge and rising edge at local reference clock.Select the output of a Parasites Fauna as output result according to the first synchronous indicating signal Clk_Sel, MUX.Such as, if delay chain has 8 delay cells, the length of delay of each delay cell is Dps, then when output register first time upset, output group depositor is 11110000.This represents that the time value that TDC circuit obtains is 5*Dps, i.e. T0=5*Dps.

Second and the 3rd period counting circuit be embodied as computing engines, computing engines is used for utilizing above-mentioned formula (1) and (2) to calculate T1 and T2, and the delay circuit based on reference clock cycle and programmable delay chain are given in output respectively.Can employ counters to realize based on the delay circuit (that is, the first delay circuit 14) of reference clock cycle, count for interval with reference clock cycle T, the T1 by signal delay, obtain Temp_1PPS.

Figure 10 illustrates the exemplary circuit structure of programmable delay chain in Fig. 8, including delay chain and MUX MUX.Obtain postponing control word according to T2, and delay control word is supplied to the selection input of MUX MUX.In delay chain, the output of each delay cell of series connection is connected to the data input pin of MUX MUX.Signal Temp_1PPS propagates through delay chain, and selects according to postponing control word, the signal 1PPS_Delay after being postponed.

Exemplary circuit structure referring to Figure 11-16 couples correcting circuit 40 according to embodiments of the present invention is described.

Figure 11 is the principle schematic illustrating to adopt 1PPS signal that reference clock is corrected.As it has been described above, according to 1PPS+TOD timing specification, in signal, the timing value of TOD field indicates the precise time of the rising edge of 1PPS.Difference Delta_TOD between two adjacent TOD indicates the precise time between two adjacent rising edges of 1PPS, Delta_TOD=TOD1-TOD2.Therefore, use reference clock Ref_Clk to 1PPS signal sampling, and start enumerator when sampling the rising edge of 1PPS, and stop enumerator when sampling the rising edge of next 1PPS.When sampling process terminates, obtaining the value of CNT*T, CNT represents count value.In the ordinary course of things, the time delay T3 considering to utilize reference clock signal Ref_Clk that the rising edge of 1PPS signal is sampled and cause and the time delay T4 next rising edge of 1PPS signal being sampled and causing, obtains Delta_TOD=CNT*T+T3-T4.But, according to embodiments of the present invention, bilateral along simultaneous techniques owing to have employed, also it is likely to half clock cycle of difference further between T3 and T4.To this, will be described in detail in conjunction with particular circuit configurations and oscillogram after a while.

Figure 12 illustrates the exemplary circuit structure chart of correction unit 40 according to embodiments of the present invention, and wherein Sync_Start, Sync_End, TDC1 and TDC2 correspond respectively to the second synchronous circuit the 50, the 3rd synchronous circuit the 52, the 4th period counting circuit 54 and the 5th period counting circuit 56.Enumerator Count and depositor below constitute number of cycles and obtain circuit 58, and calibration cycle computing engines constitutes calibration cycle counting circuit 59.Additionally, 1PPS_Start and 1PPS_End corresponds respectively to input signal In_Sig and the second input signal In_Sig2.

Signal 1PPS_Start and Ref_Clk input circuit Sync_Start, after double; two edge synchronization, output synchronizing signal Cnt_enable and indicate the rising edge with reference clock or trailing edge carries out the synchronous indicating signal Start_sel that synchronizes, wherein, Cnt_enable is also represented by sampling the rising edge of 1PPS_Start, it is possible to carry out counting.In response to this signal Cnt_enable, enumerator Count starts counting up, and its count value is input to depositor.TDC1 receives signal 1PPS_Start and Ref_Clk, carries out bilateral along time figure conversion for signal 1PPS_Start.The 26S Proteasome Structure and Function of TDC1 is same as shown in Figure 9, is not described in detail at this.Two output T3_180 and T3_0 of TDC1 are input to the data input pin of MUX, and the selection input of MUX receives synchronous indicating signal Start_sel, select one of T3_180 and T3_0 as T3 accordingly.

Figure 13 illustrates the exemplary circuit structure of Syn_Start circuit in correction unit shown in Figure 11, the oscillogram of each coherent signal when Figure 14 a and 14b respectively illustrates the trailing edge adopting reference clock signal and 1PPS signal is sampled by rising edge.

As shown in figure 13, the structure of Syn_Start circuit is identical with the above-mentioned structure with reference to the synchronous circuit described in Fig. 8.Phase shifter Shift_90 and the first Parasites Fauna Reg_E, Reg_F and Reg_G on the right side of it constitute synchronous regime testing circuit.Phase shifter Shift_90 receives reference clock signal Ref_Clk and by its phase shift 90 degree.First Parasites Fauna includes first, second, and third depositor Reg_E, Reg_F and the Reg_G of series connection, the clock input input signal 1PPS_Start of the first depositor Reg_E, data input pin receives from the reference clock signal Ref_Clk_90 after the phase shift of phase shifter, and outfan is connected to the data input pin of the second depositor Reg_F.The reference clock signal Ref_Clk_180 that the clock input of the second depositor Reg_F is anti-phase, outfan is connected to the data input pin of the 3rd depositor Reg_G, the clock input reference clock signal Ref_Clk of the 3rd depositor, outfan output synchronous indicating signal Start_Sel.Bilateral along register circuit and MUX constitute synchronizing signal obtain circuit.Bilateral second and the 3rd Parasites Fauna including parallel connection along register circuit, second Parasites Fauna includes the 4th and the 5th depositor Reg_A, Reg_B of series connection, wherein, the input end of clock of the 4th and the 5th depositor Reg_A, Reg_B all receives reference clock signal Ref_Clk, the data input pin of the 4th depositor Reg_A receives input signal 1PPS_Start, outfan is connected to the data input pin of the 5th depositor Reg_B, one of outfan selection input being connected to MUX of the 5th depositor.3rd Parasites Fauna includes the 6th and the 7th depositor Reg_C, Reg_D of series connection, wherein, the reference clock signal Ref_Clk_180 that the clock input of the 6th depositor Reg_C is anti-phase, the data input pin of the 6th depositor receives input signal 1PPS_Start, outfan is connected to the data input pin of the 7th depositor Reg_D, the clock input reference clock signal Ref_Clk of the 7th depositor, outfan is connected to another selection input of MUX.The output Start_Sel selecting to control termination receipts from Reg_G of MUX, according to one of Start_Sel output selecting Reg_B and Reg_D, as the synchronizing signal Cnt_enable exported from outfan.

With reference to Figure 14 a and 14b, 1PPS_Start signal is used to sample the reference clock signal Ref_Clk_90 of 90 degree of phase shifts, to determine the relation between the 1PPS_Start time of advent and reference clock signal Ref_Clk rising edge.As shown in figures 14a, when Reg_E/Q is 0, i.e. Start_Sel is 0, represent the trailing edge sampling 1PPS_Start using Ref_ClK, now select the output of Reg_D as Cnt_enable；When Reg_E/Q is 1, i.e. Start_Sel is 1, represents the rising edge sampling 1PPS_Start using Ref_ClK, now select the output of Reg_B as Cnt_enable.It is noted here that, Reg_E can also be metastable state, because 1PPS_Start is asynchronous with the reference clock signal Ref_Clk_90 of 90 degree of phase shifts for the time of advent.But, bilateral along Parasites Fauna to synchronize 1PPS_Start owing to adopting, it is to avoid metastable generation, thus function and certainty of measurement will not be produced impact by the sampling uncertainty of Reg_E.

The foregoing describe the process about 1PPS_Start signal.For 1PPS_End signal, adopt and process like 1PPS_Start class signal, namely, Sync_End circuit is similar with structure with the function of TDC1 with TDC2 and Sync_Start circuit, only difference is that, the outlet end part of Sync_End circuit also includes monopulse generator, as shown in figure 15.It can be seen that the structure of Sync_End circuit previous section and Sync_Start circuit is completely the same, only in also added monopulse generator after MUX.Monopulse generator is constituted by depositor with door, wherein, the data input pin of depositor is connected to the outfan of MUX, clock input reference clock signal Ref_Clk, reversed-phase output is connected to and one of door input, with the outfan that another input of door is connected to MUX.So, the signal Sample_enable of outfan output is single pulse signal, the output of this single pulse signal obtains the Enable Pin (see Figure 12) of the depositor of circuit to cycle data, represents the rising edge detecting 1PPS_End signal, it should stop the counting of enumerator.Now, being exported to calibration cycle computing engines from the outfan Q of depositor by the count value CNT obtained, the latter, according to Start_Sel and End_Sel, utilizes T3, CNT and T4 to calculate calibration cycle T_real.

Figure 16 a-16d respectively illustrates the oscillogram of each coherent signal in the four kinds of situations adopting the trailing edge of reference clock signal Ref_Clk and rising edge 1PPS_Start and 1PPS_End signal to be sampled and obtains.Figure 16 a illustrates the situation for 1PPS_Start and 1PPS_End, Ref_ClK_90=0, i.e. the Ref_ClK_90 that 1PPS_Start and 1PPS_End samples is low level.It can be seen that after the rising edge of 1PPS_Start and 1PPS_End, the trailing edge at Ref_Clk detects 1PPS_Start and 1PPS_End, namely 1PPS_Start and 1PPS_End synchronizes with the trailing edge of reference clock signal Ref_Clk.In this case, T3=t0, T4=t1, Delta_TOD=CNT*T_real+t0-t1, such that it is able to adopt above-mentioned formula (5) to calculate T_real.

Figure 16 b illustrates the situation for 1PPS_Start and 1PPS_End, Ref_Clk_90=1, i.e. the Ref_Clk_90 that 1PPS_Start and 1PPS_End samples is high level.It can be seen that after the rising edge of 1PPS_Start and 1PPS_End, the rising edge at Ref_Clk detects 1PPS_Start and 1PPS_End, namely 1PPS_Start and 1PPS_End synchronizes with the rising edge of reference clock signal Ref_Clk.In this case, T3=t0, T4=t1, Delta_TOD=CNT*T_real+t0-t1, such that it is able to adopt above-mentioned formula (5) to calculate T_real.

Figure 16 c illustrates for 1PPS_Start, Ref_Clk90=1, and for 1PPS_End, the situation of Ref_Clk_90=0, it can be seen that after the rising edge of 1PPS_Start, the rising edge at Ref_Clk detects 1PPS_Start, and after the rising edge of 1PPS_End, the trailing edge at Ref_Clk detects 1PPS_End.That is, 1PPS_Start synchronizes with the rising edge of reference clock signal Ref_Clk, and 1PPS_End synchronizes with the trailing edge of reference clock signal Ref_Clk.Now, T3=t0, T4=t1, Delta_TOD=CNT*T_real+t0-t1+T/2, such that it is able to adopt above-mentioned formula (6) to calculate T_real.

Figure 16 d illustrates for 1PPS_Start, Ref_CLK_90=0, and for 1PPS_End, the situation of Ref_Clk_90=1, it can be seen that after the rising edge of 1PPS_Start, the trailing edge at Ref_Clk detects 1PPS_Start, and after the rising edge of 1PPS_End, the rising edge at Ref_Clk detects 1PPS_End.That is, 1PPS_Start synchronizes with the trailing edge of reference clock signal Ref_Clk, and 1PPS_End synchronizes with the rising edge of reference clock signal Ref_Clk.Now, T3=t0, T4=t1, Delta_TOD=CNT*T_real+t0-t1-T/2, such that it is able to adopt above-mentioned formula (7) to calculate T_real.

The T_real thus calculated can be supplied to counting circuit 12 shown in Fig. 1, or more specifically, be supplied to the second period counting circuit 32 shown in Fig. 3, to calculate the second period T1 and the three period T2 with reference to above-mentioned formula (3) and (4).Due to the reference clock cycle that T_real is corrected, the frequency shift (FS) therefore avoiding local reference clock self and the frequency shift (FS) caused due to extraneous factors such as temperature, further increase Time Calculation precision and postpone precision.

More than adopt 1PPS signal as input signal, signal delay device according to embodiments of the present invention and exemplary circuit structure thereof have been described in detail.But, it will be understood by those skilled in the art that and the invention is not restricted to above-mentioned concrete example.

It is described referring to Figure 17 and 18 pairs of signal delay methods according to embodiments of the present invention.Figure 17 illustrates the flow chart of signal delay method according to embodiments of the present invention.Method 170 includes: step S171, utilizes reference clock signal that input signal is synchronized, and exports the input signal after synchronization as the first synchronizing signal, and described first synchronizing signal was delayed by for the first period relative to input signal；Step S172, it is determined that the first period, and the second period and the 3rd period is calculated according to scheduled time slot and the first period, wherein, the first period, the second period are equal to scheduled time slot with the 3rd period sum；Step S173, by the first second period of sync signal delay, and exports the first synchronizing signal after delay, postpones signal as first；And step S174, postpone signal delay the 3rd period by first, it is thus achieved that second postpones signal, as inputting the signal after signal delays scheduled time slot.

According to embodiments of the present invention, in step S171, adopt input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and obtains indicating the rising edge that should use reference clock or trailing edge to carry out the first synchronous indicating signal synchronized；And utilize the rising edge of reference clock signal and trailing edge that input signal is synchronized, and when the first synchronous indicating signal indicates the rising edge of reference clock signal, select the input signal after being synchronized by the rising edge of reference clock signal, as the first synchronizing signal, and when the first synchronous indicating signal indicates the trailing edge of reference clock signal, select the input signal after being synchronized by the rising edge of reference clock signal, as the first synchronizing signal.

According to embodiments of the present invention, in step S172, determine the delay relative to input signal of the rising edge of reference clock signal and trailing edge, and according to the first synchronous indicating signal, select the delay relative to input signal of the rising edge of reference clock signal or trailing edge as the first period T0, and calculate the second period T1 and the three period T2 according to formula (1) and (2).

According to embodiments of the present invention, in step S173, utilize the delay circuit based on reference clock cycle by the first second period of sync signal delay.

According to embodiments of the present invention, in step S174, programmable delay chain is utilized to postpone signal delay the 3rd period by second.

According to embodiments of the present invention, method 170 can also include aligning step, utilizes input signal that the cycle of reference clock signal is corrected in this step, and the cycle after output calibration, as calibration cycle T_real.Thus, in step S172, formula (3) and (4) is adopted to calculate the second period T1 ' and the 3rd period T2 '.

Figure 18 illustrates the flow chart of aligning step according to embodiments of the present invention, as it can be seen, flow process 180 includes: step S181, utilizes reference clock signal that input signal is synchronized, and exports the input signal after synchronization, as the second synchronizing signal；Step S182, utilizes reference clock signal to input signal to second and synchronizes, and exports the second input signal after synchronization, and as the 3rd synchronizing signal, described second input signal is the signal after input signal carries out predetermined delaying；Step S183, calculates the delay relative to input signal of second synchronizing signal as the 4th period；Step S184, calculated the 3rd synchronizing signal and inputs the delay of signal relative to second, as the 5th period；Step S185, in response to the second synchronizing signal obtained in step S181, start in units of the cycle of reference clock signal, enumerator is utilized to count, and in response to the 3rd synchronizing signal obtained in step S182, stop the counting of enumerator the count value that output counter obtains, as number of cycles；Step S186, utilize the second input signal relative to the input predetermined delay of signal, the 4th and the 5th period and number of cycles, calculate calibration cycle.

According to embodiments of the present invention, in step S181, adopt input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and export instruction should use the rising edge of reference clock or the second synchronous indicating signal of trailing edge；And utilize the rising edge of reference clock signal and trailing edge that input signal is synchronized, and when the second synchronous indicating signal indicates the rising edge of reference clock signal, select by the input signal of the rising edge synch of reference clock signal, as the second synchronizing signal, and when the second synchronous indicating signal indicates the trailing edge of reference clock signal, select by the input signal of the rising edge synch of reference clock signal, as the second synchronizing signal.Now, in step S183, it is determined that the rising edge of reference clock signal and trailing edge are relative to the delay inputting signal, and according to the second synchronous indicating signal, the rising edge of selection reference clock signal or trailing edge are relative to the delay inputting signal, as the 4th period.

According to embodiments of the present invention, in step S182, adopt the second input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and export instruction should use the rising edge of reference clock or the 3rd synchronous indicating signal of trailing edge；The rising edge and the trailing edge that utilize reference clock signal input signal to second and synchronize, and when the 3rd synchronous indicating signal indicates the rising edge of reference clock signal, select by the second input signal of the rising edge synch of reference clock signal, as the 3rd synchronizing signal, and when the 3rd synchronous indicating signal indicates the trailing edge of reference clock signal, select by the second input signal of the rising edge synch of reference clock signal, as the 3rd synchronizing signal.Now, in step S184, it is determined that the rising edge of reference clock signal and trailing edge input the delay of signal relative to second, and according to the 3rd synchronous indicating signal, the rising edge of selection reference clock signal or trailing edge input the delay of signal relative to second, as the 5th period.

In step S186, according to second and the 3rd instruction of synchronous indicating signal, it is respectively adopted above-mentioned formula (5)-(7) and calculates calibration cycle T_real.

Although above method flow process sequentially illustrates each step, it will be recognized to those skilled in the art that some step is can executed in parallel or can exchange the order of execution.The signal delay method of the present invention is not limited to shown here concrete grammar flow process.

The foregoing describe signal delay device and method according to the preferred embodiment of the invention.In the above description, only in an illustrative manner, it is shown that the preferred embodiments of the present invention, but be not intended that the invention be limited to above-mentioned steps and cellular construction.In a likely scenario, it is possible to as required step and unit are adjusted, accept or reject and combine.Additionally, element necessary to the overall invention thought of some step and the unit not enforcement present invention.Therefore, technical characteristic essential to the invention is limited solely by the minimum requirements of the overall invention thought being capable of the present invention, and not by the restriction of above instantiation.

So far already in connection with preferred embodiment, invention has been described.It should be understood that those skilled in the art are without departing from the spirit and scope of the present invention, it is possible to carry out other change, replacement and interpolation various.Therefore, the scope of the present invention is not limited to above-mentioned specific embodiment, and should be defined by the appended claims.

Claims

1. a signal delay device, it is possible to inputting signal delay scheduled time slot, this signal delay device includes:

Second delay circuit, postpones signal delay the 3rd period by first, it is thus achieved that second postpones signal, as inputting the signal after signal delays scheduled time slot；

Wherein said signal delay device also includes: correcting circuit, utilizes input signal that the cycle of reference clock signal is corrected, and the cycle after output calibration, as calibration cycle；

Described correcting circuit includes:

Second synchronous circuit, utilizes reference clock signal that input signal is synchronized, and exports the input signal after synchronization, as the second synchronizing signal；

3rd synchronous circuit, utilizes reference clock signal to input signal to second and synchronizes, and exports the second input signal after synchronization, and as the 3rd synchronizing signal, described second input signal is the signal after input signal carries out predetermined delay；

4th period counting circuit, calculates the delay relative to input signal of second synchronizing signal as the 4th period；

5th period counting circuit, calculated the 3rd synchronizing signal and inputs the delay of signal relative to second, as the 5th period；

Number of cycles obtains circuit, in response to the second synchronizing signal, starts in units of the cycle of reference clock signal, utilize enumerator to count, and in response to the 3rd synchronizing signal, stop the counting of enumerator, and the count value that output counter obtains, as number of cycles；And

Calibration cycle counting circuit, utilize the second input signal relative to the input predetermined delay of signal, the 4th and the 5th period and number of cycles, calculate calibration cycle.

2. signal delay device according to claim 1, wherein, the first synchronous circuit includes:

First synchronous regime testing circuit, adopt input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and obtains indicating the rising edge that should use reference clock or trailing edge to carry out the first synchronous indicating signal synchronized；And

First synchronizing signal obtains circuit, input signal is synchronized by the rising edge and the trailing edge that utilize reference clock signal, and when the first synchronous indicating signal indicates the rising edge of reference clock signal, select the input signal after being synchronized by the rising edge of reference clock signal, as the first synchronizing signal, and when the first synchronous indicating signal indicates the trailing edge of reference clock signal, select the input signal after being synchronized by the trailing edge of reference clock signal, as the first synchronizing signal.

3. signal delay device according to claim 2, wherein, the first synchronous regime testing circuit includes phase shifter and the first Parasites Fauna,

Phase shifter receives reference clock signal and by its phase shift 90 degree,

First Parasites Fauna includes first, second, and third depositor of series connection,

The clock input input signal of the first depositor, data input pin receives from the reference clock signal after the phase shift of phase shifter, and outfan is connected to the data input pin of the second depositor,

The reference clock signal that the clock input of the second depositor is anti-phase, outfan is connected to the data input pin of the 3rd depositor,

The clock input reference clock signal of the 3rd depositor, outfan exports described first synchronous indicating signal.

4. signal delay device according to claim 2, wherein, the first synchronizing signal obtains circuit and includes bilateral along register circuit with MUX,

Bilateral second and the 3rd Parasites Fauna including parallel connection along register circuit,

Second Parasites Fauna includes the 4th and the 5th depositor of series connection, wherein, the input end of clock of the 4th and the 5th depositor all receives reference clock signal, the data input pin of the 4th depositor receives input signal, outfan is connected to the data input pin of the 5th depositor, one of outfan selection input being connected to MUX of the 5th depositor；

3rd Parasites Fauna includes the 6th and the 7th depositor of series connection, wherein, the reference clock signal that the clock input of the 6th depositor is anti-phase, the data input pin of the 6th depositor receives input signal, outfan is connected to the data input pin of the 7th depositor, the clock input reference clock signal of the 7th depositor, outfan is connected to another selection input of MUX；

First synchronous indicating signal selecting to control termination receipts from the first synchronous regime testing circuit of MUX, outfan exports the first synchronizing signal.

5. signal delay device according to claim 2, wherein, counting circuit includes:

First period counting circuit, it is determined that the rising edge of reference clock signal and trailing edge are relative to the delay of input signal, and according to the first synchronous indicating signal, selects the delay relative to input signal of the rising edge of reference clock signal or trailing edge as the first period；

Second period counting circuit, received for the first period, the second period T1 calculated as below:

T1=FLOOR ((Delay-T0)/T) * T,

Wherein, FLOOR is downward rounding operation symbol, and Delay represents described scheduled time slot, and T0 represented for the first period, and T represents the cycle of reference clock signal；

3rd period counting circuit, receives the first period and the second period, the 3rd period T2 calculated as below:

T2=Delay-(T0+T1).

6. signal delay device according to claim 1, wherein, the first delay circuit includes the delay circuit based on reference clock cycle, with by the first second period of sync signal delay.

7. signal delay device according to claim 1, wherein, the second delay circuit includes programmable delay chain, according to the 3rd period, delay chain is programmed, and postpones signal delay the 3rd period by the delay chain after programming by second.

8. signal delay device according to claim 5, wherein, the first period counting circuit includes bilateral along time-to-digital conversion circuit with MUX,

Bilateral include the first and second Parasites Fauna and delay chain along time-to-digital conversion circuit,

Each group of n the depositor including parallel connection in first Parasites Fauna and the second Parasites Fauna, delay chain includes n-1 delay cell of series connection, and n is greater than being equal to the integer of 1,

One of outfan selection input being connected to MUX of each depositor in first Parasites Fauna and the second Parasites Fauna,

The clock input reference clock signal of first depositor in first Parasites Fauna, data input pin receives input signal, the reference clock signal that in second Parasites Fauna, the clock input of first depositor is anti-phase, data input pin receives input signal, the input of first delay cell of delay chain receives input signal

In each group of first Parasites Fauna and the second Parasites Fauna, the data input pin of m-th depositor is connected to the outfan of m-1 delay cell of delay chain, and m is the integer more than 1 and less than or equal to n；

The selecting of MUX controls termination and receives from the first synchronous indicating signal of the first synchronous circuit, and outfan is connected to second and the 3rd period counting circuit.

9. signal delay device according to claim 5, wherein, counting circuit receives the calibration cycle from correcting circuit output, and utilizes described calibration cycle in the calculation.

10. signal delay device according to claim 9, wherein,

Second period counting circuit the second period T1 ' calculated as below:

T1 '=FLOOR ((Delay-T0)/T_real) * T_real,

3rd period counting circuit the 3rd period T2 ' calculated as below:

T2 '=Delay-(T0+T1 '),

Wherein, FLOOR is downward rounding operation symbol, and Delay represents described scheduled time slot, and T0 represented for the first period, and T_real represents described calibration cycle.

11. signal delay device according to claim 1, wherein, the second synchronous circuit includes:

Second synchronous regime testing circuit, adopt input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and export instruction should use the rising edge of reference clock or the second synchronous indicating signal of trailing edge；And

Second synchronizing signal obtains circuit, input signal is synchronized by the rising edge and the trailing edge that utilize reference clock signal, and when the first synchronous indicating signal indicates the rising edge of reference clock signal, select the input signal after being synchronized by the rising edge of reference clock signal, as the first synchronizing signal, and when the first synchronous indicating signal indicates the trailing edge of reference clock signal, select the input signal after being synchronized by the rising edge of reference clock signal, as the first synchronizing signal；

Wherein, the delay relative to input signal of the rising edge of reference clock signal and trailing edge determined by 4th period counting circuit, and according to the second synchronous indicating signal, the rising edge of selection reference clock signal or trailing edge are relative to the delay inputting signal, as the 4th period.

12. signal delay device according to claim 1, wherein, the 3rd synchronous circuit includes:

3rd synchronous regime testing circuit, adopt the second input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and export instruction should use the rising edge of reference clock or the 3rd synchronous indicating signal of trailing edge；And

3rd synchronizing signal obtains circuit, the rising edge and the trailing edge that utilize reference clock signal input signal to second and synchronize, and when the 3rd synchronous indicating signal indicates the rising edge of reference clock signal, select by the second input signal of the rising edge synch of reference clock signal, as the 3rd synchronizing signal, and when the 3rd synchronous indicating signal indicates the trailing edge of reference clock signal, select by the second input signal of the rising edge synch of reference clock signal, as the 3rd synchronizing signal；

Wherein, 5th period counting circuit determines that the rising edge of reference clock signal and trailing edge input the delay of signal relative to second, and according to the 3rd synchronous indicating signal, the rising edge of selection reference clock signal or trailing edge input the delay of signal relative to second, as the 5th period.

13. a signal delay method, it is possible to inputting signal delay scheduled time slot, this signal delay method comprises the steps:

D. signal delay the 3rd period is postponed by first, it is thus achieved that second postpones signal, as inputting the signal after signal delays scheduled time slot；

Wherein, described signal delay method also comprises the steps:

E. utilize input signal that the cycle of reference clock signal is corrected, and the cycle after output calibration, as calibration cycle；

Wherein, step e includes:

F. utilize reference clock signal that input signal is synchronized, and export the input signal after synchronization, as the second synchronizing signal；

G. utilizing reference clock signal to input signal to second to synchronize, and export the second input signal after synchronization, as the 3rd synchronizing signal, described second input signal is the signal after input signal carries out predetermined delaying；

H. the delay relative to input signal of second synchronizing signal is calculated as the 4th period；

I. calculate the 3rd synchronizing signal and input the delay of signal relative to second, as the 5th period；

J. in response to the second synchronizing signal obtained in step f, start in units of the cycle of reference clock signal, utilize enumerator to count, and in response to the 3rd synchronizing signal obtained in step g, stop the counting of enumerator the count value that output counter obtains, as number of cycles；And

K. utilize the second input signal relative to the input predetermined delay of signal, the 4th and the 5th period and number of cycles, calculate calibration cycle.

14. signal delay method according to claim 13, wherein, in step a,

Adopt input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, obtain indicating the rising edge that should use reference clock or trailing edge to carry out the first synchronous indicating signal synchronized

Input signal is synchronized by the rising edge and the trailing edge that utilize reference clock signal, and when the first synchronous indicating signal indicates the rising edge of reference clock signal, select the input signal after being synchronized by the rising edge of reference clock signal, as the first synchronizing signal, and when the first synchronous indicating signal indicates the trailing edge of reference clock signal, select the input signal after being synchronized by the rising edge of reference clock signal, as the first synchronizing signal.

15. signal delay method according to claim 13, wherein, in stepb, determine the delay relative to input signal of the rising edge of reference clock signal and trailing edge, and according to the first synchronous indicating signal, select the delay relative to input signal of the rising edge of reference clock signal or trailing edge as the first period T0, and the second period T1 and the three period T2 calculated as below:

T1=FLOOR ((Delay-T0)/T) * T, T2=Delay-(T0+T1)

Wherein, FLOOR is downward rounding operation symbol, and Delay represents described scheduled time slot, and T represents the cycle of reference clock signal.

16. signal delay method according to claim 13, wherein, in step c, utilize the delay circuit based on reference clock cycle by the first second period of sync signal delay.

17. signal delay method according to claim 13, wherein, in step d, programmable delay chain is utilized to postpone signal delay the 3rd period by second.

18. signal delay method according to claim 15, wherein, in stepb, utilize in the calculation in the step e calibration cycle calculated.

19. signal delay method according to claim 18, wherein, in stepb, the second period T1 ' and the 3rd period T2 ' calculated as below:

T1 '=FLOOR ((Delay-T0)/T_real) * T_real, T2 '=Delay-(T0+T1 ')

Wherein, FLOOR is downward rounding operation symbol, and Delay represents described scheduled time slot, and T0 represented for the first period, and T_real represents calibration cycle.

20. signal delay method according to claim 13, wherein, in step f,

Adopt input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and export instruction should use the rising edge of reference clock or the second synchronous indicating signal of trailing edge

Input signal is synchronized by the rising edge and the trailing edge that utilize reference clock signal, and when the second synchronous indicating signal indicates the rising edge of reference clock signal, select by the input signal of the rising edge synch of reference clock signal, as the second synchronizing signal, and when the second synchronous indicating signal indicates the trailing edge of reference clock signal, select by the input signal of the rising edge synch of reference clock signal, as the second synchronizing signal；

In step h, it is determined that the rising edge of reference clock signal and trailing edge are relative to the delay inputting signal, and according to the second synchronous indicating signal, the rising edge of selection reference clock signal or trailing edge are relative to the delay inputting signal, as the 4th period.

21. signal delay method according to claim 20, wherein, in step f,

Adopt the second input signal that the reference clock signal through predetermined phase shift is sampled, according to sampled result, detection should use the rising edge of reference clock signal or trailing edge synchronizes, and export instruction should use the rising edge of reference clock or the 3rd synchronous indicating signal of trailing edge

The rising edge and the trailing edge that utilize reference clock signal input signal to second and synchronize, and when the 3rd synchronous indicating signal indicates the rising edge of reference clock signal, select by the second input signal of the rising edge synch of reference clock signal, as the 3rd synchronizing signal, and when the 3rd synchronous indicating signal indicates the trailing edge of reference clock signal, select by the second input signal of the rising edge synch of reference clock signal, as the 3rd synchronizing signal；

In step i, it is determined that the rising edge of reference clock signal and trailing edge input the delay of signal relative to second, and according to the 3rd synchronous indicating signal, the rising edge of selection reference clock signal or trailing edge input the delay of signal relative to second, as the 5th period.

22. signal delay method according to claim 21, wherein, in step k,

When the second synchronous indicating signal instruction uses the rising edge of reference clock signal, and when the 3rd synchronous indicating signal instruction uses the rising edge of reference clock signal, or when the second synchronous indicating signal instruction uses the trailing edge of reference clock signal, and when the 3rd synchronous indicating signal instruction uses the trailing edge of reference clock signal, calibration cycle calculated as below:

T_real=(Delta_TOD-T3+T4)/CNT,

When the second synchronous indicating signal instruction uses the rising edge of reference clock signal, and during the trailing edge of the 3rd synchronous indicating signal instruction use reference clock signal, calibration cycle calculated as below:

T_real=(Delta_TOD-T3+T4)/(CNT+0.5),

When the second synchronous indicating signal instruction uses the trailing edge of reference clock signal, and during the rising edge of the 3rd synchronous indicating signal instruction use reference clock signal, calibration cycle calculated as below:

T_real=(Delta_TOD-T3+T4)/(CNT-0.5),

Wherein, T_real represents that calibration cycle, Delta_TOD represent that predetermined delay, T3 represented for the 4th period, and T4 represented for the 5th period, and CNT represents number of cycles.

23. signal delay method according to claim 13, wherein, input signal has the field that the time difference between the adjacent rising edges to this input signal or trailing edge indicates,

Utilize described time difference as the described predetermined delay between input signal and the second input signal.

24. signal delay method according to claim 13, wherein, input signal is 1PPS+TOD time interface signal.