CN102096648A - System and method for realizing multipath burst data business caching based on FPGA (Field Programmable Gate Array) - Google Patents
System and method for realizing multipath burst data business caching based on FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention discloses a system and method for realizing multipath burst data business caching based on an FPGA (Field Programmable Gate Array), wherein the system comprises an off-chip cache and an FPGA chip, wherein the off-chip cache is used for caching multipath burst data, and the FPGA chip is used for providing an RAM (Random Access Memory) resource; the FPGA chip also comprises an off-chip cache controller, a multipath burst data caching management circuit, packet receiving and buffering circuits with the same number as that of data channels, a packet write control circuit, a packet read control circuit and a packet buffering and transmitting circuit, wherein the multipath burst data caching management circuit is used for processing request arbitration and channel authorization of the multipath burst data, generating line address information of current read/write operation and writing a packet into the off-chip cache or reading the packet from the off-chip cache. By adopting the invention, the number of the channels can be simply increased or reduced, and each path of burst data business can be relatively and evenly cached so that bottleneck caused by internal RAM shortage of an FPGA chip can be avoided.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of system and method for realizing multichannel bursty data service buffer based on FPGA.
Background technology
In communication technical field, the telecommunications data traffic that often need have characteristics such as burst, elongated, non-timed to multichannel carries out caching process, with the processing of level module fixed rate after an action of the bowels; For the protocol conversion of different rates, more need multichannel bursty data business is carried out caching process especially; In existing technology, to the buffer memory of multichannel bursty data business, multiple caching method is arranged, its implementation is respectively.
(1) adopt the special ASIC chip to realize in the mode of piling up; But the port number that the special ASIC chip provides is limited, and every asic chip needs independent plug-in memory chip; Realizing that more multichannel (N〉2) when bursty data is professional, just needs more asic chip and memory chip, cause the hardware cost height, veneer wiring difficulty is big.
(2) adopt the FPGA ram in slice to realize; Present FPGA inside generally all provides some, and the RAM of fixed capacity size utilizes the combination of these RAM resources, and the mode of data queue is independently adopted on every road, realizes the buffer memory (see figure 1) of multichannel data business; But the ram in slice resource that FPGA provides is very limited, causes data queue's degree of depth of distributing to multichannel data limited on the one hand, can't tackle the bursty data as video data; If satisfy the certain depth of data queue, it is limited that the number of channels of buffer memory multichannel data just becomes, and can't realize the more situation of port number on the other hand.
(3) adopt the outer RAM chip of FPGA ram in slice engagement tabs to realize; As the mode that Fig. 2 adopted, the moderator that multichannel bursty data business is realized by the FPGA internal logic is cached in the outer RAM chip of sheet in the fixed priority mode, and each data packet length information stores of every road bursty data is in the data packet length RAM that is made up of the FPGA ram in slice; Want flexibly this mode phase ratio method (1), (2), but still there is defective: one, data packet length RAM by the realization of FPGA ram in slice, its degree of depth has determined to be cached to the packet number of the outer RAM chip of sheet, because FPGA ram in slice resource-constrained, limit the degree of depth of data packet length RAM on the one hand, promptly limited the number that is cached to the outer RAM packet of sheet; When satisfying the requirement of the data packet length RAM degree of depth, limited the port number number again on the other hand; Two, when the multichannel bursty data adopted the fixed priority mode to be cached to the outer RAM of sheet, the high passage of priority can cause the data service of the low passage of priority to can not get timely processing under the big situation of data business volume, occurs " hungry full " phenomenon easily.
Summary of the invention
The objective of the invention is to overcome the existing shortcoming of said method, a kind of system and method for realizing multichannel bursty data service buffer based on FPGA is provided.
The embodiment of the invention is achieved in that a kind of system of the realization multichannel bursty data service buffer based on FPGA, comprises sheet External Registers that is used for buffer memory multichannel bursty data and the fpga chip that the RAM resource is provided; Described fpga chip comprises: the outer cache controller of sheet, multichannel bursty data cache management circuit, and the packet reception consistent with the data channel number and buffer circuit, packet write control circuit, packet buffering and transtation mission circuit, packet are read control circuit; Wherein,
Described packet receives and buffer circuit, its input end receives extraneous bursty data input, output terminal and is connected with the packet write control circuit, comprise packet reception control circuit and send buffer, be used for receiving the bursty data of extraneous input and it being write send buffer when empty at send buffer, and when writing complete packet the whole bag of set zone bit;
Described packet write control circuit, its input end receives with packet and buffer circuit is connected, output terminal is connected with multichannel bursty data cache management circuit, be used for being set and the buffer area of chip external memory respective channel when being non-full state at described whole bag zone bit, under the also authorized situation of multichannel burst packet cache management circuit application, read packet complete in the send buffer and itself and its length information is combined in the buffer area of new data flow cache respective channel in the chip external memory, generate the row address information of next write operation simultaneously;
Described packet buffering and transtation mission circuit, its input end read with packet that control circuit is connected, output terminal is connected with extraneous port, comprise sending buffer zone and packet sending controling circuit, are used to cushion complete packet and send it to extraneous port;
Described packet is read control circuit, its input end is connected with multichannel bursty data cache management circuit, output terminal is connected with packet buffering and transtation mission circuit, when the buffer area that is used for sending buffer zone and is sky and chip external memory respective channel is non-dummy status, after under the also authorized situation of multichannel burst packet cache management circuit application, from chip external memory, reading complete packet in the buffer area of respective channel, write in the transmission buffer zone, generate the row address information of next read operation simultaneously;
Described multichannel burst packet cache management circuit, be connected to multichannel data bag write control circuit and packet respectively and read control circuit, and be connected with the outer cache controller of sheet, be used for receive the multichannel bursty data read to wrap apply for/write when application bag the bursty data passage that sends application is arbitrated and authorize, the concrete read operation/write operation of channel grant to authorizing again, generate the column address information of current read/write operation, write the data packet the sheet External Registers or packet is read out from the sheet External Registers;
Described outer cache controller is connected respectively with the sheet External Registers with multichannel burst packet cache management circuit, is used for the sheet External Registers is controlled.
Wherein, described multichannel bursty data cache management circuit comprises: multichannel bursty data combined arbitration device, read-write arbitration circuit, burst management circuit, cache user interface, buffer state management circuit, write end data and address selector, read end data and address selector, read authority control circuit, write the authorization control circuit.
Wherein, described multichannel bursty data combined arbitration device, be used for mode that single channel request adopts fixed priority is only arranged or greater than the mode that adopted circular priority at 1 o'clock each bursty data passage being arbitrated and being authorized in the quantity of current channel request current, and the bursty data channel information of authorizing offered the read-write arbitration circuit, authorize concrete read operation or write operation by it.
Described burst management circuit is used for generating the column address of the sheet External Registers of current operation in read operation or write operation process, finishes the conversion of sheet External Registers address and the interface signal of the outer cache controller of generation sheet in view of the above by the cache user interface simultaneously.
Described buffer state management circuit, comprise a N consistent package counting facility with the bursty data port number, be used for the sheet External Registers is carried out real-time statistics respectively corresponding to the number of the packet in each bursty data passage buffer storage district, road, the package counting facility value of every road correspondence during greater than max-thresholds/less than minimum threshold corresponding write authorization control circuit/read authority control circuit and the packet write control circuit/packet of notice read its corresponding cache region of control circuit and be full state/dummy status, multichannel bursty data combined arbitration device will be in view of the above state packet write control circuit/packet of ending the response respective channel read writing of control circuit and wrap/read the bag application, the packet write control circuit/packet of respective channel is read control circuit simultaneously will expire state/dummy status in view of the above and end to send to write and wrap/read bag application.
Describedly write end data and address selector/read end data and address selector are used for selecting according to the arbitration result of multichannel bursty data combined arbitration device institute's authorised channel when write operation/read operation corresponding packet and row address.
Wherein, described send buffer is made up of the ram in slice storer with ping-pong work of 2 dual-ports; Described transmission buffer zone is made up of the ram in slice storer of 1 dual-port.
Wherein, it is 8 that the address wire of the write port of the ram in slice storer of described composition send buffer has 11, input data width, and it is 64 that the address wire of read port has 8, output data width.
It is 64 that the address wire of write port that described composition sends the ram in slice storer of buffer zone has 8, write data width, and it is 8 that the address wire of read port has 11, read data width.
Wherein, described External Registers is made up of 2 16 chip external memory.
Wherein, described chip external memory is divided into the storage block of a plurality of same capability sizes, and wherein continuous a plurality of storage blocks are formed buffer area and distributed to each road bursty data passage.
Wherein, described chip external memory is divided into the storage block of a plurality of 2048 byte-sized.
A kind of method of realization multichannel bursty data service buffer of system as mentioned above comprises: receive the step of data processing, the step of write data application, the step of multichannel bursty data arbitration management, the step of read data application and the step that sends data processing; Wherein,
The step of described reception data processing comprises: bursty data when input arranged in the external world, judge that whether send buffer is whether the buffer area of respective channel in sky and the sheet External Registers is non-full, if not, then abandons the packet of current input; If, then this packet is write in the send buffer by byte, add up the byte number of this packet simultaneously, and when receiving a complete packet the whole bag of set zone bit;
The step of write data application comprises: inquire about the whole bag zone bit in the send buffer in real time, when detecting set, initiate to write the bag application to multichannel burst packet cache management circuit, and by application and when authorized, read packet content complete in the send buffer and with its and this length of data package message block synthesize new data flow cache in the chip external memory corresponding in this bursty data passage buffer storage district;
The step of described multichannel bursty data arbitration management comprises: inquire about the read of each paths in real time, carry out earlier the arbitration of request and the mandate of passage are read and write arbitration to the passage of authorizing again, generate read operation mandate or write operation mandate;
The step of described read data application comprises: whether the buffer area that detect to send buffer zone and whether be respective channel in sky and the sheet External Registers non-NULL, if, then initiate to read the bag application to multichannel burst packet cache management circuit, and by application and when authorized, from the sheet External Registers, read complete packet in the buffer area of respective channel and from wherein isolating packet content and data length information, the record data length information writes packet content in the transmission buffer zone;
The step of described transmission data processing comprises: detect to send in the buffer zone whether complete packet is arranged, then read data packet and send it to extraneous output terminal from send buffer zone.
Wherein, in the step of described multichannel bursty data arbitration management,, adopt the mode of circular priority or fixed priority to realize to the arbitration of request and the mandate of passage according to the quantity of current channel request.
Wherein, if current only have a single channel request, then adopt the mode of fixed priority to realize to the arbitration of request and the mandate of passage; If the quantity of current channel request greater than 1, then adopts the mode of circular priority to realize the arbitration of request and the mandate of passage.
Wherein, described method also comprises the step of system initialization, and this step further comprises:
Behind the electrification reset, system carries out initialization procedure immediately, row, column address zero clearing with each passage in the fpga chip, package counting facility, length counter zero clearing in the buffer state management, RAM read/write address, the whole zero clearings of passage read-write requests, each buffer zone, buffer area are made as dummy status, and each road buffer area pipeline depth is set, and each steering logic of inside is located at idle condition.
The embodiment of the invention compared with prior art, beneficial effect is:
1) the present invention adopts FPGA to realize the buffer memory of multichannel bursty data business, be particularly suitable for the caching process of the multichannel communication multiple telecommunication data in the data communications equipment, can realize the buffer memory of multichannel (N〉2) bursty data business, realize flexibly relatively, can dispose more passage as requested.
2) the present invention's mode of adopting circular priority to combine with fixed priority realizes the operation arbitration to the multichannel bursty data, makes the bursty data business on each road can obtain the buffer memory of relative equilibrium.
3) the present invention is combined into new data stream with data length information and date content, leaves in the outer storer of sheet, has avoided the data length record sheet to cause the bottleneck of FPGA ram in slice shortage of resources.
4) the present invention adopts unique system architecture, reaches the FPGA resource situation according to demand, can simply increase or reduce the passage number in modular mode, to be fit to different applicable cases.
5) the present invention adopts the simple address generting machanism to the visit of chip external memory, does not need to adopt complicated chained list, make the BANK of chip external memory, row, column address independently to produce, and the generation of column address is not subjected to the influence of passage number.
Description of drawings
Fig. 1 adopts the FPGA ram in slice to realize the system chart of the multi-channel data buffer memory of data queue.
Fig. 2 adopts the outer RAM of FPGA ram in slice and sheet to combine to realize the system chart of multi-channel data buffer memory.
Fig. 3 is the system chart that the employing FPGA that provides of the embodiment of the invention realizes multichannel bursty data service buffer.
Fig. 4 is the storage block that provides of the embodiment of the invention and the division synoptic diagram of multichannel bursty data buffer area.
Fig. 5 is the circular priority distribution method synoptic diagram that the embodiment of the invention provides
Fig. 6 is that the single channel bursty data that the embodiment of the invention provides receives processing flow chart.
Fig. 7 is that the single channel bursty data that the embodiment of the invention provides is write the control and treatment process flow diagram.
Fig. 8 is the multichannel bursty data cache management process flow diagram that the embodiment of the invention provides.
Fig. 9 is that the single channel bursty data that the embodiment of the invention provides is read the control and treatment process flow diagram.
Figure 10 is that the single channel bursty data that the embodiment of the invention provides sends control flow chart.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
(1), as shown in Figure 3, adopt FPGA to realize that the system of multichannel bursty data service buffer comprises: fpga chip 1 and sheet External Registers 2 that the block RAM resource is provided in the present embodiment.
Fpga chip wherein further comprises: packet reception consistent with the data channel number and buffer circuit 11, packet write control circuit 12, packet are read control circuit 13, packet buffering and transtation mission circuit 14, multichannel bursty data cache management circuit 15, the outer cache controller 16 of sheet.
The annexation of above-mentioned each ingredient and principle of work are as described below respectively.
(1) packet receives and buffer circuit 11, the bursty data input that its input comes from the outside, output is connected to packet write control circuit 12, be used for be responsible for receiving the data of input end and with data buffering, and with the full state of the sky in the send buffer and whether there is the sign of whole bag to feed back to packet write control circuit 12.It includes the ping-pong buffer with ping-pong work that 2 two-port RAMs are formed, and buffering produces the full status signal of buffer empty simultaneously from the bursty data of external world's input.Address wire, the data line width difference of forming 2 two-port RAM reading-writing port of ping-pong buffer, the address wire of write port are that 11, data width are 8, and the address wire of read port be 8, data width is 64.
(2) the packet write control circuit 12, input receives and buffer circuit 1 from the bursty data of prime is professional, output is connected to multichannel bursty data cache management circuit 15, and the full status signal in each passage buffer storage zone state management also offers packet write control circuit 12 as input.It is used to be responsible under by application and authorized situation, with a complete data pack buffer in chip external memory corresponding cache district.
(3) packet is read control circuit 13, and its input is from multichannel bursty data cache management circuit 15, and output is connected to data pack buffer and transtation mission circuit 14.It is responsible for packet and reads, and under by application and authorization conditions, reads a complete packet and be written in the transmission buffer zone from chip external memory corresponding cache district.
(4) packet sends and buffer circuit 14, and its input is read control circuit 13 from packet, and output is connected to extraneous port.It is responsible for cushioning the whole packet that reads, and sends to the external world then.It includes the transmission data buffer of being made up of 1 two-port RAM, the address wire of the reading-writing port of two-port RAM, data line width difference, the address wire of write port is that 8, data line width are 64, is 8 and the address wire of read port is 11, data line width.
(5) multichannel bursty data cache management circuit 15, and its input and output read control circuit 13 with packet write control circuit 12, the packet on every road and the outer cache controller 16 of sheet links to each other.It is responsible for request, arbitration and the channel grant of multichannel bursty data, select data, address, the status information of authorised channel, the state of statistics buffer area generates column address, writes the data packet to chip external memory or packet is read out from chip external memory.It includes buffer state management circuit 151, multichannel bursty data combined arbitration device 152, read-write arbitration circuit 153, burst management circuit 154, cache user interface 155, writes end data and address selector 156, reads end data and address selector 157, writes functional modules such as authorization control circuit 158 and read authority control circuit.
Wherein: multichannel bursty data combined arbitration device 152 is the modes that adopt fixed priority to combine with circular priority, realizes request, arbitration, mandate to the multichannel bursty data.
Read that end data and address selector 156/ are write end data and address selector 157 all is that N selects 1 X position MUX, the size of N is with the bursty data port number correspondence of design, and for data selector, X is 2 times of total data bit width of chip external memory 2; For address selector, the row, column address bit length and the data bit width of the figure place heel piece external storage 2 of X are relevant.
Buffer state management circuit 151 contains the package counting facility of N K position, and the size of N is with bursty data port number correspondence, and the size of K is relevant with the degree of depth of the buffer area of respective channel; When corresponding buffer area write a bag on certain road, corresponding package counting facility added 1, and when taking a bag away, corresponding package counting facility subtracts 1; When the package counting facility value surpassed max-thresholds, the buffer area of respective channel was judged to dummy status, read this moment to hold no longer to send and read application; When the package counting facility value surpassed minimum threshold, the buffer area of respective channel was judged to full state, write end this moment and will no longer send and write application; Simultaneously, under the empty or full situation of buffer area, multichannel bursty data combined arbitration device 152 will no longer respond the request of reading or writing.
(6) the outer cache controller 16 of sheet, its input end, output terminal are connected with sheet External Registers 2 and multichannel bursty data cache management circuit 15 respectively; Soft the examining now of IP that the outer cache controller 16 of sheet adopts fpga chip manufacturer to provide.
(7) the sheet External Registers 2, and its input end, output terminal link to each other with the outer cache controller 16 of sheet, and it is the chip external memory that is independent of FPGA.
Sheet External Registers 2 is made up of the outer memory chip of sheet, according to the storage organization of storage chip inside, the memory block can be divided into the storage block of a plurality of 2048 byte-sized, and the memory unit address of each storage block is continuous.Continuous a plurality of storage blocks are formed buffer area, and each road bursty data passage is given in reallocation; Storage block can be divided according to row, column address, the data bit width of storage chip, if column address width is 10, the data bit width is 16, and then just in time delegation is divided into a storage block, complete packet of corresponding each storage block storage.And if that the size of each road buffer area is all distributed is identical, then can divide according to the BANK address of storage chip and the high address of row.If multichannel bursty data passage is 32, and storage chip BANK address width is 3, and then buffer area can be by 8 BANK, and each BANK is divided into four districts and divides, high 2 bit address at once are used for doing the division of four buffer areas in the BANK, and dividing mode can be with reference to the accompanying drawings 4.Therefore the address on every road produces, and just becomes very simple, and the address of row is generated by the burst administration module in the multichannel bursty data cache management circuit, and after each burst operation, column address increases by burst-length automatically; And the address of row is produced by the packet Writing/Reading control circuit on every road, promptly each past buffer area writes a complete packet, (high 2 bit address are used for the buffer area dividing region to row low (N-2) bit address, constant after distributing) add 1 automatically, read a complete packet from buffer area, the row low order address subtracts 1 automatically at every turn.
In addition, packet receives and buffer circuit 11 contains Data Receiving control circuit and data packet buffer, Data Receiving control circuit wherein is used for being responsible for the ablation process of the extraneous input of control data to data bag buffer zone, generation write address (wr_ram_adr) and relevant writing enable (wr_ram_en) signal, contain 2 data packet length registers (pkt_length_reg), 2 whole bag zone bits (full_pkt_flag), wherein: data packet length register (pkt_length_reg) is used for when a complete packet is written to the bag buffer zone, latch current write address (wr_ram_adr) value, when record length information of current data packet and packet write buffer area by the required burst number of times information of certain burst-length; Whether whole bag zone bit (full_pkt_flag) indicates buffer zone complete packet.
Packet write control circuit 12 is realized by internal logic, detect whole the bag when indicating (full_pkt_flag) set, initiate write request (ch_wr_req) to multichannel bursty data cache management circuit 15, etc. mandate to be written (ch_wr_gnt), the data query bag receives and the dummy status signal of the ping-pong buffer that buffer circuit 11 provides then, judge which buffer zone has whole bag, and in write data requests (ch_wdata_req) effectively under the situation, read the data of buffer zone and itself and data packet length message block are synthesized new data stream export to multichannel bursty data cache management circuit 15; And every after buffer area writes a complete data packet, row address (ch_wr_row_adr) adds 1 automatically, points to the line position that next packet is wanted buffer memory.
Multichannel bursty data cache management circuit 15 is realized by internal logic, and the read-write arbitration that the arbitration of a plurality of passages is authorized passage is authorized from function separately.Whether the multichannel bursty data combined arbitration device 152 real-time detections that include have channel request, and adopt the mode of circular priority or fixed priority to arbitrate according to a plurality of requests or single request and authorize which passage, and the passage of authorizing offered read-write arbitration circuit 153, read-write arbitration circuit 153 is with concrete the reading or write operation of authorised channel.Read or the write operation process in, burst management circuit 154 generates the column address (col_adr) of current operation, and column address (col_adr) increases by burst-length after each burst operation, wants burst position next time to point to; Cache user interface 155 is finished the conversion of sheet External Registers address simultaneously, and generates the interface signal of the outer cache controller 16 of sheet.The priority method of circular priority as shown in Figure 5, the bursty data passage that current priority is the highest is distributing medium priority minimum next time.
Packet is read control circuit 13, realize by internal logic control, when detecting the transmission buffer empty, and the outer buffer area of sheet is when having packet, initiate read request (ch_rd_req) to multichannel bursty data cache management circuit 15, and wait read authority (ch_rd_gnt), when read data useful signal (ch_rdata_valid) is effective, the data that read are written in the transmission buffer zone, latch the data packet length information (pkt_length_info) that reads simultaneously, data packet length information (pkt_length_info) provides current read data packet by the required burst number of times of certain burst-length.
Packet sends and buffer circuit 14, contains data and reads control circuit and send buffer zone, and data are read control circuit when the transmission buffer area has complete data packet, generate read control signal, and control sends the data read of buffer zone.
(2), the course of work of said system is:
(1) initialization procedure.
Behind the electrification reset, system carries out initialization procedure immediately, all zero clearings such as the row address of each passage in the FPGA sheet, length counter, RAM read/write address, passage read, column address, package counting facility, each buffer state in the buffer state management is empty, each road buffer area pipeline depth is set, and each inner control logic is in idle condition.
(2) receive data processing.
With reference to the accompanying drawings 6, the concrete treatment scheme in this process is: if extraneous data input is arranged, check whether ping-pong buffer is empty, check whether the outer buffer state of corresponding sheet is non-full, if condition is false, then abandons the packet of current input; If condition is set up, then will import data is written in the ping-pong buffer by byte, the byte number of the data of counting input simultaneously, after receiving a complete packet, the write address (wr_ram_adr) that latchs ping-pong buffers is in data packet length register (pkt_length_reg), and set simultaneously is whole bag sign (full_pkt_flag) accordingly.
(3) write data application.
With reference to the accompanying drawings 7, concrete treatment scheme in this process is: the packet write control circuit is inquired about whole bag sign (full_pkt_flag) under the clock period, when detecting whole bag flag set, known ping-pong buffer has a complete packet, initiate to write bag application (ch_wr_req) to multichannel bursty data cache management circuit immediately, and wait for multichannel bursty data combined arbitration device write mandate (ch_wr_gnt), when write data requests useful signal (ch_wdata_req) arrives, the packet write control circuit reads the complete data packet content of ping-pong buffer, and the value in itself and this length of data package information (pkt_length_reg) is combined into new data flow cache in the sheet External Registers in the corresponding cache district; Row address under the write operation (ch_wr_col_adr) writes in the sheet External Registers behind its corresponding cache district a complete data packet, adds 1 automatically, points to the position that next packet will write; The abort signal (ch_wr_term) of writing of packet is to be produced by the burst number of times in more current column address (col_adr) and the whole packet length (pkt_length_reg) by the burst management circuit in the multichannel bursty data cache management circuit.
(4) multichannel bursty data arbitration management.
With reference to the accompanying drawings 8, concrete treatment scheme in this process is: whether the detection in real time under the clock period of multichannel bursty data combined arbitration device has passage (reading or writing) request (chx_req), and according to the quantity of current channel request, decision adopts circular priority (the channel request number is greater than 1) or fixed priority (having only single request) mode to realize the poll of asking and the mandate (chx_gnt) of passage, the passage of authorizing by the read-write arbitration, generates read operation mandate (chx_rd_gnt) or write operation mandate (chx_wr_gnt) again.Select data, row address, burst number of times, the control signal of institute's authorised channel correspondence simultaneously according to the result of arbitration, the selection of the data of authorised channel, row address, burst number of times, control signal is by reading to hold/write end address and data selector to finish; When corresponding passage buffer storage district writes a complete data packet, corresponding package counting facility adds 1 automatically in the buffer state management circuit, when when corresponding passage buffer storage district reads a complete data packet, corresponding package counting facility subtracts 1 automatically in the buffer state management circuit; When the package counting facility value surpasses max-thresholds or minimum threshold, with the full or dummy status signal of buffer area that produces respective channel.
(5) read data application.
With reference to the accompanying drawings 9, concrete treatment scheme in this process is: data read whether control circuit detection transmission buffer zone is empty, detect whether non-NULL of the outer buffer area of corresponding sheet again, then send then and read bag application (ch_rd_req) to multichannel bursty data cache management circuit, and the read authority (ch_rd_gnt) of wait multichannel bursty data combined arbitration device, when reading of data useful signal (ch_rdata_valid) is effective, isolate packet content and data length information, data length is recorded in the length information register (pkt_length_info), and data content is written to chronologically and sends in the buffer zone.After a complete data packet was read, the row address under the read operation (ch_rd_col_adr) added 1 automatically, pointed to the next packet position that will read.The abort signal (ch_rd_term) of reading of packet relatively produces by burst number of times in the length information register (pkt_length_info) and when top address (col_adr).The concrete visible accompanying drawing 9 of treatment scheme.
(6) send data processing.
With reference to the accompanying drawings 10, the concrete treatment scheme in this process is: packet buffering and transtation mission circuit detect and send buffer zone whether complete packet is arranged, and send to extraneous output terminal after the reading of data with the byte form from send buffer zone then.In the process of transmitting, byte number (tx_bytes) with the record transmission, and compare with current data packet length information (pkt_length_info), whether the specified data bag sends, after being sent completely, send byte number and current data packet length information and all be cleared, wait for reading and sending of next packet.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. the system based on the realization multichannel bursty data service buffer of FPGA is characterized in that, this system comprises sheet External Registers that is used for buffer memory multichannel bursty data and the fpga chip that the RAM resource is provided; Described fpga chip comprises: the outer cache controller of sheet, multichannel bursty data cache management circuit, and the packet reception consistent with the data channel number and buffer circuit, packet write control circuit, packet buffering and transtation mission circuit, packet are read control circuit; Wherein,
Described packet receives and buffer circuit, its input end receives extraneous bursty data input, output terminal and is connected with the packet write control circuit, comprise packet reception control circuit and send buffer, be used for receiving the bursty data of extraneous input and it being write send buffer when empty at send buffer, and when writing complete packet the whole bag of set zone bit;
Described packet write control circuit, its input end receives with packet and buffer circuit is connected, output terminal is connected with multichannel bursty data cache management circuit, be used for being set and the buffer area of chip external memory respective channel when being non-full state at described whole bag zone bit, under the also authorized situation of multichannel burst packet cache management circuit application, read packet complete in the send buffer and itself and its length information is combined in the buffer area of new data flow cache respective channel in the chip external memory, generate the row address information of next write operation simultaneously;
Described packet buffering and transtation mission circuit, its input end read with packet that control circuit is connected, output terminal is connected with extraneous port, comprise sending buffer zone and packet sending controling circuit, are used to cushion complete packet and send it to extraneous port;
Described packet is read control circuit, its input end is connected with multichannel bursty data cache management circuit, output terminal is connected with packet buffering and transtation mission circuit, when the buffer area that is used for sending buffer zone and is sky and chip external memory respective channel is non-dummy status, after under the also authorized situation of multichannel burst packet cache management circuit application, from chip external memory, reading complete packet in the buffer area of respective channel, write in the transmission buffer zone, generate the row address information of next read operation simultaneously;
Described multichannel burst packet cache management circuit, be connected to multichannel data bag write control circuit and packet respectively and read control circuit, and be connected with the outer cache controller of sheet, be used for receive the multichannel bursty data read to wrap apply for/write when application bag the bursty data passage that sends application is arbitrated and authorize, the concrete read operation/write operation of channel grant to authorizing again, generate the column address information of current read/write operation, write the data packet the sheet External Registers or packet is read out from the sheet External Registers;
Described outer cache controller is connected between multichannel burst packet cache management circuit and the sheet External Registers, is used for the sheet External Registers is controlled.
2. the system of the realization multichannel bursty data service buffer based on FPGA as claimed in claim 1, it is characterized in that described multichannel bursty data cache management circuit comprises: multichannel bursty data combined arbitration device, read-write arbitration circuit, burst management circuit, cache user interface, buffer state management circuit, write end data and address selector, read end data and address selector, read authority control circuit, write the authorization control circuit; Wherein,
Described multichannel bursty data combined arbitration device, be used for mode that single channel request adopts fixed priority is only arranged or greater than the mode that adopted circular priority at 1 o'clock each bursty data passage being arbitrated and being authorized in the quantity of current channel request current, and the bursty data channel information of authorizing offered the read-write arbitration circuit, authorize concrete read operation or write operation by it;
Described burst management circuit is used for generating the column address of the sheet External Registers of current operation in read operation or write operation process, finishes the conversion of sheet External Registers address and the interface signal of the outer cache controller of generation sheet in view of the above by the cache user interface simultaneously;
Described buffer state management circuit, comprise a N consistent package counting facility with the bursty data port number, be used for the sheet External Registers is carried out real-time statistics respectively corresponding to the number of the packet in each bursty data passage buffer storage district, road, the package counting facility value of every road correspondence during greater than max-thresholds/less than minimum threshold corresponding write authorization control circuit/read authority control circuit and the packet write control circuit/packet of notice read its corresponding cache region of control circuit and be full state/dummy status, multichannel bursty data combined arbitration device will be in view of the above state packet write control circuit/packet of ending the response respective channel read writing of control circuit and wrap/read the bag application, the packet write control circuit/packet of respective channel is read control circuit simultaneously will expire state/dummy status in view of the above and end to send to write and wrap/read bag application.
Describedly write end data and address selector/read end data and address selector are used for selecting according to the arbitration result of multichannel bursty data combined arbitration device institute's authorised channel when write operation/read operation corresponding packet and row address.
3. the system of the realization multichannel bursty data service buffer based on FPGA as claimed in claim 1 or 2 is characterized in that described send buffer is made up of the ram in slice storer with ping-pong work of 2 dual-ports; Described transmission buffer zone is made up of the ram in slice storer of 1 dual-port.
4. the system of the realization multichannel bursty data service buffer based on FPGA as claimed in claim 3 is characterized in that,
It is 8 that the address wire of the write port of the ram in slice storer of described composition send buffer has 11, input data width, and it is 64 that the address wire of read port has 8, output data width;
It is 64 that the address wire of write port that described composition sends the ram in slice storer of buffer zone has 8, write data width, and it is 8 that the address wire of read port has 11, read data width.
5. the system of the realization multichannel bursty data service buffer based on FPGA as claimed in claim 1 is characterized in that described External Registers is made up of 2 16 chip external memory.
6. as the system of claim 1 or 5 described realization multichannel bursty data service buffers based on FPGA, it is characterized in that, described chip external memory is divided into the storage block of a plurality of same capability sizes, and wherein continuous a plurality of storage blocks are formed buffer area and distributed to each road bursty data passage.
7. the system of the realization multichannel bursty data service buffer based on FPGA as claimed in claim 6 is characterized in that described chip external memory is divided into the storage block of a plurality of 2048 byte-sized.
8. method of the realization multichannel bursty data service buffer of system according to claim 1, it is characterized in that this method comprises: receive the step of data processing, the step of write data application, the step of multichannel bursty data arbitration management, the step of read data application and the step that sends data processing; Wherein,
The step of described reception data processing comprises: bursty data when input arranged in the external world, judge that whether send buffer is whether the buffer area of respective channel in sky and the sheet External Registers is non-full, if not, then abandons the packet of current input; If, then this packet is write in the send buffer by byte, add up the byte number of this packet simultaneously, and when receiving a complete packet the whole bag of set zone bit;
The step of write data application comprises: inquire about the whole bag zone bit in the send buffer in real time, when detecting set, initiate to write the bag application to multichannel burst packet cache management circuit, and by application and when authorized, read packet content complete in the send buffer and with its and this length of data package message block synthesize new data flow cache in the chip external memory corresponding in this bursty data passage buffer storage district;
The step of described multichannel bursty data arbitration management comprises: inquire about the read of each paths in real time, carry out earlier the arbitration of request and the mandate of passage are read and write arbitration to the passage of authorizing again, generate read operation mandate or write operation mandate;
The step of described read data application comprises: whether the buffer area that detect to send buffer zone and whether be respective channel in sky and the sheet External Registers non-NULL, if, then initiate to read the bag application to multichannel burst packet cache management circuit, and by application and when authorized, from the sheet External Registers, read complete packet in the buffer area of respective channel and from wherein isolating packet content and data length information, the record data length information writes packet content in the transmission buffer zone;
The step of described transmission data processing comprises: detect to send in the buffer zone whether complete packet is arranged, then read data packet and send it to extraneous output terminal from send buffer zone.
9. the method for realization multichannel bursty data service buffer as claimed in claim 8, it is characterized in that, in the step of described multichannel bursty data arbitration management, according to the quantity of current channel request, adopt the mode of circular priority or fixed priority to realize to the arbitration of request and the mandate of passage.
10. the method for realization multichannel bursty data service buffer as claimed in claim 9 is characterized in that,
If current only have a single channel request, then adopt the mode of fixed priority to realize to the arbitration of request and the mandate of passage;
If the quantity of current channel request greater than 1, then adopts the mode of circular priority to realize the arbitration of request and the mandate of passage.
11. the method as the described realization multichannel of the arbitrary claim of claim 8 to 10 bursty data service buffer is characterized in that this method also comprises the step of system initialization, this step further comprises:
Behind the electrification reset, system carries out initialization procedure immediately, row, column address zero clearing with each passage in the fpga chip, package counting facility, length counter zero clearing in the buffer state management, RAM read/write address, the whole zero clearings of passage read-write requests, each buffer zone, buffer area are made as dummy status, and each road buffer area pipeline depth is set, and each steering logic of inside is located at idle condition.
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