CN102750244B - Transmitting device and transmitting method of graded buffer direct memory access (DMA) - Google Patents
Transmitting device and transmitting method of graded buffer direct memory access (DMA) Download PDFInfo
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- 239000000872 buffer Substances 0.000 title claims abstract description 161
- 238000000034 method Methods 0.000 title claims abstract description 31
- 230000002093 peripheral effect Effects 0.000 claims abstract description 98
- 230000003139 buffering effect Effects 0.000 claims description 28
- 230000004044 response Effects 0.000 claims description 23
- 230000008569 process Effects 0.000 claims description 20
- 238000013459 approach Methods 0.000 claims description 11
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- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
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Abstract
The invention is suitable for the field of chip design, and particularly discloses a transmitting device and a transmitting method of graded buffer direct memory access (DMA). When a large amount of data is transmitted to a memory controller, a design method of a direct memory access primary storage control circuit is provided. An uploaded DMA buffer is divided into a large primary buffer and a small front buffer, the primary buffer adopts a single-port memory, and therefore chip area is reduced greatly while transmission stability of data between balanced double data rate (DDR) and a peripheral device is guaranteed.
Description
Technical field
The present invention relates to chip design field, particularly relate to DMA (Direct Memery Access, the direct memory access) read/writing control method from mass data to DDR (Double Data Rate synchronous dynamic data-carrier store), the Apparatus and system that transmit.
Background technology
In a chip design, there is the mutual process of mass data in the real-time peripheral hardware and the chip system main memory DDR that are usually directed to a big data quantity.Due to peripheral hardware passivity and the constancy to demand data, with DDR main memory feedback information can not exact controllability, often a large FIFO (First Input First Output is used in a chip design, first-in first-out) chip by peripheral data and DDR response between keep apart, and in order to level and smooth DDR respond sudden, ensure peripheral data transmission harmony.
Existing method often adopts full asynchronous design, asynchronous data read/writing control method adopts asynchronous first-in first-out mode to realize usually, namely by dual port random access storer (Random Access Memory, RAM) after Gray code conversion is carried out in address, judge the full state of the sky of FIFO by the distance of adjudicating address, and it can be used as the handshake of cross clock domain.Said method well can process cross clock domain isolation, is applicable to the situation of fixed-direction data in enormous quantities transmission, particularly the main selection of full asynchronous process.But along with chip DDR control end competition complexity increase time, the data that DDR feeds back are very uneven, and FIFO needs therefore for isolating peripheral hardware and DDR are very large, could the constancy of the sudden and peripheral equipment requirement of level and smooth DDR end well.
RAM generally has twoport and single port two kinds: the RAM of twoport can carry out read operation and write operation simultaneously, shares a slice region of memory, in the content of a port write, can read out in the address that another port is identical; And the RAM of single port only has a set of read/write address, some moment can only complete operation to RAM by an equipment, but area only has the half of the RAM of twoport.
When there is synchronized relation in peripheral clock and DDR control clock, if adopt the method for time-sharing multiplex (TimeDvision Multiplex Accesss), the dual port RAM of this bulk is replaced to single port RAM, become one of chip design acreage reduction important means, and the starting point of invention is provided in the transmission of DMA data exactly, the solution encountered problems with single port RAM replacement dual port RAM.
Summary of the invention
In view of this, the object of the embodiment of the present invention is that providing a kind of replaces to single port memory (Spram by DMA two ports FIFO (twoport FIFO), single port RAM) method for designing and the method for designing of corresponding steering logic, be intended to ensure balance DDR and peripheral hardware between data transmit stable while, reduce chip area as far as possible.
For solving above technical matters, the technical scheme that the embodiment of the present invention provides is: a kind of DMA conveyer of classification buffering, comprise some peripheral hardware ends, a main control end, a DMA single port host buffer and a host buffer controller and a front buffer and a front buffer controller, wherein:
Described peripheral hardware end, for directive sending/reception request msg evenly;
Described main control end, for the sending/receiving request of the formula response peripheral hardware end that bursts out, completes after response in finite time;
Described single port host buffer, under the scheduling of described host buffer controller, at the uniform velocity request of data and the main control end contradiction of bursting out between formula process of level and smooth peripheral hardware end, when normal operating condition, described peripheral hardware end directly can access described single port host buffer; When data volume reaches pre-set threshold value in described single port host buffer, start the DMA request of access to described main control end by described host buffer controller;
Described front buffer, under the scheduling of described front buffer controller, when the DMA for responding described peripheral hardware end in described main control end asks, starts the request of data that described front buffer receives described peripheral hardware end to send.
More preferably, described front buffer can complete in described main control end and respond the gap location of accessing described single port host buffer with described peripheral hardware end to the DMA request of described peripheral hardware end, the content of described front buffer is progressively moved in described single port main buffering region, is merged into a complete data volume.
More preferably, the partial data in described single port host buffer when the request of peripheral hardware end is read request, before described peripheral hardware end initiates DMA request, can be moved in described front buffer by described single port host buffer in advance.
More preferably, described front buffer is single port RAM.
More preferably, described front buffer is dual port RAM.
The DMA transfer approach that the embodiment of the present invention also provides a kind of classification to cushion, comprising:
Peripheral hardware end directive sending evenly/reception request msg;
Main control end bursts out the sending/receiving request of formula response peripheral hardware end, completes after response in finite time;
Single port host buffer under the scheduling of host buffer controller, at the uniform velocity request of data and the main control end contradiction of bursting out between formula process of level and smooth peripheral hardware end, wherein: when normal operating condition, peripheral hardware end directly accesses single port host buffer; When in single port host buffer, data volume reaches pre-set threshold value, host buffer controller starts the DMA request of access to main control end;
Front buffer, under the scheduling of front buffer controller, when main control end responds the DMA request of described peripheral hardware end, starts the request of data that front buffer receives peripheral hardware end to send.
More preferably, front buffer completes the gap location of the DMA of peripheral hardware end request response and peripheral hardware end being accessed to single port host buffer in main control end, the content of front buffer progressively moved in single port main buffering region, is merged into a complete data volume.
More preferably, the partial data in single port host buffer, when the request of peripheral hardware end is read request, before peripheral hardware end initiates DMA request, is moved in front buffer by single port host buffer in advance.
More preferably, according to peripheral hardware end, at the uniform velocity request of data and main control end burst out the access degree of depth of the contradiction peak value determination single port host buffer between formula process.
More preferably, burst out according to main control end the access degree of depth of formula response time, peripheral hardware end request data quantity summation and the peak value determination front buffer of the ratio of peripheral hardware end data access frequency.
Compared with prior art, embodiments provide a kind of mass data when transmitting toward Memory Controller Hub, a kind of method for designing of dma control circuit, by splitting into large host buffer and very little front buffer by uploading DMA buffering buffer, host buffer single port memory, significantly reduced chip area, and ensured the stable of data transmission between balance DDR and peripheral hardware.
Accompanying drawing explanation
Fig. 1 is the control signal schematic diagram of existing DMA conveyer;
Fig. 2 is the theory diagram of DMA conveyer one embodiment of classification of the present invention buffering;
Fig. 3 is the control signal schematic diagram in Fig. 2;
Fig. 4 is the sequential chart of DMA transfer approach one embodiment of classification of the present invention buffering.
Embodiment
Core of the present invention splits into host buffer and very little front buffer by uploading DMA buffer (buffering), host buffer with single port memory (storer), thus be able to data between guarantee balance DDR and peripheral hardware transmit stable while significantly reduce chip area.
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
See Fig. 1, be the control signal schematic diagram of existing DMA conveyer, the DDR of its main control end is owing to being multiple threads, always be in busy condition, CPU is accessed to the request of DDR or miscellaneous equipment access DDR, can not be corresponding in time, but once response, in finite time, complete request process.In order to level and smooth DDR respond sudden, ensure peripheral data transmission harmony, be provided with large twoport DMA buffer, thus chip area is larger.
In the program, twoport DMA buffe relates to Read_clk (reading clock), Read_en (reading enable), Read_addr (reading address), Read_data (read data), and the control signal such as Write_clk (writing clock), Write_en (writing enable), Write_addr (write address), Write_data (writing data), they are by buffer control unit (scheming not shown) United Dispatching, and the frequency of read signal is greater than the frequency (Freq_rclk > Freq_wclk) of write signal.
Different with it, the present invention splits into very large host buffer and very little front buffer by uploading DMA buffer, wherein host buffer single port memory, thus effectively can reduce chip area.
See Fig. 2, indicate an embodiment of the DMA conveyer of classification of the present invention buffering.This DMA being used for big data quantity transmission sends and control device embodiment realizes like this, it mainly comprises following components: peripheral hardware end 200 is initiated/received to data at the uniform velocity, the part such as the formula that bursts out data reception/transmission main control end 400, DMA single port host buffer 200 and host buffer controller 100, front buffer 500 and front buffer controller 600, wherein:
Peripheral hardware end 200 is initiated/received to data at the uniform velocity, and orientation sends/request msg to main control end 400 endlessly.Because peripheral hardware end 200 compares main control end 400 speed more at the uniform velocity to initiate request of data, and main control end 400 is always in busy condition owing to being multiple threads, therefore can not respond in time the request of certain peripheral hardware, but once response, in finite time, complete the request process to peripheral hardware end 200.
For this reason, single port host buffer 300 (single port RAM, spram) is then used for the contradiction of process of bursting out of the at the uniform velocity request of data of level and smooth peripheral hardware and master control.The access degree of depth of the spram of this single port host buffer 300, according in reality between peripheral hardware and master control the peak value of contradiction select.
Single port host buffer 300 works under host buffer controller 100 is dispatched, its steering logic is: when normally running, or when the read-write control signal of single port host buffer 300 is not shared by the master control of bursting out, peripheral hardware end 200 has the direct access right to single port host buffer 300; When the data volume in single port host buffer 300 reaches the threshold value of certain setting, DMA host buffer controller 100 starts the DMA request of access to main control end 400.
When main control end 400 responds the DMA request of peripheral hardware end, the access rights of the spram of single port host buffer 300 will be occupied completely.And the loss of data now in order to prevent external unit from sending/asking, start the request of data that front buffer 500 is sent for receiving peripheral hardware end 200.
When main control end 400 completes the DMA request response to peripheral hardware end 200, peripheral hardware end 200 recovers to weigh the access control of the spram of host buffer 300, but because peripheral hardware end 200 also has partial data request to be deposited with in front buffer 500, therefore the gap location of spram is accessed at peripheral hardware end 200, the content of front buffer 500 will progressively move single port host buffer 200, be merged into a complete data volume.
When peripheral hardware end 200 request of data is read request, before peripheral hardware end 200 initiates DMA request, by the data of single port host buffer 300 part, move in front buffer 500 in advance, when can ensure that main control end 400 pairs of single port host buffers 300 are accessed, be supplied to peripheral data by front buffer 500.
The degree of depth in front buffer district 500 by master control burst out the formula response time, peripheral hardware request the summation of data volume determine with the peak value of peripheral data access frequency ratio.And front buffer 500 is very little due to the degree of depth, no matter adopt single port RAM or dual port RAM can.And use dual port RAM can simplify the steering logic of front buffer 500, but not very large to area effect.
See Fig. 3, for in scheme shown in Fig. 2, single port DMA buffe relates to control signal, comprise Write_bus (write bus), CLK (clock), Wen (writing enable), Wdata (writing data), Waddr (write address) etc., they are by host buffer controller 100 United Dispatching.Similarly, the frequency of read signal is greater than the frequency (Freq_rclk > Freq_wclk) of write signal.
Two paths are related to: Article 1 represents " DDR does not access big DMA buffer ", and namely peripheral hardware directly can be write and lead in big buffer in Fig. 3; The upper left corner in Article 2 path is provided with one " not gate ", represents " DDR is just accessing big DMA buffe ", and namely peripheral hardware must be write front buffer and gets on, and this is key point of the present invention.
On aforementioned base, below the DMA transfer approach of classification buffering of the present invention is described.
See Fig. 4, represent the sequential of the DMA transfer approach that classification of the present invention cushions, its detailed process is:
Peripheral hardware end directive sending evenly/reception request msg (process 1);
When main control end is nonbusy condition, main control end bursts out the sending/receiving request of formula response peripheral hardware end, completes (process 6) after response in finite time;
When main control end is busy condition, single port host buffer under the scheduling of host buffer controller, at the uniform velocity request of data and the main control end contradiction of bursting out between formula process of level and smooth peripheral hardware end, wherein:
When normal operating condition, peripheral hardware end directly accesses single port host buffer (process 3);
When in single port host buffer, data volume reaches pre-set threshold value, host buffer controller starts the DMA request of access (process 5) to main control end;
Front buffer, under the scheduling of front buffer controller, when main control end responds the DMA request of described peripheral hardware end, starts the request of data (process 7) that front buffer receives peripheral hardware end to send.
Meanwhile, front buffer completes the gap location of the DMA of peripheral hardware end request response and peripheral hardware end being accessed to single port host buffer in main control end, the content of front buffer progressively moved in single port main buffering region, is merged into a complete data volume (process 8).
Especially, at single port host buffer when the request of peripheral hardware end is read request, before peripheral hardware end initiates DMA request, the partial data in single port host buffer is moved in front buffer in advance.
In this transfer approach, according to peripheral hardware end, at the uniform velocity request of data and main control end burst out the access degree of depth of the contradiction peak value determination single port host buffer between formula process; Meanwhile, burst out according to main control end the access degree of depth of formula response time, peripheral hardware end request data quantity summation and the peak value determination front buffer of the ratio of peripheral hardware end data access frequency.
Above embodiment, by cushioning buffer split into large host buffer and very little front buffer, host buffer single port memory by uploading DMA, thus is significantly reduced chip area, and ensures stablizing of data transmission between balance DDR and peripheral hardware.
Be below an embody rule example of the present invention, be briefly described below.
Application example
Peripheral hardware terminal is camera (video camera) camera, when recording DV, substantially based on the clock of about 40M, continue to send into image data in DDR, Video coding is carried out again by CPU, be transferred in SD card (safe digital card) and store, lcd screen carries out image preview simultaneously.
Controller and the DDR controller of Camera are operated in same frequency 120M, and just in time 3 cycles send a picture element by camera controller.
Due to lcd screen be endlessly acquisition number according to the show, therefore the DMA priority of LCD is the highest, the DMA of DDR preferential answering LCD request.For improving DMA efficiency, each each equipment DMA application is 256 bytes.
Through the statistical estimation of system, the dma controller of camera need the degree of depth be 2048 data buffering, could devoid of risk ground smoothing system busy time burst work cause the DMA request that cannot respond camera in time.Otherwise easily there is the Writing overflow state of camera data buffering.
Owing to being continuation address access, DDR controller, the data access of each service 256 bytes, needs 54 cycles, adds the expense of control signal, want altogether 60 seeervice cycles.Namely when camera initiates DMA request, it is uncertain what starts to obtain the real response time, but once obtain service response, will complete service at most within 60 cycles, the DDR just Read-write Catrol of release to DMA single port host buffer after completing.
And within these 60 cycles, the data of nearly 20 pixels need buffering, consider that the frequency ratio of DDR controller clock and camera data acquisition clock may change, for the purpose of therefore guarding, the size in front buffer district is 32 pixels.
Time initial, camera every 3 cycles write a pixel (be simplified characterization, think that a pixel is exactly a byte here, only have brightness one road component, colourity two components describe in this literary composition to be ignored) inside big buffer.And now front buffer is in idle condition.
When the write address of big buffer reaches 256, CC (camera controller, camera control unit) starts DMA asks uploading data.Because DDRC (DDR controller, DDR controller) is in busy condition always, when CC obtains DMA request confirmation, the write address of big buffer arrives 280.
After CC obtains DMA request confirmation, the Read-write Catrol power of big buffer is by giving DDRC completely, and now CC latches the write address of big buffer by CC, and starts front buffer district simultaneously.
During DDRC is to the DMA request service of CC, CC continues, toward address 281,282, the address of 283 to write data, and only there is a notional offset address 280 now 0 address in front buffer district, state when namely bigbuffer control is transferred.
When CC is altogether toward 300 address, preposition buffer write road, DDRC completes the DMA services request of CC---and the byte of 256 in big buffer is all read away, and releases the control of big buffer.When CC continues to insert next data in big buffer, the address of filling is 301, increases successively later.
Because CC average 3 cycles insert 1 picture element toward big buffer, therefore in fact big buffer also has the time of 2/3 to be in the free time.The content of 20 picture elements therefore in front buffer, can before CC writes new data on 311 addresses, utilize gap these data to be moved completely the address space of 280 ~ 299 of big buffer, complete after moving, front buffer district enters idle condition again.
When next time, CC initiated new DMA request, address 256 ~ 511 space content in big buffer is continuous content, and similar action goes round and begins again.
Below be only the preferred embodiment of the present invention, it should be pointed out that above-mentioned preferred implementation should not be considered as limitation of the present invention, protection scope of the present invention should be as the criterion with claim limited range.For those skilled in the art, without departing from the spirit and scope of the present invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a DMA conveyer for classification buffering, is characterized in that, comprises some peripheral hardware ends, a main control end, a DMA single port host buffer and a host buffer controller and a front buffer and a front buffer controller, wherein:
Described peripheral hardware end, for directive sending/reception request msg evenly;
Described main control end, for the sending/receiving request of the formula response peripheral hardware end that bursts out, completes after response in finite time;
Described single port host buffer, under the scheduling of described host buffer controller, at the uniform velocity request of data and the main control end contradiction of bursting out between formula process of level and smooth peripheral hardware end, when normal operating condition, described peripheral hardware end directly can access described single port host buffer; When data volume reaches pre-set threshold value in described single port host buffer, start the DMA request of access to described main control end by described host buffer controller;
Described front buffer, under the scheduling of described front buffer controller, when DMA for responding described peripheral hardware end in described main control end asks, start the request of data that described front buffer receives described peripheral hardware end to send, when described main control end responds the DMA request of described peripheral hardware end main control end occupied the access rights of single port buffering.
2. the DMA conveyer of classification buffering as claimed in claim 1, it is characterized in that, described front buffer can complete in described main control end and respond the gap location of accessing described single port host buffer with described peripheral hardware end to the DMA request of described peripheral hardware end, the content of described front buffer is progressively moved in described single port main buffering region, is merged into a complete data volume.
3. the DMA conveyer of classification buffering as claimed in claim 1, it is characterized in that, partial data in described single port host buffer when the request of peripheral hardware end is read request, before described peripheral hardware end initiates DMA request, can be moved in described front buffer by described single port host buffer in advance.
4. the DMA conveyer of the classification buffering as described in claim 1,2 or 3, it is characterized in that, described front buffer is single port RAM.
5. the DMA conveyer of the classification buffering as described in claim 1,2 or 3, it is characterized in that, described front buffer is dual port RAM.
6. a DMA transfer approach for classification buffering, is characterized in that, comprising:
Peripheral hardware end directive sending evenly/reception request msg;
Main control end bursts out the sending/receiving request of formula response peripheral hardware end, completes after response in finite time;
Single port host buffer under the scheduling of host buffer controller, at the uniform velocity request of data and the main control end contradiction of bursting out between formula process of level and smooth peripheral hardware end, wherein: when normal operating condition, peripheral hardware end directly accesses single port host buffer; When in single port host buffer, data volume reaches pre-set threshold value, host buffer controller starts the DMA request of access to main control end;
Front buffer is under the scheduling of front buffer controller, when main control end responds the DMA request of described peripheral hardware end, start the request of data that front buffer receives peripheral hardware end to send, when described main control end responds the DMA request of described peripheral hardware end, main control end is occupied the access rights of single port buffering.
7. the DMA transfer approach of classification buffering as claimed in claim 6, it is characterized in that, front buffer completes in main control end asks response and peripheral hardware end to access the gap location of single port host buffer to the DMA of peripheral hardware end, the content of front buffer is progressively moved in single port main buffering region, is merged into a complete data volume.
8. the DMA transfer approach of classification buffering as claimed in claim 6, is characterized in that, the partial data in single port host buffer, when the request of peripheral hardware end is read request, before peripheral hardware end initiates DMA request, is moved in front buffer by single port host buffer in advance.
9. the DMA transfer approach of the classification buffering as described in claim 6,7 or 8, is characterized in that, according to peripheral hardware end, at the uniform velocity request of data and main control end burst out the access degree of depth of the contradiction peak value determination single port host buffer between formula process.
10. the DMA transfer approach of the classification buffering as described in claim 6,7 or 8, is characterized in that, the access degree of depth of burst out according to main control end formula response time, peripheral hardware end request data quantity summation and the peak value determination front buffer of the ratio of peripheral hardware end data access frequency.
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| CN108984148B (en) * | 2018-06-13 | 2020-11-06 | 浙江芯昇电子技术有限公司 | Data storage method based on synchronous FIFO memory and memory |
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