CN102566958B - Image segmentation processing device based on SGDMA (scatter gather direct memory access) - Google Patents
Image segmentation processing device based on SGDMA (scatter gather direct memory access) Download PDFInfo
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Abstract
The invention discloses an image segmentation processing device based on SGDMA (scatter gather direct memory access). The image segmentation processing device comprises a DMA (direct memory access) controller, an external memory connected to the DMA controller, a video memory/an internal memory connected to the DMA controller through a bus, and GPUs (graphic processing units) connected to the video memory/the internal memory; and in addition, the image segmentation processing device further comprises an image segmentation controller, which is connected between the DMA controller and the external memory and used for segmenting data of an entire image in the external memory into blocks in advance; then the blocks are transmitted to the video memory/the internal memory by the DMA controller and further undertake the follow-up processing by the GPUs. According to the image segmentation processing device disclosed by the invention, the data of the image is segmented before DMA transmission, and the special data is only transmitted to each GPU, so that the bandwidth utilization rates of the bus and the external memory can be improved.
Description
Technical field
The present invention relates to digital image processing techniques, particularly relate to a kind of Iamge Segmentation treating apparatus based on SGDMA, it is specially adapted to large-scale digital jointing display wall field.
Background technology
DMA (Direct Memory Access, direct memory access) be a kind of ideal style of high speed data transfer, data are directly transmitted by dma mode between internal memory and I/O equipment, its data manipulation is completed by dma controller and does not need the participation of more CPU, thus greatly increases the utilization factor of CPU.
DMA has two kinds of implementations: one is Bulk transport formula DMA (block DMA) mode; Another kind is SGDMA (Scatter Gather DMA, dispersin polymerization formula DMA) mode, can by the data-moving of discontinuous storage to continuation address space, otherwise good.
DMA transmits in the process of data and usually requires that source physical address and target physical address are continuous print, but there will be source physical address and the discontinuous situation of target physical address in some applications, then DMA transmits to be divided into and repeatedly completes.For this kind of application, SGDMA mode describes the discontinuous storer of physics by a DMA chained list.After dma controller transfers one piece of physics continuous print data, transmit next block physics continuous print data according to DMA chained list, finally initiate once to interrupt.
At present, DMA is used widely.Such as, in image processing field, existing image processing process is roughly as follows: acquisition of image data, with dma mode by PCIE (Peripheral Component Interconnection Express, peripheral component interconnection is expanded) view data collected is sent to video memory or internal memory by bus, then GPU (Graphic Processing Unit, graphic process unit) or CPU is utilized to process view data.
For large-scale digital jointing display wall field, then need multiple GPU to process a secondary complete image, each GPU only needs the small block data processed wherein simultaneously.Therefore, image Segmentation Technology seems particularly important in this case, is summarized as follows.
Referring to Fig. 1, is the schematic diagram of conventional images dividing processing device.This Iamge Segmentation treating apparatus comprises: data acquisition unit 101, for gathering the decoded view data of video decoding chip 100, and is stored in external memory storage 104 by the view data of collection; Dma controller 102, for the image data transmission that will be stored in external memory storage 104 in video memory/internal memory 105; CPU 107, can be stored in external memory storage 104 or video memory/internal memory 105 by DMA chained list (specific constructive form refers to Fig. 2); GPU 108, is used as image procossing, wherein comprises image segmentating device 106, for realizing the segmentation to image.
As shown in Figure 1, owing to there being multiple unit can carry out read-write operation to external memory storage 104, therefore, in order to avoid producing conflict, the operation of these different units to external memory storage 104 can be controlled by carrying device 103 second month in a season.Specifically, when data acquisition unit 101 and dma controller 102 pairs of external memory storages 104 carry out read-write operation, by moderator 103 for distributing the control of read-write operation.Such as, if data acquisition unit 101 externally storer 104 initiate read-write requests, and dma controller 102 does not initiate read-write requests, and now the Read-write Catrol of external memory storage 104 power is distributed to data acquisition unit 101 by moderator 103; If data acquisition unit 101 and dma controller 102 initiate read-write requests simultaneously, now read-write controller power preferentially can be distributed to dma controller 102 by moderator 103.
It should be noted that, the dma controller 102 in above-mentioned Iamge Segmentation treating apparatus, data acquisition unit 101, moderator 103 can be realized by FPGA (Field Programmable Gate Array, field programmable gate array).
As shown in Figure 2, the exterior storage address of the data that can be transmitted as required by CPU 107 of above-mentioned DMA chained list, size of data and video memory or internal memory the information such as address and generate in advance.As shown in Figure 2, this DMA chained list can be check configuration or loop configuration, comprising data source address and data destination address.Also can comprise the information such as control word and next node pointer further, wherein in control word, comprise data bit width, whether data block size, current block end of transmission (EOT) cause the control informations such as interruption.DMA Bulk transport can be regarded as only containing a node, and next node pointer always points to the hash transmission of present node.
From above, prior art, when dividing processing one secondary complete image, is that an auxiliary image data is intactly sent to each GPU 108 by it simultaneously, is then completed the dividing function of image by GPU 108.The shortcoming of this Iamge Segmentation mode is:
(1) auxiliary image data is intactly sent to each GPU by this dividing method, and in fact just a part of data wherein of needing of each GPU, this causes data in transmitting procedure, need to take the bandwidth of bus, and therefore, this method causes the utilization factor of bandwidth in bus lower;
(2) view data is taken out from external memory storage, and too much invalid data also can reduce the bandwidth availability ratio of external memory storage;
(3) realize function of image segmentation by GPU, add the complexity of GPU programming.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of Iamge Segmentation treating apparatus based on SGDMA, can bandwidth availability ratio be improved.
For solving above technical matters, technical scheme of the present invention is, a kind of Iamge Segmentation treating apparatus based on SGDMA, comprise dma controller, be connected to the external storage of dma controller, be connected to the video memory/internal memory of dma controller by bus, be connected to the GPU of video memory/internal memory, comprise Iamge Segmentation controller, this Iamge Segmentation controller is connected between dma controller and external storage, for in advance the entire image Data Segmentation in external memory storage being become block, be transferred to video memory/internal memory by dma controller afterwards, then carry out subsequent treatment by GPU.
More preferably, comprising data acquisition unit, for gathering entire image data, and being stored in external memory storage.
More preferably, comprise video decoding chip, this video decoding chip is connected with data acquisition unit, for the decoding video signal obtained, exports entire image data to data acquisition unit.
More preferably, comprise moderator, this moderator is connected between data acquisition unit and Iamge Segmentation controller, for distributing data acquisition unit and dma controller to the read-write operation control of external memory storage, when dma controller obtains the read-write operation control to external memory storage, start the entire image data in Iamge Segmentation controller segmentation external memory storage.
More preferably, dma controller, Iamge Segmentation controller, data acquisition unit and moderator are integrated in FPGA.
More preferably, the DMA chained list of entire image is stored in external storage or video memory/internal memory, wherein each DMA chained list node comprises data source address and destination address, so that the view data of data source address is divided into block by Iamge Segmentation controller, after being transferred to video memory/internal memory by dma controller, then carry out subsequent treatment by the GPU that destination address is corresponding.
More preferably, comprising the CPU being connected to dma controller by bus, for transmitting the address information of the exterior storage address of data, size of data and video memory or internal memory as required, generating and storing this DMA chained list in advance.
More preferably, DMA chained list is check configuration or loop configuration.
More preferably, each DMA chained list node comprises control word and next node pointer, wherein comprises data bit width in control word, control information that whether data block size, current block end of transmission (EOT) cause interruption.
More preferably, in each DMA chained list node, next node pointer always points to present node.
Compared with prior art, namely the present invention is split view data before DMA transmission, can obtain and include but are not limited to following beneficial effect:
(1) utilization ratio of bus bandwidth is improved.Namely view data is split before DMA transmission, only transmit particular data to each GPU, instead of transmit complete view data to each GPU, therefore can reduce transmitted data amount, bus bandwidth utilization factor is improved;
(2) bandwidth availability ratio of external memory storage is improved.Namely split view data before DMA transmission, data are with strong points, and the invalid data read from external storage reduces, and this can improve the bandwidth availability ratio of external memory storage undoubtedly.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of conventional images dividing processing device;
Fig. 2 is the data structure diagram of DMA chained list in conventional images division processing method;
Fig. 3 is the schematic diagram of the Iamge Segmentation treating apparatus that the present invention is based on SGDMA.
Embodiment
Core concept of the present invention is, Iamge Segmentation controller is set, namely view data is split before DMA transmission, realize the part image data only transmitting corresponding region to GPU, thus can improve the utilization ratio of bus bandwidth and the bandwidth utilization efficiency of external memory storage.
In order to make those skilled in the art understand technical scheme of the present invention better, below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
See Fig. 3, represent the preferred embodiment that the present invention is based on the Iamge Segmentation treating apparatus of SGDMA.This Iamge Segmentation treating apparatus comprises the elements such as video decoding chip 100, data acquisition unit 101, dma controller 102, Iamge Segmentation controller 303, moderator 103, external memory storage 104, video memory/internal memory 105, GPU 108, CPU 107, wherein: video memory/internal memory 105 and CPU 107 are connected to dma controller 102 by bus, this video memory/internal memory 105 is also connected with GPU; Iamge Segmentation controller 303 is connected to dma controller 102; External storage 104 is by moderator 103 incoming image segmentation controller 303 and data acquisition unit 101, and this data acquisition unit 101 is also connected to video decoding chip 100.Below respectively each main element is described.
Data acquisition unit 101, for gathering the decoded view data of video decoding chip 100, and is stored into the view data of collection in external memory storage 104.
Not only store view picture data image in external memory storage 104, also can store the DMA chained list (this DMA chained list page can be stored in video memory/internal memory 105) of entire image.This DMA chained list can be check configuration or loop configuration, and the information such as address of the exterior storage address of the data generally transmitted as required by CPU 107, size of data and video memory or internal memory generates in advance.Wherein, each node of this DMA chained list comprises: data source address and destination address; Also can comprise the information such as control word and next node pointer further, wherein in this control word, comprise data bit width, whether data block size, current block end of transmission (EOT) cause the control informations such as interruption.Whole DMA Bulk transport then can be regarded as only containing a node, and next node pointer always points to the hash transmission of present node.
Moderator 103, for distributing data acquisition unit and dma controller to the read-write operation control of external memory storage, so just can avoid conflict.Such as, when data acquisition unit 101 externally storer 104 initiate read-write requests and dma controller 102 do not initiate read-write requests time, the Read-write Catrol of external memory storage 104 power is distributed to data acquisition unit 101; When data acquisition unit 101 and dma controller 102 initiate read-write requests simultaneously, preferentially read-write controller power is distributed to dma controller 102, and when dma controller 102 obtains the read-write operation control to external memory storage, Iamge Segmentation controller 303 can be started and split entire image data in external memory storage.
Iamge Segmentation controller 303, for realizing the dividing function of image.This Iamge Segmentation controller 303 is connected between dma controller and external storage, in advance the entire image Data Segmentation in external memory storage can be become block, form target area image data, dma controller 102 only can transmit the part image data of corresponding region to GPU afterwards.
Dma controller 102, obtaining to the Read-write Catrol of external storage 104 temporary, dma controller 102 obtains the view data be stored in external memory storage 104 for Iamge Segmentation controller 303, and after being divided into block to become target area image data, it is transferred in video memory/internal memory 105.
GPU 108, then receive these target area image data in video memory/internal memory 105, and carry out subsequent treatment by predetermined policy, and concrete process then can by prior art process.
CPU 107, can be used for transmitting as required the address information of the exterior storage address of data, size of data and video memory or internal memory, generate and store this DMA chained list in advance in external storage 104 or video memory/internal memory 105, so that dma controller 102 carries out corresponding operating.
It should be noted that, in the present embodiment, dma controller 102, Iamge Segmentation controller 303, data acquisition unit 101 and moderator 103 are more preferably realized by FPGA.
In above embodiment, the advantage of image partition method is: (1) is namely split view data before DMA transmission, only transmit particular data to each GPU, instead of transmit complete view data to each GPU, therefore can reduce transmitted data amount, bus bandwidth utilization factor is improved; (2) namely split view data before DMA transmission, data are with strong points, and the invalid data read from external storage reduces, and this can improve the bandwidth availability ratio of external memory storage undoubtedly.
Below be only the preferred embodiment of the present invention, it should be pointed out that above-mentioned preferred implementation should not be considered as limitation of the present invention, protection scope of the present invention should be as the criterion with claim limited range.For those skilled in the art, without departing from the spirit and scope of the present invention, can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. the Iamge Segmentation treating apparatus based on SGDMA, be applied to large-scale digital jointing display wall field, comprise dma controller, be connected to the external storage of dma controller, video memory/the internal memory of dma controller is connected to by bus, be connected to the GPU of video memory/internal memory, wherein, multiple GPU processes a complete image simultaneously, each GPU only needs a process wherein small block data, it is characterized in that, comprise Iamge Segmentation controller, this Iamge Segmentation controller is connected between dma controller and external storage, for in advance the entire image Data Segmentation in external memory storage being become block, form multiple target area image data, video memory/internal memory is transferred to afterwards by dma controller, subsequent treatment is carried out again by GPU.
2., as claimed in claim 1 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, comprise data acquisition unit, for gathering entire image data, and being stored in external memory storage.
3. as claimed in claim 1 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, comprise video decoding chip, this video decoding chip is connected with data acquisition unit, for to the decoding video signal obtained, export entire image data to data acquisition unit.
4. as claimed in claim 2 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, comprise moderator, this moderator is connected between data acquisition unit and Iamge Segmentation controller, for distributing data acquisition unit and dma controller to the read-write operation control of external memory storage, when dma controller obtains the read-write operation control to external memory storage, start the entire image data in Iamge Segmentation controller segmentation external memory storage.
5., as claimed in claim 4 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, dma controller, Iamge Segmentation controller, data acquisition unit and moderator are integrated in FPGA.
6. the Iamge Segmentation treating apparatus based on SGDMA as described in any one of Claims 1 to 5, it is characterized in that, the DMA chained list of entire image is stored in external storage or video memory/internal memory, wherein each DMA chained list node comprises data source address and destination address, so that the view data of data source address is divided into block by Iamge Segmentation controller, after being transferred to video memory/internal memory by dma controller, then carry out subsequent treatment by the GPU that destination address is corresponding.
7. as claimed in claim 6 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, comprise the CPU being connected to dma controller by bus, for transmitting the address information of the exterior storage address of data, size of data and video memory or internal memory as required, generate and store this DMA chained list in advance.
8., as claimed in claim 6 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, DMA chained list is check configuration or loop configuration.
9. as claimed in claim 6 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, each DMA chained list node comprises control word and next node pointer, wherein comprises data bit width in control word, control information that whether data block size, current block end of transmission (EOT) cause interruption.
10., as claimed in claim 9 based on the Iamge Segmentation treating apparatus of SGDMA, it is characterized in that, in each DMA chained list node, next node pointer always points to present node.
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| CN103021378B (en) * | 2012-12-25 | 2015-09-09 | 广东威创视讯科技股份有限公司 | A kind of device for multi-screen mosaic display and method |
| CN103559157B (en) * | 2013-11-14 | 2016-08-17 | 绵阳市维博电子有限责任公司 | Gather the transmission method of data, Apparatus and system |
| CN105072353B (en) * | 2015-07-16 | 2018-01-16 | 成都新昱科技有限公司 | A kind of image decoding based on more GPU spells prosecutor method |
| CN107124286B (en) * | 2016-02-24 | 2020-05-26 | 深圳市知穹科技有限公司 | System and method for high-speed processing and interaction of mass data |
| CN106933542B (en) * | 2017-03-31 | 2019-06-07 | 中国核动力研究设计院 | A kind of DMA coprocessor and method based on FPGA for nuclear power plant's DCS system |
| CN111262620B (en) * | 2020-04-26 | 2020-07-31 | 武汉卓目科技有限公司 | Test data simulation method and system capable of flexibly customizing frame format |
| CN114785748B (en) * | 2022-06-21 | 2022-09-16 | 苏州领慧立芯科技有限公司 | DMA control system and method for image transmission |
| CN115022076A (en) * | 2022-06-29 | 2022-09-06 | 浪潮电子信息产业股份有限公司 | Data encryption/decryption method, device, system and medium |
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