CN102079502B - MEMS (micro electro mechanical system) device and wafer-level vacuum packaging method thereof - Google Patents
MEMS (micro electro mechanical system) device and wafer-level vacuum packaging method thereof Download PDFInfo
- Publication number
- CN102079502B CN102079502B CN201010571925.3A CN201010571925A CN102079502B CN 102079502 B CN102079502 B CN 102079502B CN 201010571925 A CN201010571925 A CN 201010571925A CN 102079502 B CN102079502 B CN 102079502B
- Authority
- CN
- China
- Prior art keywords
- silicon
- pressure welding
- welding point
- sensitive structure
- structure layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses an MEMS (micro electro mechanical system) device and a wafer-level vacuum packaging method thereof, wherein the MEMS device is composed of a glass substrate (1), a silicon wafer sensitive structure layer with a sealing ring (2), and a silicon cap (9), and the MEMS device is characterized in that at least two silicon islands (11) are arranged in the silicon wafer sensitive structure layer, the bottom of each silicon island (11) is connected with the glass substrate (1) and an electrode lead (8), a press welding spot (6) is respectively arranged on the top of each silicon island (11); parts, corresponding to the silicon islands, on the silicon cap are respectively provided with a press welding spot cavity (7), so that the press welding spots (6) are arranged in the press welding spot cavities (7); and the periphery of each press welding spot cavity is provided with a press welding spot sealing ring (12) which is connected and matched with the top of each silicon island, and the periphery of each press welding spot sealing ring is provided with a press welding spot isolation channel (5). The MEMS device and the wafer-level vacuum packaging method thereof disclosed by the invention have the advantages that the technical problem of electrical isolation between the leakproof structure of the press welding spot and the press welding spots caused by that an electrode is led in the surface of the structural layer of the device from the substrate is avoided, so that the vacuum packaging structure of the MEMS device disclosed by the invention is reasonable in design, simple in process, long in vacuum retention time, reliable in performance and versatile, thereby reducing the cost for vacuum packaging.
Description
Technical field
The invention belongs to micro-electronic mechanical skill field, relate to a kind of MEMS device and MEMS device disc grade vacuum packaging method.
Background technology
MEMS (the abbreviation of Micro Electro Mechanical systems, being microelectromechanical systems) device comprises some moving parts conventionally, these movable members are very fragile, easily be subject to the impact of the factor such as dust, steam in scribing and assembling process, cause the decline of device destruction or overall performance, also have a lot of MEMS devices need to be operated in vacuum environment simultaneously, reduce air damping, improve the quality factor q value of device.As mems accelerometer, gyroscope, micro-resonator, diaphragm pressure sensor, RF MEMS element, vacuum field transmitter and some optical MEMS devices etc.The quality of Vacuum Package has directly determined the performance of this class device, thereby it becomes particularly important.
The Vacuum Package of MEMS device disc grade refers to carries out encapsulation operation taking silicon wafer as unit, between chip and encapsulation, all packaging process such as be connected, and is all that unit operates at silicon wafer, compared with single-chip, has greatly saved the cost of encapsulation.In MEMS wafer-level vacuum package, be mainly to adopt the wafer bonding technology such as anode linkage, silicon-silicon bond close, Au-Si bonding, middle binder bonding (SU-8 glue, BCB glue, glass paste etc.).In corresponding being sealed in of the chip having processed on silicon chip vacuum cavity, make chip operation in vacuum state, be not subject to external influence.The adverse effect that simultaneously can also protect chip not caused by later process (as scribing etc.).
The particularity of MEMS encapsulation has increased difficulty and the cost of MEMS encapsulation greatly, and MEMS packaging cost accounts for 50%～90% of whole MEMS cost, and encapsulation technology becomes the bottleneck of MEMS development.Solve MEMS encapsulation problem is the research emphasis of MEMS technical field always.
MEMS device disc grade vacuum sealing technique, mainly contains the MEMS device of making for surface treatment, often adopts the more of wafer-level vacuum package research that si-glass or silicon-silicon realizes.Adopt in addition the wafer-level vacuum package that glass-silicon bonding body silicon technology is carried out to MEMS device, it mainly contains to adopt in substrate glass back beats the encapsulating structure method of lead hole, but this complex process, cost is high, the vacuum retention time is short.The metal crimp solder joint of device will be distributed on device surface under normal conditions.The method for packing providing as following patent application:
1, the patent No.: 200510102941.7, patent name: wafer-level vacuum encapsulating method.Electrode is on substrate, on the cover board dig through hole, under vacuum environment, in capping, be evenly coated with one deck encapsulating material, make encapsulating material fill up each through hole, for the each through hole of sealing, make the micro-structured component in each space be positioned at a vacuum state, then by encapsulating material slaking, then complete the encapsulation crystal grain of one one single through cutting.
2, the patent No.: 200710121384.2, patent name: a kind of microelectromechanical systems wafer-level vacuum package and flip chip method.Be mainly used in the MEMS device of surface treatment processing, adopt sheet glass block to encapsulate, need not consider electrode draw and electrode between electricity isolation and sealing problem.
3, the patent No.: 200910306690.2, patent name: wafer-level vacuum encapsulation wire interconnecting structure of micro electro mechanical system and manufacture method thereof.On silicon substrate, open hole, through hole and silicon substrate surface have insulating barrier, and metal electrode passes through hole and sealed, and between metal electrode and insulating barrier, has intermediate layer, and cover plate and silicon substrate bonding complete Vacuum Package.
Summary of the invention
Object of the present invention is exactly that the existing shortcoming of opening the encapsulating structure method existence of fairlead from substrate glass back, a kind of MEMS device architecture providing and MEMS device disc grade vacuum packaging method are provided.
To achieve these goals, the present invention has adopted following technical scheme:
A kind of MEMS device, by glass substrate, form with silicon chip sensitive structure layer and the silicon cap of seal ring structure, it is characterized in that: in silicon chip sensitive structure layer, be provided with at least two silicon island according to designed pressure welding point quantity and position, each silicon island and other parts of sensitive structure layer mutually isolate and insulate, below each silicon island, be connected with glass substrate and the electrical leads that is arranged on glass substrate respectively, above each silicon island, be respectively equipped with pressure welding point; On silicon cap, be respectively equipped with three pressure welding point cavitys with each silicon island correspondence position, pressure welding point cavity is arranged with pressure welding point sealing ring outward and above silicon island, is connected cooperation, and pressure welding point sealing ring is arranged with pressure welding point isolation channel outward, makes pressure welding point in pressure welding point cavity.
A kind of MEMS device disc grade vacuum packaging method, is characterized in that comprising the steps:
(1) silicon chip sensitive structure layer anchor point made: utilize photoetching process, ICP to carve silicon technology, produce silicon island, sealing ring and anchor point, and form corresponding shallow slot on silicon chip sensitive structure layer;
(2) on glass substrate, make contact conductor: splash-proofing sputtering metal aluminium on glass substrate, utilize photoetching process photoetching metal lead wire, form contact conductor after corroding unnecessary metal;
(3) silicon-Bo electrostatic bonding: silicon chip sensitive structure layer and glass substrate are aimed at through plasma treatment, dual surface lithography, adopt silicon-Bo static bonding process, completes being connected of silicon chip sensitive structure layer and glass substrate;
(4) on silicon chip sensitive structure layer, make metal electrode pressure welding point: splash-proofing sputtering metal aluminium on silicon chip sensitive structure layer, forms metal electrode pressure welding point through photoetching, quarter after aluminium;
(5) structure discharges: adopt photoetching process, ICP deep etching technique, the shallow slot of the silicon island part of silicon chip sensitive structure layer is carved and led to, and silicon chip sensitive structure is discharged, form movable sensitive structure parts;
(6) making of silicon cap: silicon chip is carried out to high-temperature thermal oxidation, LTO oxidation formation oxide layer, in this oxide layer, deposit layer of gold, adopt photoetching process, etching gold, carve oxide layer, ICP etch silicon, form pressure welding point isolation channel, pressure welding point sealing ring and the pressure welding point cavity corresponding with the shallow slot of silicon chip sensitive structure layer; And the Sensitive Apparatus cavity corresponding with Sensitive Apparatus;
(7) silicon cap and silicon chip sensitive structure layer gold-silicon eutectic bonding: silicon cap is aimed at silicon chip sensitive structure layer dual surface lithography, adopted vacuum gold-silicon eutectic bonding technology, complete the encapsulation of upper silicon cap and silicon chip sensitive structure layer;
(8) etching is exposed pressure welding point: adopt photoetching process, double-sided alignment photoetching, ICP deep etching silicon etch metal crimp solder joint cavity in silicon cap.
The present invention is by structural design and the manufacture of silicon island, sealing ring and lid silicon cap, while solving the MEMS device disc grade Vacuum Package of bulk silicon MEMS technique manufacture, electrode is drawn out to the difficult problem on device architecture top layer or silicon cap plate from glass substrate, has realized interelectrode electricity isolation and the encapsulation of MEMS device disc grade high vacuum.This technical matters is simple, easily realizes, and does not need to add any processing step on the basis of bulk silicon technological, has reduced packaging cost, and dependable performance, meets the requirement of MEMS component vacuum package application.
Key problem in technology of the present invention is the structural design of wafer-level vacuum package, mainly comprises structural design, the structural design of sealing ring and the structural design of silicon cap of silicon island.By these effective structural designs, the distributing again of electrode, electrical isolation and wafer-level vacuum package are realized.
The invention has the advantages that: avoided electrode in prior art to be incorporated into device architecture layer surface from underlay substrate, and arrived while finally blocking a shot Vacuum Package the technical problems such as the electricity isolation between design of Sealing Structure and pressure welding point to pressure welding point.Make that vacuum encapsulation structure of the present invention is reasonable in design, technique is simple, vacuum retention time length, dependable performance, have versatility, has reduced Vacuum Package cost.
Four brief description of the drawings
The present invention has 5 accompanying drawing.
Fig. 1 is MEMS device disc grade encapsulating structure generalized section;
Fig. 2 is silicon island and seal ring structure schematic diagram in silicon chip sensitive structure layer;
Fig. 3 is the planar structure schematic diagram after silicon chip sensitive structure layer and glass substrate silicon-Bo bonding;
Fig. 4 is silicon cap schematic diagram;
Fig. 5-1---Fig. 5-9 are that MEMS device disc grade encapsulating structure is made and encapsulation process technological process generalized section.
detailed description of the invention
One, the structure of MEMS device:
Referring to accompanying drawing 1, a kind of MEMS device provided by the invention, on a slice silicon wafer, produces one group of MEMS device, and each MEMS device is by glass substrate 1, form with silicon chip sensitive structure layer and the silicon cap 9 of sealing ring 2.
(silicon island is according to the corresponding setting of pressure welding point quantity and position in silicon chip sensitive structure layer, to be provided with three silicon island 11, the present embodiment is designed to three silicon island), each silicon island 11 mutually isolates and insulate with other parts of sensitive structure layer, below each silicon island 11, be connected respectively with glass substrate 1 and the electrical leads 8 that is arranged on glass substrate, each silicon island 11 is respectively equipped with pressure welding point 6 above; On silicon cap, be respectively equipped with a pressure welding point cavity 7 with each silicon island correspondence position, pressure welding point cavity is arranged with pressure welding point sealing ring 12 outward and above silicon island, is connected cooperation, pressure welding point sealing ring is arranged with pressure welding point isolation channel 5 outward, makes pressure welding point 6 in pressure welding point cavity 7.
Shown in Fig. 1, Fig. 2, silicon chip sensitive structure layer periphery is that the interior distribution triangular in shape of sealing ring 2, sealing ring 2 arranges three silicon island 11, and silicon island 11 mutually isolates and insulate with other parts of sensitive structure layer.Sealing ring will surround all device architecture parts, ensures that MEMS device is in internal cavities.
Shown in Fig. 1, Fig. 3, be connected with glass substrate 1 and the electrical leads 8 that is arranged on glass substrate respectively below each silicon island 11.The effect of silicon island is by silicon-Bo bonding techniques, and the contact conductor 8 of making on glass substrate is drawn out on device architecture surface, realizes electrical connection and electricity isolation.The structure of silicon island and anchor point are on same lithography mask version.On device architecture layer, silicon island and inner sensitive structure part disconnect.
Shown in Fig. 1, Fig. 4, the structural design of silicon cap 9: on silicon cap, design two kinds of cavitys, the one, the cavity 9a of containment device sensitive structure 10 parts, the 2nd, the cavity 7 of the metal crimp solder joint on containment device structure sheaf, metal crimp solder joint is distributed on silicon island.In design, the cavity structure size of the metal crimp solder joint on containment device structure sheaf is larger than metal crimp solder joint, but less than silicon island size.Surrounded a circle electrically isolating ring 12 outward at each pressure welding point cavity, shading ring 12 is outer is arranged with a circle isolation channel 5 simultaneously, realizes the electricity isolation between pressure welding point.
Two, MEMS device and wafer-level encapsulation method thereof:
A kind of MEMS device disc grade method for packing, is characterized in that comprising the steps:
(1), silicon chip sensitive structure layer anchor point made: as shown in Fig. 5-1, adopt N (100) silicon chip and Pyrex7740 glass and cleaning treatment, utilize photoetching process, ICP to carve silicon technology, on silicon chip sensitive structure layer, produce silicon island 11, sealing ring 2, anchor point 13 and sealing ring 2, and form corresponding isolation channel 5, cavity 9a;
(2), make contact conductor on glass substrate: as shown in Fig. 5-2, splash-proofing sputtering metal aluminium on glass substrate 1, utilizes photoetching process photoetching metal lead wire, form contact conductor 8 after corroding unnecessary metal;
(3), silicon-Bo electrostatic bonding: as shown in Fig. 5-3, silicon chip sensitive structure layer and glass substrate 1 aimed at through plasma treatment, dual surface lithography, adopts silicon-Bo static bonding process, completes being connected of silicon chip sensitive structure layer and glass substrate;
(4), on silicon chip sensitive structure layer, make metal electrode pressure welding point: as shown in Fig. 5-4, splash-proofing sputtering metal aluminium on silicon chip sensitive structure layer, forms metal electrode pressure welding point 6 through photoetching, quarter after aluminium;
(5), structure discharges: as shown in Fig. 5-5, adopt photoetching process, ICP deep etching technique, the isolation channel of the silicon island part of silicon chip sensitive structure layer is carved to the complete pressure welding point isolation channel 5 of logical formation, and silicon chip sensitive structure is discharged, form movable sensitive structure parts 10;
(6), the making of silicon cap:
As shown in Fig. 5-6, carry out high-temperature thermal oxidation, LTO oxidation formation oxide layer 4 to making the silicon chip of silicon cap 9, in this oxide layer, deposit layer of gold 3;
As shown in Fig. 5-7, adopt photoetching process, etching gold, carve oxide layer, ICP etch silicon, form pressure welding point isolation channel 5, pressure welding point sealing ring 12 and the pressure welding point cavity 7 corresponding with silicon chip sensitive structure layer; And the Sensitive Apparatus cavity 9a corresponding with Sensitive Apparatus;
(7), silicon cap and silicon chip sensitive structure layer gold-silicon eutectic bonding: as shown in Fig. 5-8, silicon cap 9 is aimed at silicon chip sensitive structure layer dual surface lithography, adopted vacuum gold-silicon eutectic bonding technology, complete the encapsulation of upper silicon cap and silicon chip sensitive structure layer;
(8) etching is exposed pressure welding point: as shown in Fig. 5-9, adopt photoetching process, double-sided alignment photoetching, ICP deep etching silicon etch metal crimp solder joint cavity 7 in silicon cap 9.
Through above-mentioned production process, realize the wafer-level vacuum package of MEMS device.Upper strata is that silicon cap, intermediate layer are that device architecture part, lower floor are glass, and its structural profile schematic diagram as shown in Figure 1.
Claims (2)
1. a MEMS device, by glass substrate (1), form with silicon chip sensitive structure layer and the silicon cap (9) of sealing ring (2), it is characterized in that: in silicon chip sensitive structure layer, be provided with at least two silicon island (11), each silicon island (11) mutually isolates and insulate with other parts of sensitive structure layer, below each silicon island (11), be connected respectively with glass substrate (1) and the electrical leads (8) that is arranged on glass substrate, each silicon island (11) are respectively equipped with pressure welding point (6) above; On silicon cap, be respectively equipped with a pressure welding point cavity (7) with each silicon island correspondence position, make pressure welding point (6) in pressure welding point cavity (7), pressure welding point cavity is arranged with pressure welding point sealing ring (12) outward and above silicon island, is connected cooperation, and pressure welding point sealing ring is arranged with pressure welding point isolation channel (5) outward.
2. a MEMS device disc grade vacuum packaging method, is characterized in that comprising the steps:
(1) silicon chip sensitive structure layer anchor point made: utilize photoetching process, ICP to carve silicon technology, on silicon chip sensitive structure layer, produce silicon island (11), sealing ring (2) and anchor point (13), and form corresponding Sensitive Apparatus cavity (9a);
(2) on glass substrate, make contact conductor (8): splash-proofing sputtering metal aluminium on glass substrate, utilize photoetching process photoetching metal lead wire, form contact conductor (8) after corroding unnecessary metal;
(3) silicon-Bo electrostatic bonding: silicon chip sensitive structure layer and glass substrate (1) are aimed at through plasma treatment, dual surface lithography, adopts silicon-Bo static bonding process, completes being connected of silicon chip sensitive structure layer and glass substrate;
(4) on silicon chip sensitive structure layer, make metal electrode pressure welding point: splash-proofing sputtering metal aluminium on silicon chip sensitive structure layer, forms metal electrode pressure welding point (6) through photoetching, quarter after aluminium;
(5) structure discharges: adopt photoetching process, ICP deep etching technique, the shallow slot of the silicon island part of silicon chip sensitive structure layer is carved and led to, and silicon chip sensitive structure is discharged, form movable sensitive structure parts (10);
(6) making of silicon cap: silicon chip is carried out to high-temperature thermal oxidation, LTO oxidation forms oxide layer (4), at this oxide layer (4) upper deposition layer of gold (3), adopt photoetching process, etching gold, carve oxide layer, ICP etch silicon, form the pressure welding point isolation channel (5) corresponding with the shallow slot of silicon chip sensitive structure layer, pressure welding point sealing ring (12) and pressure welding point cavity (7), and the Sensitive Apparatus cavity (9a) corresponding with Sensitive Apparatus, wherein, pressure welding point cavity is arranged with pressure welding point sealing ring (12) outward, pressure welding point sealing ring is arranged with pressure welding point isolation channel (5) outward, silicon island and other parts of sensitive structure layer mutually isolate and insulate, below each silicon island, be connected with an electrical leads,
(7) silicon cap and silicon chip sensitive structure layer gold-silicon eutectic bonding: silicon cap is aimed at silicon chip sensitive structure layer dual surface lithography, adopted vacuum gold-silicon eutectic bonding technique, complete the encapsulation of upper silicon cap and silicon chip sensitive structure layer;
(8) etching is exposed pressure welding point: adopt photoetching process, double-sided alignment photoetching, ICP deep etching silicon etch metal crimp solder joint cavity (7) in silicon cap.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010571925.3A CN102079502B (en) | 2010-12-03 | 2010-12-03 | MEMS (micro electro mechanical system) device and wafer-level vacuum packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010571925.3A CN102079502B (en) | 2010-12-03 | 2010-12-03 | MEMS (micro electro mechanical system) device and wafer-level vacuum packaging method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102079502A CN102079502A (en) | 2011-06-01 |
| CN102079502B true CN102079502B (en) | 2014-08-13 |
Family
ID=44085732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010571925.3A Active CN102079502B (en) | 2010-12-03 | 2010-12-03 | MEMS (micro electro mechanical system) device and wafer-level vacuum packaging method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102079502B (en) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270712B (en) * | 2011-07-27 | 2013-07-10 | 东莞市福地电子材料有限公司 | LED (Light-Emitting Diode) vacuum encapsulating device and method |
| CN102367165B (en) * | 2011-08-31 | 2015-01-21 | 华东光电集成器件研究所 | Method for interconnecting electrodes of MEMS (micro electro mechanical system) device based on SOI (silicon-on-insulator) |
| CN102408091B (en) * | 2011-10-10 | 2015-04-15 | 无锡微奥科技有限公司 | Improved wafer level package structure of micro-electro-mechanical system platform |
| CN102358616B (en) * | 2011-11-09 | 2014-04-30 | 中国电子科技集团公司第二十四研究所 | Airtight sintering device of glass tube and MEMS chip |
| CN102556956B (en) * | 2012-03-08 | 2014-06-25 | 中国科学院上海微系统与信息技术研究所 | Vacuum packaging structure of MEMS (Micro Electro Mechanical System) device and manufacture method thereof |
| CN102795593A (en) * | 2012-08-29 | 2012-11-28 | 深迪半导体(上海)有限公司 | Method for processing ultrathin vacuum-sealed MEMS (Micro-electromechanical System) wafer |
| CN102862947B (en) * | 2012-09-18 | 2016-01-27 | 华东光电集成器件研究所 | A kind of MEMS and wafer-level vacuum encapsulating method thereof |
| CN104140072B (en) * | 2013-05-09 | 2016-07-13 | 苏州敏芯微电子技术股份有限公司 | The integrated chip of MEMS and integrated circuit and manufacture method thereof |
| CN103434998B (en) * | 2013-08-29 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | The bubble-tight test structure of wafer scale and method of testing |
| CN103779252B (en) * | 2014-01-23 | 2016-05-04 | 江苏艾特曼电子科技有限公司 | A kind of online detection architecture for wafer level bonding particle contamination |
| KR20150145413A (en) * | 2014-06-19 | 2015-12-30 | 삼성전기주식회사 | Sensor package and manufacturing method thereof |
| CN104355284B (en) * | 2014-10-13 | 2016-06-29 | 华东光电集成器件研究所 | A kind of MEMS is two-sided to logical dielectric isolation structure and preparation method |
| CN105293428B (en) * | 2015-10-19 | 2017-04-19 | 北京航天控制仪器研究所 | Full silicification wafer level vacuum encapsulation method and device for MEMS (Micro-Electro-Mechanical System) device |
| CN107359156B (en) * | 2017-05-31 | 2020-03-17 | 中国电子科技集团公司第十三研究所 | Heterogeneous integrated silicon-based radio frequency microsystem structure and manufacturing method thereof |
| TWI706911B (en) | 2017-06-15 | 2020-10-11 | 聯華電子股份有限公司 | Microelectron-mechanical system device and method for electrostatic bonding the same |
| CN110002396B (en) * | 2019-03-13 | 2021-08-31 | 华中科技大学 | Packaging method of wafer-level three-layer structure |
| US20200385263A1 (en) * | 2019-06-06 | 2020-12-10 | Solid State System Co., Ltd. | Package structure of micro-electro-mechanical-system (mems) microphone package and packaging method thereof |
| CN110683509B (en) * | 2019-08-27 | 2022-12-02 | 华东光电集成器件研究所 | Preparation method of anti-interference MEMS device |
| CN112265956B (en) * | 2020-09-25 | 2023-07-28 | 华东光电集成器件研究所 | MEMS wafer level vacuum packaging method for packaging different vacuum degrees |
| CN113697761B (en) * | 2021-08-25 | 2023-07-07 | 中国电子科技集团公司第四十九研究所 | Resonant pressure sensitive chip probe of isolation packaging structure and packaging method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1891617A (en) * | 2005-07-01 | 2007-01-10 | 北京大学 | Method for protecting etched structure in induction coupling plasma etching |
| KR20070078233A (en) * | 2006-01-26 | 2007-07-31 | 재단법인서울대학교산학협력재단 | Method of packaging of mems device at the vacuum state using a silicide bonding and vacuum packaged mems device using the same |
| CN101108722A (en) * | 2007-09-05 | 2008-01-23 | 北京大学 | Wafer level vacuum encapsulation of microelectron mechanical system and upside-down mounting soldering method thereof |
| EP1886969A2 (en) * | 2006-08-07 | 2008-02-13 | Honeywell Inc. | Methods of fabrication of wafer-level vacuum packaged devices |
| CN101746706A (en) * | 2009-10-16 | 2010-06-23 | 华中科技大学 | Micro-electromechanical system (MEMS) wafer-level vacuum packaging transverse interconnection structure and manufacture method thereof |
| CN101780942A (en) * | 2009-12-11 | 2010-07-21 | 中国电子科技集团公司第十三研究所 | Wafer level vacuum packaging method of MEMS (Micro-electromechanical System) component |
-
2010
- 2010-12-03 CN CN201010571925.3A patent/CN102079502B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1891617A (en) * | 2005-07-01 | 2007-01-10 | 北京大学 | Method for protecting etched structure in induction coupling plasma etching |
| KR20070078233A (en) * | 2006-01-26 | 2007-07-31 | 재단법인서울대학교산학협력재단 | Method of packaging of mems device at the vacuum state using a silicide bonding and vacuum packaged mems device using the same |
| EP1886969A2 (en) * | 2006-08-07 | 2008-02-13 | Honeywell Inc. | Methods of fabrication of wafer-level vacuum packaged devices |
| CN101108722A (en) * | 2007-09-05 | 2008-01-23 | 北京大学 | Wafer level vacuum encapsulation of microelectron mechanical system and upside-down mounting soldering method thereof |
| CN101746706A (en) * | 2009-10-16 | 2010-06-23 | 华中科技大学 | Micro-electromechanical system (MEMS) wafer-level vacuum packaging transverse interconnection structure and manufacture method thereof |
| CN101780942A (en) * | 2009-12-11 | 2010-07-21 | 中国电子科技集团公司第十三研究所 | Wafer level vacuum packaging method of MEMS (Micro-electromechanical System) component |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102079502A (en) | 2011-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102079502B (en) | MEMS (micro electro mechanical system) device and wafer-level vacuum packaging method thereof | |
| CN102556956B (en) | Vacuum packaging structure of MEMS (Micro Electro Mechanical System) device and manufacture method thereof | |
| CN104303262B (en) | For the technique of a portion exposure sealing MEMS device at ambient | |
| US7955885B1 (en) | Methods of forming packaged micro-electromechanical devices | |
| US8748998B2 (en) | Sensor module | |
| US9406747B2 (en) | Component in the form of a wafer level package and method for manufacturing same | |
| CN101554988B (en) | Wafer-grade vacuum encapsulation method for micro-electro-mechanical system | |
| US8217474B2 (en) | Hermetic MEMS device and method for fabricating hermetic MEMS device and package structure of MEMS device | |
| CN103818874B (en) | The method for packing of MEMS structure and treatment circuit integrated system | |
| JP2017504490A (en) | Wafer level hermetic packaging method using vertical feedthrough | |
| CN102759636B (en) | Capacitive micro-electromechanical system (MEMS) accelerometer and manufacturing method thereof | |
| CN102183335A (en) | Mems pressure sensor and manufacturing method thereof | |
| CN101941673B (en) | Micro electro mechanical system wafer-level vacuum packaging method | |
| CN102583219A (en) | Vacuum package structure and vacuum packaging method for wafer-level MEMS (micro-electromechanical system) devices | |
| CN103552980A (en) | Wafer level packaging method for micro electromechanical system (MEMS) chip and single-chip micro-miniature type MEMS chip | |
| CN103832964A (en) | Micro-electro-mechanical system device manufacturing method | |
| US20140332909A1 (en) | Integrated chip with micro-electro-mechanical system and integrated circuit mounted therein and method for manufacturing the same | |
| CN206332654U (en) | The miniaturization acoustic surface wave filter device encapsulating structure being easily integrated | |
| CN202988703U (en) | Micro-electromechanical system device | |
| CN107892268A (en) | Pressure sensor and its manufacture method | |
| CN107445135A (en) | Semiconductor devices and its method for packing | |
| WO2016200346A1 (en) | Hermetic packaging method for soi-mems devices with embedded vertical feedthroughs | |
| US8378433B2 (en) | Semiconductor device with a controlled cavity and method of formation | |
| CN207456650U (en) | Pressure sensor | |
| CN110155934A (en) | A kind of MEMS device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |