WO2016200346A1 - Hermetic packaging method for soi-mems devices with embedded vertical feedthroughs - Google Patents
Hermetic packaging method for soi-mems devices with embedded vertical feedthroughs Download PDFInfo
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- WO2016200346A1 WO2016200346A1 PCT/TR2015/050001 TR2015050001W WO2016200346A1 WO 2016200346 A1 WO2016200346 A1 WO 2016200346A1 TR 2015050001 W TR2015050001 W TR 2015050001W WO 2016200346 A1 WO2016200346 A1 WO 2016200346A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00261—Processes for packaging MEMS devices
- B81C1/00301—Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B2207/00—Microstructural systems or auxiliary parts thereof
- B81B2207/09—Packages
- B81B2207/091—Arrangements for connecting external electrical signals to mechanical structures inside the package
- B81B2207/094—Feed-through, via
- B81B2207/096—Feed-through, via through the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0109—Bonding an individual cap on the substrate
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/03—Bonding two components
- B81C2203/031—Anodic bondings
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/03—Bonding two components
- B81C2203/033—Thermal bonding
- B81C2203/036—Fusion bonding
Abstract
A wafer-level packaging method for SOI-MEMS structures that are desired to be encapsulated in a hermetic cavity with electrical leads to the outside without destroying the hermeticity of the cavity. The MEMS devices and vertical feedthroughs are both fabricated on the same SOI wafer, whereas a glass or silicon wafer is used for capping and routing metallization. The method requires at most five process masks and a single SOI wafer. Compared to the existing packaging technologies it reduces the number of wafers, process masks, and process steps. Conventional wirebonding is sufficient to connect the vertical feedthroughs to the outer world, without a need for conductor-refill inside the via openings. The method is compatible with low-temperature thermo-compression-based bonding/sealing processes and also with the silicon-glass anodic or silicon-silicon fusion bonding processes, which do not require any sealing material for bonding/sealing. The simplified process increase the reliability and yield in addition to lowering the manufacturing costs of hermetically-sealed MEMS components with the present invention.
Description
HERMETI C PACKAGI NG METHOD FOR SOI -MEMS DEVI CES Wl TH EMBEDDED
VERTI CAL FEEDTHROUGHS
Technical Field This invention relates to the field of wafer-level packaging of microstructures as well as vertical feedthroughs formed on a single silicon-on-insulator (SOI ) wafer that need to be encapsulated in a hermetic cavity and having a single or multiple electrical leads on the same wafer to be transferred to the outside of the cavity without destroying the hermeticity of the cavity.
Background of the I nvention (Prior Art) :
Micro-electro-mechanical systems (MEMS) enables the development of state-of- the-art transducers, sensors, actuators, resonators, etc. used in a variety of applications ranging from consumer electronic market towards the automotive and even military electronic products. MEMS products offer the advantages of lower cost, better compatibility with high-volume batch fabrication, smaller space requirement, and higher reliability compared to the conventional electromechanical systems. The core of the MEMS products include precision micromachined electro-mechanical components that transduce physical, chemical, biological, etc. signals to electrical signals. Some of these micromachined components must have a direct physical contact with the outer world, as in the case of the gas flow sensors or pressure sensors. On the other hand, a great variety of the micromachined components, including but not limited to the inertial sensors, resonators, and infrared detectors, must be isolated from the atmosphere of the ambient in which they are operated. This isolation is necessary for both "forming a controlled operating atmosphere for the micromachined component" and "keeping these tiny components safe from the adverse effects of various factors including solid, liquid and/or gas contamination, humidity, and/or pressure variations". Isolation of the micromachined components from the ambient is simply achieved by encapsulating them in hermetically-sealed packages.
The earlier examples of packaging MEMS components achieve hermetic sealing of every fabricated MEMS component individually, which increases the packaging cost due to the increased labor and time as well as reduced the process yield and reliability. An obviously better alternative is to seal the MEMS component at the wafer-level, which reduces the packaging costs significantly by minimizing the labor and time as well as increasing the
process yield and reliability. Wafer-level packaging typically refers to the use of wafer-level MEMS processing techniques to form a capping element (either a layer or a wafer) on top of a sensor wafer that contains the MEMS components to be packaged. This way, all the MEMS components located on a sensor wafer can be encapsulated simultaneously. Encapsulation, however, is just the first half of the packaging process, whereas the second half is nothing but the transfer of the electrically conductive leads of the encapsulated MEMS component to the outer world without degrading the hermeticity of the encapsulation.
There are various methods reported in the prior art for the wafer-level encapsulation of MEMS components including techniques for lead transfer. Well known in the prior art is the use of glass-frit as the sealing material between a cap wafer and a sensor wafer, for which the leads of the encapsulated MEMS component is transferred laterally through the surface of the sensor wafer and creating a step-height below the glass-frit material, which must be sealed properly. Sealing step-heights up to few micrometers with glass-frit material is not a significant problem, since the glass-frit has a thickness typically more than 25μιη after firing. On the other hand, temperatures required for glass-frit bonding exceed 430°C, which may not only limit the number of compatible materials that can be used on the MEMS component but may also result in a high packaging stress. Moreover, glass-frit is a thick-film paste that has the risk of creating free-to-move frit particles inside the encapsulated cavity and contaminating the MEMS components, which may both reduce the packaging yield and long-term reliability. Finally, the hermeticity of the glass-frit is known to be worse compared to metal-based alloys used as sealing materials.
Another method in the prior art is the use of metal-based alloys as the sealing material (Au-l n, Au-Sn, Al-Ge, Si-Au, etc.) . These alloys generally provide better hermeticity compared to the glass-frit as well as require lower process temperatures typically in the range from 200°C to 400°C for various alloy materials and compositions. However, being electrically conductive, these sealing materials do not allow lead transfer through the sealing region, unless an additional insulating layer is used between the leads and the sealing material. Even with this insulating layer, the metal-based sealing material must still be capable of covering the step-height caused by the leads passing under the sealing region, which typically requires a sealing material thickness of a few microns or more. Such a thickness is not desired for metal-alloy based sealing materials due to the increased mechanical stress and also the cost of the thicker metal layers.
I n the other examples of the prior art, the leads are transferred to the outer world using conductive feedthrough patterns that are machined vertically with respect to the
surface of the sensor wafer. This way, a thinner sealing material can be used for sealing the MEMS component since the leads in this case do not cause a step-height under the sealing region as they are transferred to the outer world through a path that does not cross through the sealing region. Still, implementing the vertical feedthroughs increases the complexity and number of steps of the processes used to fabricate either the sensor or the cap wafers, or both. One of the difficulties with the vertical feedthrough processes is to achieve the sealing and the lead transfer in the same step, which requires precise control of the thickness of the sealing material, sensor leads, sealing regions, vertical feedthroughs. Any offsets between some of these parameters may form "a properly encapsulated cavity without a successful lead transfer", or "a successful lead transfer without an encapsulated cavity". Another difficulty with some of the prior art using vertical feedthroughs is the void-free and hermetic filling of the via openings with a conductive material, which will form the vertical feedthroughs.
Another prior art eliminates the above mentioned problems by allowing lead transfer using vertical feedthrough patterns that are formed by well-known MEMS etching processes, without requiring complex via-fill, trench-refill, or similar deposition-based techniques. This method facilitates smart micromachining of an SOI cap wafer, which is then bonded to another wafer containing the microstructures by using either metal-alloy based sealing materials or even by some well-known bonding methods that do not require a sealing material at all. However, this method requires the use of at least two SOI wafers for the fabrication of the cap and device wafers which increases the number of process steps, and therefore the manufacturing costs.
I n summary, it is desirable to develop a simple method that achieves the fabrication of microstructures and vertical feedthroughs simultaneously using a single SOI wafer and without requiring any complex process steps, whereas a single glass or silicon cap wafer would be sufficient for the wafer-level hermetic sealing of these microstructures. A method with the abovementioned features would eliminate the need for using "multiple SOI wafers" during manufacturing wafer-level hermetically sealed microstructures with vertical feedthroughs, and therefore, improve the process simplicity, yield, and reliability besides reducing the fabrication and packaging costs.
Brief Description of the I nvention:
The present invention provides a method of wafer-level hermetic packaging process developed for SOI -MEMS devices, where a single SOI wafer is used for the fabrication of MEMS structures as well as the vertical feedthroughs for the lead transfer, while a glass or
silicon wafer is used for capping and routing metallization. The present invention is compatible with low-temperature bonding/sealing processes as well as requiring no re-fill inside the vertical feedthrough via openings, providing a very easy way of both hermetic sealing and lead transfer. A few embodiments of the present invention are disclosed, some of which providing the advantages of "eliminating the need for a sealing material".
The method described in this invention requires the bonding of two substrates, one of which contains the MEMS component and vertical feedthroughs, and called the sensor substrate. The second substrate is called the capping substrate, and is used for hermetically sealing and also for the lead-transfer of the MEMS components laid on the sensor substrate. The fabrication of the sensor substrate of the present invention requires double-face patterning of a single SOI wafer or a wafer having a similar structure, only by using some straightforward silicon etching and thin-film deposition/ etching techniques. Etching the first face of the sensor wafer simultaneously forms "the MEMS component that will be encapsulated" as well as "the vertical feedthrough patterns that would face the conductive leads of the MEMS component to be encapsulated inside the cavity". Etching the second face of the cap wafer forms the "via openings" that reach to "the surfaces of the vertical feedthrough patterns that would face the outer world". I n different embodiments of the present invention, it is also possible to deposit and pattern metal layers on a single or both faces of the cap wafer, acting either as a sealing material, a getter material, or a wirebonding pad, depending on the deposition site.
The advantages of the method described in the present invention are listed below: a. The present invention utilizes the patterning of both the "microstructures" and "vertical feedthroughs" on the same SOI substrate, eliminating the need for a second SOI wafer for the capping and decreasing the number of process masks and related process steps. b. The present invention eliminates the need for refilling the via openings that reach to the vertical feedthrough patterns fabricated on the SOI substrate. Opening these vias neither causes any harm to the sealing region nor affects the hermeticity of the encapsulated cavity. c. The present invention is compatible with low-temperature thermo-compression- based bonding/sealing (eutectic or transient liquid phase bonding) processes using various sealing materials such as thin-film metals and alloys, and also in some of the embodiments, with the silicon-glass anodic or silicon-silicon fusion
bonding processes, which do not require any sealing material to be deposited on neither the sensor nor the capping substrates for bonding/sealing. d. I n some of the embodiments of the present invention, it is possible to use the metal layer of the capping substrate, which is intentionally laid over the sealing region of the capping substrate, as the sealing material. This eliminates the need for an additional sealing material patterned on the capping or sensor substrate, although a different sealing material can still be used if desired, provided that the sealing material is electrically conductive. e. The present invention allows using submicron-thick sealing materials as the disclosed method ensures no step-height in the sealing region. f. I n one of the embodiments of the present invention, the complete fabrication of a suspended MEMS component encapsulated in a hermetically-sealed cavity requires only four lithography steps. g. The reduced number of process steps and the elimination of complex processes other than the well-known MEMS deposition/ etch/bonding processes increase the reliability and yield as well as lower the cost of manufacturing hermetically-sealed MEMS components with the method of the present invention. h. The present invention is compatible with a conductor-refill process inside the via openings, although this is not the only way to get an electrical contact from the vertical feedthroughs for the present invention. Moreover, the conductor-refill process does not need to fill the via openings hermetically for the present invention, as the refill process does not affect the hermeticity of the sealed cavity for the disclosed packaging method.
Definition of the Figures:
I n order to explain the present invention in more detail, the following figures have been prepared and attached to the description. The list and the definition of the figures are given below. Fl GURES 1 , 2, and 3 describe the three different embodiments of the method presented in this invention, respectively.
FI GURE 1 A shows a first substrate (10), which can be an SOI wafer or a similar wafer, having a via opening (18) formed by etching the second silicon layer of the substrate (16)
Fl GURE 1 B shows the patterning of contact metal (20) inside the via opening (18) in order to get electrical contact by wire bonding after the hermetic sealing;
FI GURE 1 C shows the patterning of the first silicon layer of the substrate (12) in order to form the MEMS component (22) ;
Fl GURE 1 D shows the release of the MEMS component (22) by partial etching of the buried oxide layer (14) of the SOI substrate (10) ; FI GURE 1 E shows a second substrate made of a glass wafer (28) which is patterned to contain a cavity (30) and sealing wall (34) ;
FI GURE 1 F shows the patterning of metal leads of the MEMS component (32) , the sealing material (36), as well as the thin-film getter (56) on the second substrate (28) ;
FI GURE 1 G shows the sealing region (24) of the first substrate (10) bonded to the sealing region (34) of the second substrate (28) with or without using a sealing material and in such a way that the microstructures (22) is completely encapsulated within the enclosed cavity (30)
FI GURE 1 H shows the wirebond (38) connected to the contact metal (20) inside the via opening (18) in order to get electrical contact from the vertical feedthrough (26) ; FI GURE 2A shows a first substrate (10) , with a MEMS component (22) formed on the first silicon layer (12) of the first substrate as well as a sealing wall (24) and vertical feedthrough (26) ;
FI GURE 2B shows the release of the MEMS component (22) by partial etching the buried oxide layer (14) of the SOI substrate (10) ;
FI GURE 2C shows a second substrate (28) , which is identical to the capping substrate of FI GURE 1 F, where having a cavity (30) , metal leads of the sensor (32), thin-film getter (56), and sealing material (36) ;
FI GURE 2D shows the sealing wall (24) of the first substrate (10) anodically or eutectically or transient liquid phase (TLP) bonded to the second substrate (28) with or without using a sealing material (36) and in such a way that the MEMS component (22) is completely encapsulated within the enclosed cavity (30) ;
Fl GURE 2E shows the thinned second silicon layer (40) of the first substrate (10) ;
FI GURE 2F shows the reduced size via opening (42) formed on the thinned second silicon layer (40) of the first substrate (10) ;
FI GURE 2H shows the wirebond (38) connected to the contact metal (20) inside the reduced size via opening (42) in order to get electrical contact from the vertical feedthrough (26) ;
Fl GURE 3A shows a second substrate (44) made from silicon having a cavity (46) ; FI GURE 3B shows a dielectric layer (48) on which metal sensor leads (50) are formed in the cavity (46) and sealing material (52) is formed on the sealing region (54) ;
FI GURE 3C shows the first substrate (10) , which is identical to the sensor substrate of FI GURE 1 D, having the MEMS component (22), vertical feedthrough (26), and sealing wall (24) on the first silicon layer (12), via opening (18) and contact metal (20) on the second silicon layer (16) ;
FI GURE 3D shows the sealing wall (24) of the first substrate (10) being fusion or eutectically bonded to the second substrate (44) with or without using a sealing material (52) and in such a way that the microstructure (22) is completely encapsulated within the enclosed cavity (46) ; FI GURE 3E shows the wirebond (38) is connected to the contact metal (20) inside the via opening (18) in order to get electrical contact from the vertical feedthrough (26) ;
Definition of the Elements (Features/ Components/ Parts) on the Figures:
The definition of the features/ components/ parts which are covered in the figures that are prepared in order to explain the present invention better are separately numbered and given below. 10 - First (sensor) substrate
12 - First silicon layer of the first (sensor) substrate
14 - Buried oxide layer of the first (sensor) substrate
16 - Second silicon layer of the first (sensor) substrate
18 - Via opening 20 - Contact metal
22 - MEMS component
24 - Sealing wall
26 - Vertical feedthrough
28 - Second (capping) substrate made of a glass base 30 - Cavity
32 - Metal leads of the MEMS component 34 - Sealing region 36 - Sealing material 38 - Wirebond 40 - Thinned second silicon layer of the first (sensor) substrate
42 - Reduced size via opening
44 - Second (capping) substrate made of silicon
46 - Cavity on the second substrate made of silicon
48 - Dielectric on the second substrate made of silicon 50 - Sensor leads on the second substrate made of silicon
52 - Sealing material on the second substrate made of silicon
54 - Sealing region of the second substrate made of silicon
56 - Thin-film getter
Detailed Description Of The I nvention:
The present invention aims to provide an easily repeatable, high-yield, high-reliability, and low-cost wafer-level hermetic packaging method applicable to SOI -MEMS structures. The invention is described by a few exemplary embodiments, although the scope and spirit of the invention is not limited to the particular forms disclosed by these embodiments.
FI GURE 1 A shows a first substrate (10) , which is used to fabricate the MEMS component (22) and vertical feedthrough (26) on the same substrate, having a via opening (18) formed on the second layer (16) of the first substrate (10) . First substrate (10) is composed of a conductive first layer (12) , an insulator layer (14) , and a conductive second layer (16) . The first substrate (10) can be an SOI substrate composed of a conductive first silicon layer (12), a buried oxide layer (14) , and a conductive second silicon layer (16) . A via opening (18) has been patterned by a masked through-etching of the second silicon layer (16) until reaching to the buried oxide layer (14). FI GURE 1 B shows the contact metal (20) which is formed in order to get wirebond
(38) on top of the vertical feedthrough (26) for the signal transfer after the hermetic sealing.
FI GURE 1 C shows the simultaneous patterning of the MEMS component (22) , sealing wall (24) and vertical feedthroughs (26) simply by etching the first silicon layer (12) of the first substrate (10) until reaching the buried oxide layer (14) . Sealing wall (24) completely surrounds both the vertical feedthroughs (26) and MEMS component (22) .
FI GURE 1 D shows the release of the MEMS component (22) by partial etching of the buried oxide layer (14) of the first substrate (10) with dry or wet etching.
FI GURE 1 E shows a second substrate (28), which is used to fabricate the capping substrate for the MEMS component (22) in FI GURE 1 D. The base of the second substrate (28) can be made of a glass such as Borosilicate or Fyrex. The substrate (28) is patterned such that a cavity (30) and sealing regions (34) are formed simultaneously. Cavity (30) forms an offset for the MEMS component (22) of Figure 1 D to be encapsulated by the second substrate (28) .
FI GURE 1 F shows metal leads (32) and sealing material (36) simultaneously formed over the second substrate (28) using the same type of material, and they may have identical thickness. Alternatively, forming a sealing material (36) over the sealing region (34) can be ignored for the case where the hermetic sealing will be achieved by silicon-glass anodic bonding. It is possible to coat a getter material (56) inside the cavity (30) . The getter
material (56) can be a thin-film metal layer, which is capable of absorbing unwanted gases inside the cavity (30) after sealing the MEMS component, and can be deposited by using a proper shadow mask.
FI GURE 1 G shows the sealing region (34) of the second substrate (28) bonded to the sealing wall (24) of the first substrate (10) with or without using a sealing material (36) and in such a way that the MEMS component (22) is completely encapsulated in the enclosed cavity (30). Bonding technique can be silicon-glass anodic bonding, which does not require an intermediate bonding material, or a thermo-compression based bonding (eutectic or transient liquid phase bonding), which forms an eutectic alloy at the bond interface such as Au-Si, Au-Sn, etc. Bonding process can be performed in a controlled atmosphere such as a noble gas or vacuum, which defines the desired atmosphere for the MEMS component (22) encapsulated within the enclosed cavity (30). During the bonding process, vertical feedthrough (26) on the first substrate (10) is also bonded to the metal leads (32) on the second substrate (28). This way, the metal leads (32) of the MEMS component (22) can be electrically accessible from the outer world through the vertical feedthrough (26) , achieving the transfer of the metal leads (32) to the outer world without affecting the hermeticity of the package.
FI GURE 1 H shows wirebonds (38) picked from the contact metal (20) using a technique such as ball-wedge style bonding. Getting the electrical contacts from the vertical feedthroughs (26) using wirebonds (38) eliminates the need for a further conductor-refill process inside the via opening (18) .
I n a second embodiment of the present invention, it may be desired to reduce the dimensions of the via opening (18) . The size of the via opening (18) is limited by the diameter of the wire bonder capillary tip and the thickness of the second silicon layer (16) of the first substrate (10). For a fixed wire bonder capillary diameter, the via opening (18) can be reduced by decreasing the thickness of the second silicon layer (16). FI GURE 2A shows a first substrate (10), with a MEMS component (22) , sealing wall (24) , and vertical feedthrough (26) which are simultaneously formed by etching the first silicon layer (12) of the first substrate (10) . FI GURE 2B shows the release of the MEMS component (22) by partial etching the buried oxide layer (14) of the first substrate (10) with dry or wet etching.
FI GURE 2C shows a second substrate (28) , which is identical to the capping substrate of FI GURE 1 F where a cavity (30) and sealing region (34) are simultaneously formed by wet
etching and metal leads of the sensor (32) and optional sealing material (36) are formed over the second substrate (28) .
FI GURE 2D shows the sealing region (34) of the second substrate (28) bonded to the sealing wall (24) of the first substrate (10) with or without using a sealing material (36) and in such a way that the MEMS component (22) is completely encapsulated in the enclosed cavity (30). Bonding process can be a sealing material free silicon-glass anodic bonding or a thermos-compression based process (eutectic or transient liquid phase bonding), which forms an alloy at the bond interface such as Au-Si, Au-Sn, etc. Bonding process can be performed in a controlled atmosphere such as a noble gas or vacuum, which defines the desired atmosphere for the MEMS component (22) encapsulated within the enclosed cavity (30) .
FI GURE 2E shows the thinning of the second silicon layer (16) of the first substrate (10) with grinding, dry etching or wet etching. The thinned second silicon layer (40) allows the formation of reduced-size via openings (42) . FI GURE 2F shows the formation of the reduced-size via openings (42) by etching the thinned second silicon layer (40) of the first substrate (10) until reaching to the buried oxide layer (14) .
FI GURE 2H shows wirebonds (38) picked from the contact metal (20) using a technique such as ball-wedge style bonding. Getting the electrical contacts from the vertical feedthroughs (26) using wirebonds (38) eliminates the need for a further conductor-refill process inside the via opening (42) .
I n a third embodiment of the present invention, it is possible to fabricate a capping layer using a silicon wafer instead of a glass wafer. I n this way, the hermetic sealing process is achieved between two silicon wafers and the fabricated MEMS chips are less affected from the mismatches associated with the thermal expansion coefficients of the sensor and capping substrates. FI GURE 3A shows a second substrate (44) that is made from silicon, and on which a cavity (46) and a sealing region (54) are simultaneously formed by etching the top side of the second substrate (44) .
FI GURE 3B shows the formation of dielectric (48) , metal leads (50) , and sealing material (52) on top of the second substrate (44) . The dielectric layer (48) is used to passivate the metal leads (50) and sealing material (52) from the conductive second substrate (44) .
FI GURE 3C shows a first substrate (10) , which is identical to the capping substrate of FI GURE 1 D where a MEMS component (22), sealing wall (24), and vertical feedthroughs (26) are simultaneously formed by etching the first silicon layer (12) of the first substrate (10) whereas the via openings (18) are formed by etching the second silicon layer (16) of the first substrate (10) . A contact metal (20) is then formed inside the via opening (18) for wire bonding purposes. The MEMS component (22) is released by partial etching buried oxide layer (14) of the first substrate (10).
FI GURE 3D shows the sealing region (54) of the second substrate (28) bonded to the sealing wall (24) of the first substrate (10) with or without using a sealing material (52) and in such a way that the MEMS component (22) is completely encapsulated in the enclosed cavity (46) . Bonding process can be a silicon-silicon direct fusion bonding, which does not require an intermediate bonding material, or a thermo-compression based bonding (eutectic or transient liquid phase bonding) , which forms an eutectic alloy at the bond interface such as Au-Si, Au-Sn, etc. Bonding process can be performed in a controlled atmosphere such as a noble gas or vacuum, which defines the desired atmosphere for the MEMS component (22) encapsulated within the enclosed cavity (46) .
FI GURE 3E shows wirebonds (38) picked from the contact metal (20) using a technique such as ball-wedge style bonding. Getting the electrical contacts from the vertical feedthroughs (26) using wirebonds (38) eliminates the need for a further conductor-refill process inside the via opening (18) .
I n all of the embodiments disclosed above, the formation of MEMS component and vertical feedthroughs on the same substrate is highlighted for reducing the use of number of SOI wafers and process masks used in the fabrication. Still, the signal transfer is achieved by simply getting wirebond (38) on top of the vertical feedthrough (26), eliminating the need for a conductor-refill process inside the via opening (18).
I n the embodiments of the present invention listed above, the reduced number of process wafers and steps, as well as the elimination of complex processes other than the well-known MEMS deposition/etch/bonding processes increase the reliability and yield in addition to lowering the manufacturing costs of the hermetically-sealed MEMS components.
Claims
1 . A method for wafer-level hermetic packaging of Micro-electro-mechanical systems (MEMS) components, comprising steps of:
• Forming a via opening (18) patterned by a masked through-etching on first substrate (10) composed of a conductive first layer (12) , an insulator layer (14), and a conductive second layer (16)
• Forming contact metal (20) in via opening (18) on top of the first silicon layer (12) by selectively etching buried oxide layer (14) ,
• Forming at least one MEMS component (22), at least one vertical feedthrough (26), and sealing wall (24) completely surrounding the MEMS component (22) and vertical feedthroughs (26)
• releasing MEMS component (22) by partial etching of the buried oxide layer (14) with dry or wet etching
• forming a second substrate (28, 44) for capping and routing metallization
• Bonding the first substrate (10) to the second substrate (28,44)
2. The method according to Claim 1 , wherein the first substrate (10) is silicon-on-insulator (SOI) substrate comprising a first silicon layer (12) , a second silicon layer (16) , and a buried oxide layer (14) sandwiched between the first silicon layer (12) and second silicon layer (16).
3. The method according to Claim 1 , wherein second substrate (28) is glass.
4. The method according to Claim 1 , wherein second substrate (44) is silicon.
5. The method according to Claim 3, wherein forming second substrate (28) for capping and routing metallization comprises steps of,
• forming a cavity (30), and a sealing region (34) that completely surrounds the cavity (30)
• forming metal leads (32),
• optionally forming thin film getter (56) and sealing material (36)
6. The method according to Claim 4, wherein forming second substrate (44) for capping and routing metallization comprises steps of,
• forming a cavity (30), and a sealing region (34) that completely surrounds the cavity (30)
• forming a dielectric layer (48)
• forming metal leads (32),
• optionally forming thin film getter (56) and sealing material (36)
7. The method according to Claim 3, wherein bonding is silicon-glass anodic bonding, eutectic or transient liquid phase bonding.
8. The method according to Claim 4, wherein bonding is silicon-silicon fusion bonding, eutectic or transient liquid phase bonding.
9. The method according to Claim 1 , further comprising step of forming wirebond (38) on the exposed surfaces of the vertical feedthroughs (26) that are exposed to the contact metal (20) in the via openings (18) on the first substrate (10) .
10. A method for wafer-level hermetic packaging of Micro-electro-mechanical systems (MEMS) components, comprising steps of:
• Forming at least one MEMS component (22), at least one vertical feedthrough (26), and sealing wall (24) completely surrounding the MEMS component (22) and vertical feedthroughs (26) on first substrate (10) composed of a conductive first layer (12), an insulator layer (14), and a conductive second layer (16)
• releasing MEMS component (22) by partial etching of the buried oxide layer (14) with dry or wet etching
• forming a second substrate (28, 44) for capping and routing metallization
• Bonding the first substrate (10) to the second substrate (28,44)
• Thinning second silicon layer (40)
• Forming reduced-size via openings (42)
• Forming contact metal (20) in reduced- via opening (42) on top of the first silicon layer (12) by selectively etching buried oxide layer (14)
1 1 . The method according to Claim 10, wherein the first substrate (10) is silicon-on-insulator (SOI) substrate comprising a first silicon layer (12) , a second silicon layer (16) , and a buried oxide layer (14) sandwiched between the first silicon layer (12) and second silicon layer (16).
12. The method according to Claim 10, wherein second substrate (28) is glass.
13. The method according to Claim 10, wherein second substrate (44) is silicon.
14. The method according to Claim 12 , wherein forming second substrate (28) for capping and routing metallization comprises steps of,
• forming a cavity (30), and a sealing region (34) that completely surrounds the cavity (30)
• forming metal leads (32),
• optionally forming thin film getter (56) and sealing material (36)
15. The method according to Claim 13, wherein forming second substrate (44) for capping and routing metallization comprises steps of, · forming a cavity (30), and a sealing region (34) that completely surrounds the cavity (30)
• forming a dielectric layer (48)
• forming metal leads (32),
• optionally forming thin film getter (56) and sealing material (36)
16. The method according to Claim 12, wherein bonding is silicon-glass anodic bonding, eutectic or transient liquid phase bonding.
17. The method according to Claim 13, wherein bonding is silicon-silicon fusion bonding, eutectic or transient liquid phase bonding.
18. The method according to Claim 10, further comprising step of forming wirebond (38) on the exposed surfaces of the vertical feedthroughs (26) that are exposed to the contact metal (20) in the reduced-via openings (42) on the first substrate (10) .
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/TR2015/050001 WO2016200346A1 (en) | 2015-06-08 | 2015-06-08 | Hermetic packaging method for soi-mems devices with embedded vertical feedthroughs |
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/TR2015/050001 WO2016200346A1 (en) | 2015-06-08 | 2015-06-08 | Hermetic packaging method for soi-mems devices with embedded vertical feedthroughs |
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