CN101430663A - Caching management unit and caching management method - Google Patents
Caching management unit and caching management method Download PDFInfo
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- CN101430663A CN101430663A CNA2007100480140A CN200710048014A CN101430663A CN 101430663 A CN101430663 A CN 101430663A CN A2007100480140 A CNA2007100480140 A CN A2007100480140A CN 200710048014 A CN200710048014 A CN 200710048014A CN 101430663 A CN101430663 A CN 101430663A
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Abstract
The invention discloses a cache management unit and a cache management method. The cache management unit comprises a state calculation circuit for calculating effective data in a cache and obtaining a cache state according to calculation of effective data values; a state indication circuit for outputting the cache state to a producer and/or a consumer; a writing synchronization circuit for sending a writing synchronization signal to perform writing synchronization operation on the state calculation circuit when the producer really writings primary data in the cache at each time; a reading synchronization circuit for sending a reading synchronization signal to perform reading synchronization operation on the state calculation circuit when the customer receives the primary data in the cache at each time; a writing presynchronization circuit for sending a writing presynchronization signal to perform writing presynchronization operation on the state calculation circuit when the producer sends out a write command at each time; and a reading presynchronization circuit for sending a reading presynchronization signal to perform reading presynchronization operation on the state calculation circuit when the customer sends out a read command at each time. The cache management unit and the cache management method help enhance the overall cache efficiency.
Description
Technical field
The present invention relates to cache management, relate in particular to the memory management unit and the corresponding buffer memory management method that adopt hardware circuit to realize.
Background technology
In system design, data often will be delivered to the consumer from the producer.General, between the producers and consumers, need cache resources data cached.Cache resources generally includes storage resources such as SRAM, SDRAM and FIFO.Cache resources need manage, make the producers and consumers visit can be correct during this buffer memory the state that obtains buffer memory, thereby avoid taking place resource contention.
General, the producer can be divided into 3 series processes to cache writing data at every turn: the producer produces data, the producer sends out write order and data write buffer memory.The consumer can divide 2 series processes from the buffer memory read data at every turn: the consumer sends out read command and the consumer receives data.No matter be the producer to cache writing data or consumer from the buffer memory read data, all exist different time-delays between each series process.For example, the producer in the cache writing data process, the producer sends out write order to buffer memory after producing data, but whether the producer does not understand the state of buffer memory this moment allows to continue write data next time, after needing one section time-delay of experience, by the buffer status signal that buffer memory feeds back, could understand the state of buffer memory., from the buffer memory reading data course, after the consumer sends out read command, also need to understand in the buffer memory whether allow to continue read data next time earlier the consumer.And the producer to cache writing data and consumer from the buffer memory reading data course, the status signal of buffer memory feedback need obtain from the data volume that buffer memory is read to data volume or the consumer that buffer memory writes according to the producer.
The management of buffer memory generally both can be carried out by pure software, also can be carried out by hardware, and perhaps both are in conjunction with carrying out.The implementation of pure software generally is the management of finishing buffer memory by the processor executive routine; The implementation of hardware mainly is the management that special memory management unit of design is finished buffer memory.Because the granularity of pure software management buffer memory is all bigger, the implementation of pure software can not be very accurate to the management of buffer memory, for example, when the state of return cache, because the delay that program is carried out, when buffer status arrived the producers or consumers, real buffer status changed to some extent.Utilize memory management unit to carry out cache management, the accuracy that has on the one hand improved cache management greatly can be accurate to the management buffer memory of clock period level; On the other hand, can also discharge processor resource, memory management unit is when carrying out cache management, and processor can carry out other work.
During memory management unit management cache resources, provide the status signal of buffer memory to the producers or consumers by memory management unit.In the general existing memory management unit, the producer (or consumer) synchronization caching administrative unit each time will just can carry out in the final step of series process, promptly writes buffer memory (or the consumer receives data) in data and carries out afterwards.Before carrying out management by synchronization, the synchronization caching administrative unit can't provide the state of buffer memory in advance, thereby causes the producers and consumers can't be with the pipeline system access cache, promptly, will be after the producer finish whole data and write, the consumer could begin to carry out reading of data.Like this, carry out exchanges data the producers and consumers by bus, perhaps the producer needs the long period to produce under the data conditions, uses general memory management unit loss in efficiency will occur.
As shown in Figure 1, the producer 11 and consumer 12 come shared buffer memory 15 by bus 13, and the buffer memory 15 here for example is SDRAM.Adopt general basic model memory management unit 17 shown in Figure 3 to carry out cache management among Fig. 1.Basic model memory management unit shown in Figure 3 comprises state calculation circuit 171, writes synchronizing circuit 173, reads synchronizing circuit 175 and condition indication circuit 177.According to the agreement of memory management unit, be provided with full signal and empty signal in the condition indication circuit 177, full signal indication buffer memory takes, and can not receive new data; Empty signal indication buffer memory is empty, does not have enough data can supply to have read.The producer could whenever write a secondary data and will notify memory management unit after buffer memory toward write data in the buffer memory in the full invalidating signal, for example can notify memory management unit by sending write buffer signal.Memory management unit carries out synchronous operation by writing synchronizing circuit after data are written to buffer memory.The consumer could be from buffer memory in the empty invalidating signal read data, whenever from buffer memory, read a secondary data and all will notify memory management unit, for example can notify memory management unit by sending read buffer signal.Memory management unit carries out synchronous operation by reading synchronizing circuit after consumer's sense data.
Because have time-delay on the bus, after the producer sent write order, data were not write in the buffer memory immediately; After the consumer sent read command, the consumer did not receive data immediately yet.Sending write order the producer really writes to data in the delay time in the buffer memory, because memory management unit does not also provide the state of buffer memory, even also have unnecessary space in the buffer memory, the basic model memory management unit can not allow the producer to continue write data, (otherwise old valid data may be covered by new valid data), thus loss on the buffer efficiency caused.Similarly, sending read command the consumer really returns to data in the delay time between the consumer inside, because memory management unit does not also provide the state of buffer memory, even also have enough data in the buffer memory, the basic model memory management unit can not allow the consumer to continue read data, (otherwise may read invalid data) can cause the loss on the meeting buffer efficiency equally.
In the example shown in Figure 2, the producer 11 and consumer's 12 direct shared buffer memory 15, the buffer memory 15 here for example is SRAM.Also adopt basic model memory management unit shown in Figure 3 17 to carry out cache management among Fig. 2.The producer could whenever write a secondary data and will notify memory management unit after buffer memory toward write data in the buffer memory in the full invalidating signal, for example can notify memory management unit by sending the writebuffer signal.Memory management unit 17 carries out synchronous operation by writing synchronizing circuit 173 after data are written to buffer memory 15.The consumer could be from buffer memory in the empty invalidating signal read data, whenever from buffer memory, read a secondary data and all will notify memory management unit, for example can notify memory management unit by sending read buffer signal.Memory management unit carries out synchronous operation by reading synchronizing circuit 175 after consumer's sense data.In this scene, the producer needs a long time to produce data, needs to obtain data from bus earlier such as the producer, and exists competition and arbitration etc. on the bus, has prolonged the time-delay that the producer obtains data further.
Because there is a process that produces data in the producer, the producer (or consumer) will write buffer memory (or receiving data) in data each time and utilize memory management unit to carry out management by synchronization afterwards.Memory management unit can't provide the state of buffer memory in advance, and therefore, in the basic model memory management unit, the producer produces actions such as data and this write order of the producer next time can not parallel expansion.Even also have unnecessary space in the buffer memory, the basic model memory management unit can not allow the producer to continue to produce data.After each producer finishes to all operations that data is write buffer memory from generation data, transmission write order, just can restart the operation of generation data next time, can't make full use of the time-delay that produces data, cause the loss on the efficient.
Summary of the invention
Fundamental purpose of the present invention provides a kind of memory management unit, can accurately, in time reflect buffer status, and can allow generation person and consumer carry out the write and read buffer memory in the mode of streamline, thereby improves the service efficiency of buffer memory.
Another object of the present invention provides a kind of buffer memory management method that improves the service efficiency of buffer memory.
According to an aspect of the present invention, provide a kind of memory management unit, comprising:
State calculation circuit in order to the valid data in the buffer memory are calculated, and calculates buffer status according to the valid data value;
Condition indication circuit is in order to export to buffer status the producer and/or consumer;
Write synchronizing circuit, when the producer really writes a secondary data in the buffer memory at every turn, send one and write synchronizing signal state calculation circuit is write synchronous operation;
Read synchronizing circuit, when the consumer receives in the buffer memory secondary data at every turn, send one and read synchronizing signal state calculation circuit is read synchronous operation;
Write the presynchronization circuit, when the producer sends a write order at every turn, send one and write the presynchronization signal state calculation circuit is write presynchronization operation;
Read the presynchronization circuit, when the consumer sends a read command at every turn, send one and read the presynchronization signal state calculation circuit is read presynchronization operation.
According to above-mentioned memory management unit, wherein, described state calculation circuit comprises according to described to be write the presynchronization signal and reads first counter that the buffer memory valid data are write in synchronizing signal calculating, and reads the presynchronization signal and write second counter that the buffer memory valid data are read in synchronizing signal calculating according to described.
According to above-mentioned memory management unit, wherein, described state calculation circuit also comprises according to described to be write the buffer memory valid data and writes first comparator circuit that max-thresholds obtains the state of writing of buffer memory, and according to described second comparator circuit of reading the buffer memory valid data and reading the read states of minimum threshold acquisition buffer memory, wherein, write max-thresholds and represent to allow the max-thresholds of the producer, read minimum threshold and represent to allow the minimum threshold of consumer from the buffer memory sense data to buffering write data.
According to above-mentioned memory management unit, wherein, the digit of described first counter and second counter is the size of synchronization granularity, and this synchronization granularity writes the data volume size of a secondary data or the consumer reads a secondary data from buffer memory data volume size for the producer to buffer memory.
According to above-mentioned memory management unit, described synchronization granularity is fixed.
According to above-mentioned memory management unit, described synchronization granularity changes.
According to above-mentioned memory management unit, the data volume N that the producer writes a secondary data to buffer memory fixes, and the consumer fixes from the data volume M of cache read one secondary data, and data volume N is identical with data volume M or have a proportionate relationship.
According to above-mentioned memory management unit, wherein, the described presynchronization signal of writing is to send after the producer is dealt into the write order of a synchronization granularity on the bus, or before the producer sends to bus with first write order, or a part of write order sends to and sends after the bus.
According to above-mentioned memory management unit, wherein, the described presynchronization signal of reading is to send after the consumer is dealt into the read command of a synchronization granularity on the bus, or before the consumer sends to bus with first read command, or a part of read command sends to and sends after the bus.
According to above-mentioned memory management unit, wherein, described writing comprises the information of writing a data synchronization granule size in the presynchronization signal, describedly reads to comprise in the presynchronization signal information of reading a data synchronization granule size.
According to a further aspect in the invention, provide a kind of buffer memory management method, comprise the steps:
When administrative unit allowed to write data, the producer sent to memory management unit and writes the presynchronization notice;
Memory management unit receive effectively write presynchronization notice after, calculate the useful space of buffer memory according to writing the presynchronization notice, and feed back to the producer;
After the producer really writes a secondary data in the buffer memory, send to memory management unit and to write synchronization notice;
Memory management unit receives to be write after the synchronization notice, calculates the valid data of buffer memory, and feeds back to the consumer;
When memory management unit allowed reading of data, the consumer sent to memory management unit and reads the presynchronization notice;
Memory management unit receive effectively read presynchronization notice after, calculate the valid data of buffer memory according to reading the presynchronization notice, and feed back to the consumer;
After the consumer really reads a secondary data among the consumer, send to memory management unit and to read synchronization notice;
Memory management unit receives to be read after the synchronization notice, calculates the useful space of buffer memory, and feeds back to the producer.
According to a further aspect in the invention, provide a kind of buffer memory management method, comprise the steps:
When memory management unit allowed to write data, the producer sent to memory management unit and writes the presynchronization notice;
Memory management unit receive effectively write presynchronization notice after, calculate the useful space of buffer memory according to writing the presynchronization notice, and feed back to the producer;
After the producer really writes a secondary data in the buffer memory, send to memory management unit and to write synchronization notice;
Memory management unit receives to be write after the synchronization notice, calculates the valid data of buffer memory, and feeds back to the consumer.
According to a further aspect in the invention, provide a kind of buffer memory management method, comprise the steps:
When memory management unit allowed reading of data, the consumer sent to memory management unit and reads the presynchronization notice;
Memory management unit receive effectively read presynchronization notice after, calculate the valid data of buffer memory according to reading the presynchronization notice, and feed back to the consumer;
After the consumer really reads a secondary data among the consumer, send to memory management unit and to read synchronization notice;
Memory management unit receives to be read after the synchronization notice, calculates the useful space of buffer memory, and feeds back to the producer.Memory management unit provided by the invention has increased the producer and has read the presynchronization circuit to write presynchronization circuit and the consumer of the presynchronization operation of cache writing data from the presynchronization operation of buffer memory read data compared to prior art.The producer is in the cache writing data process, owing to when sending write order, just carry out in advance synchronously, be equivalent to memory management unit before the write data and just carried out in advance the synchronous operation of writing, memory management unit can be before data writing operation be finished, and just sends to write status signal and give the producer.The producer can begin to prepare data in advance according to writing status signal, makes the producer can make full use of the delay of preparing data or bus etc., and improves buffer efficiency.Similarly, the consumer is from the buffer memory reading data course, owing to when sending read command, just carry out in advance synchronously, be equivalent to memory management unit before the read data and just carried out in advance the synchronous operation of reading, memory management unit can just be sent status signals and give the consumer before the read data operation be finished.The consumer can send read command in advance according to status signals, thereby improves buffer efficiency.And,, make that writing the process that the consumer reads from the producer can carry out with the form of streamline, has therefore improved the efficient of buffer memory on the whole because the consumer can know the state of buffer memory in advance before the producer really writes data to buffer memory.
Description of drawings
The following drawings is the aid illustration to exemplary embodiment of the present, to the elaboration of the embodiment of the invention, be to disclose feature of the present invention place, but do not limit the present invention in conjunction with the following drawings for further, same-sign is represented respective element or step among the embodiment among the figure, wherein:
Fig. 1 is a kind of application model synoptic diagram of memory management unit.
Fig. 2 is the another kind of application model synoptic diagram of memory management unit.
Fig. 3 is the circuit theory synoptic diagram of a kind of basic model memory management unit in the prior art.
Fig. 4 is the circuit theory synoptic diagram of memory management unit of the present invention.
Fig. 5 is the circuit block diagram of state calculation circuit according to an embodiment of the invention.
Fig. 6 is the circuit structure block diagram of counter according to an embodiment of the invention.
Fig. 7 is the process flow diagram of the buffer memory management method according to the present invention.
Fig. 8 is the cache management sequential chart of the write-once data of buffer memory management method according to an embodiment of the invention.
Fig. 9 is the cache management sequential chart of a reading of data of buffer memory management method according to an embodiment of the invention.
Embodiment
The present invention adopts hardware circuit that cache resources is managed, and both can discharge processor resource, also can improve the accuracy of cache management, makes buffer status can be as accurate as a clock period level.The circuit that among the present invention cache resources is managed is called memory management unit, when integrated circuit is realized, both can design independent circuit, also can direct multiplexing integrated circuit in original hardware resource.
Fig. 4 represents the circuit theory synoptic diagram of memory management unit according to an embodiment of the invention.Memory management unit comprises state calculation circuit 171, writes synchronizing circuit 173, reads synchronizing circuit 175, writes presynchronization circuit 178, reads presynchronization circuit 179 and condition indication circuit 177 among the figure.State calculation circuit is used for the valid data in the buffer memory are calculated, and calculates buffer status according to the valid data value; Condition indication circuit is exported to the producers and consumers to buffer status; Write synchronizing circuit at every turn when the producer really writes a secondary data in the buffer memory, state calculation circuit is write synchronous operation; Read synchronizing circuit at every turn when the consumer receives in the buffer memory secondary data, state calculation circuit is read synchronous operation; Write the presynchronization circuit at every turn when the producer sends a write order, state calculation circuit is write the presynchronization operation; Read the presynchronization circuit at every turn when the consumer sends a read command, state calculation circuit is read the presynchronization operation.
Fig. 5 is the circuit block diagram of state calculation circuit according to an embodiment of the invention.State calculation circuit is main according to writing synchronizing circuit, read synchronizing circuit, writing the presynchronization circuit and read input signal that the presynchronization circuit provides and calculate the valid data or the useful space in the buffer memory, and, obtain the state of writing and the read states of buffer memory by after the comparator circuit comparison operation.In some embodiments of the invention, state calculation circuit can realize with counter 1711,1712 and comparator circuit 1717,1718.
Counter has a read-write pointer at least, can count the valid data in the buffer memory, and give comparator circuit the effective data value of buffer memory of record.The digit of counter can be the size of synchronization granularity, and synchronization granularity writes the data volume size of a secondary data or the consumer reads a secondary data from buffer memory data volume size for the producer to buffer memory.
Fig. 6 is the circuit structure block diagram of counter according to an embodiment of the invention.Counter has counting logical circuit 1713 and d type flip flop 1714.The counting logical circuit has the first input end mouth Sel0 and the second input port Sel1, and output port connects d type flip flop.The output of d type flip flop is the output of counter, and the output port of d type flip flop is the connection count logical circuit simultaneously.The initial value (representing with A at this) of the read-write pointer of counting logical circuit after the logical operation through the counting logical circuit, obtains output valve (representing with B at this).The output valve B of counting logical circuit output port from counter behind d type flip flop is exported.Simultaneously, the output valve of counter output mouth still must feed back to the counting logical circuit, as the initial value A of the read-write pointer of counting logical circuit.The logical operation principle of work of wherein counting logical circuit is as follows.
1.Sel0=1 and Sel1=0, then B=A+1
2.Sel0=0 and Sel1=1, then B=A-1
3.Sel0=0 and Sel1=0, then B=A
4.Sel0=1 and Sel1=1, then B=A
That is, effective as the first input end mouth Sel0 of counter, and the second input port Sel1 is when invalid, and the output valve of counter is that initial value adds 1; Sel0 is invalid when the first input end mouth, and the second input port Sel1 is when effective, and the output valve of counter is that initial value subtracts 1; As first input end mouth Sel0 with the second input port Sel1 is invalid or all effectively the time, the output valve of counter is initial value.
According to one embodiment of present invention, the presynchronization circuit is write in the first input end mouth Sel0 of first counter connection, and synchronizing circuit is read in second input port Sel1 connection, and output port connects second input port of first comparator circuit; Synchronizing circuit is write in the first input end mouth Sel0 connection of second counter, and the presynchronization circuit is read in second input port Sel1 connection, and output port connects second input port of second comparator circuit.First counter is write the presynchronization signal and is read synchronizing signal according to input, calculates and writes the buffer memory valid data, and output to first comparator circuit.Second counter is read the buffer memory valid data according to writing synchronizing signal and reading the presynchronization calculated signals of input, and outputs to second comparator circuit.
According to the logical operation principle of work of counting logical circuit, the principle of work of first counter is as follows:
1.prepsyc=1 and csync=0, then B=A+1
2.prepsyc=0 and csync=1, then B=A-1
3.prepsyc=0 and csync=0, then B=A
4.prepsyc=1 and csync=1, then B=A
That is to say,, 4 kinds of situations may occur for first counter.Under the 1st kind of situation, it is effective to write presynchronization signal prepsync signal, and read synchronizing signal csync invalidating signal, promptly this moment, the producer sent a write order, and the consumer does not receive data from buffer memory, then first counter of state calculation circuit adds 1, has increased a valid data value in the expression buffer memory.On the contrary, under the 2nd kind of situation, write presynchronization signal prepsync invalidating signal, and it is effective to read synchronizing signal csync signal, promptly this moment, the producer did not send write order, and the consumer receives data from buffer memory, and then first counter of state calculation circuit subtracts 1, has reduced by a valid data value in the expression buffer memory.The 3rd or the 4th kind of situation under, it is invalid simultaneously or simultaneously effectively, the output valve of first counter of state calculation circuit is constant to write presynchronization signal prepsync signal and read synchronizing signal csync signal, the quantity of valid data value is constant in the expression buffer memory.
The principle of work of second counter is as follows:
1.psync=1 and precsyc=0, then B=A+1
2.psync=0 and precsyc=1, then B=A-1
3.psync=0 and precsyc=0, then B=A
4.psync=1 and precsyc=1, then B=A
Similarly, for second counter, 4 kinds of situations may appear also.Under the 1st kind of situation, read presynchronization signal precsync invalidating signal, and it is effective to write synchronizing signal psync signal, promptly this moment, the consumer did not send read command, and the producer has sent data to buffer memory, then second counter of state calculation circuit adds 1, has increased a valid data value in the expression buffer memory.On the contrary, under the 2nd kind of situation, it is effective to read presynchronization signal precsync signal, and write synchronizing signal psync invalidating signal, promptly this moment, the consumer sent a read command, and the producer does not send data in the buffer memory, and then second counter of state calculation circuit reduces 1, has reduced by a valid data value in the expression buffer memory.The 3rd or the 4th kind of situation under, it is invalid simultaneously or simultaneously effectively, the output valve of second counter of state calculation circuit is constant to read presynchronization signal prepcync signal and write synchronizing signal psync signal, the quantity of valid data value is constant in the expression buffer memory.
Usually according to the characteristic of cache resources, can write max-thresholds and read minimum threshold, wherein write max-thresholds and refer to allow the producer to write the max-thresholds of data, read the minimum threshold that minimum threshold refers to allow consumer's sense data for the buffer memory setting.State calculation circuit need and be write max-thresholds max_threshold the effective data value of the buffer memory of counter records and compare, to obtain the state of writing of buffer memory; Simultaneously, need and read minimum threshold min_threshold the effective data value of the buffer memory of counter records and compare, to obtain the read states of buffer memory.
Among the embodiment shown in Figure 5, realize effective data value of buffer memory and the comparison of writing max-thresholds, realize effective data value of buffer memory and the comparison of reading minimum threshold with second comparator circuit with first comparator circuit.Wherein, the input signal of first comparator circuit is respectively the effective data value of buffer memory of writing the max-thresholds and first counter records of buffer memory, output signal be can indicate whether buffer memory allow to write data write status signal pstatus signal.For example, the effective data value of buffer memory is when writing max-thresholds, and the output signal display buffer allows the producer to write data; The effective data value of buffer memory is greater than or equal to when writing max-thresholds, and the output signal display buffer does not allow the producer to write data.The input signal of second comparator circuit is respectively the effective data value of buffer memory of reading the minimum threshold and second counter records of buffer memory, and output signal is to indicate buffer memory whether to allow the status signals cstatus signal of sense data.For example, the effective data value of buffer memory is when reading minimum threshold, and the output signal display buffer allows consumer's sense data; The effective data value of buffer memory is less than or equal to when reading minimum threshold, and the output signal display buffer does not allow consumer's sense data.177 of condition indication circuits comprise being used for exporting writes writing the status signal indicating circuit and being used for exporting the status signals indicating circuit of status signals cstatus signal of status signal pstatus signal.In some embodiments of the invention, writing max-thresholds and reading minimum threshold of buffer memory all can be provided with, and for example, can write by program.
According to one embodiment of present invention, write synchronizing signal, to read synchronizing signal, write the presynchronization signal and read the presynchronization signal be monocycle signal.When signal was effective, for example writing synchronizing signal, to provide one-period be 1 pulse value, and the expression producer has really write buffer memory inside to a secondary data from the producer.Be understandable that in other embodiments, writing synchronizing signal, reading synchronizing signal, write the presynchronization signal and read the presynchronization signal also can be binary cycle signal or other type signal.
According to one embodiment of present invention, writing status signal and status signals is level signal.Write status signal when effective, for example writing status signal pstatus signal value is 1, and the expression buffer memory allows the producer to write a secondary data; When invalid, for example writing status signal pstatus signal value is 0, and the expression buffer memory does not allow the producer to write a secondary data.Similarly, when status signals was effective, for example status signals cstatus signal value was 1, and the expression buffer memory allows the consumer to read a secondary data; When invalid, for example status signals cstatus signal value is 0, and the expression buffer memory does not allow the consumer to read a secondary data.In other embodiments, write status signal pstatus signal and status signals cstatus signal also can be represented with the signal of monocycle signal or other type.
In one embodiment of the invention, when the producer write a secondary data or consumer from cache read one secondary data to buffer memory, one time the data synchronization granularity was determined, promptly the synchronization granularity of memory management unit keeps identical.Synchronization granularity can be configured to the designated parameter value of counter.
In another embodiment of the present invention, the producer data volume N from a secondary data to buffer memory that write fixes; The consumer can fix from the data volume M of cache read one secondary data; But N is not necessarily identical with M, and they can have proportionate relationship, and memory management unit also can have corresponding modification.N/M=3/2 for example, for memory management unit, each value that increases or reduce is 3 in first counter, and each value that increases or reduce is 2 in second counter.
In yet another embodiment of the present invention, when the producer write a secondary data or consumer from cache read one secondary data to buffer memory, one time the data synchronization granule size can change, and promptly the synchronization granularity of memory management unit is inequality.For example, can increase a control register, utilize register bus will read and write pointer and be configured to memory management unit.For memory management unit, the each value that increases or reduce of first counter and second counter is not fixed, but the write pointer that transmits from bus or the value of read pointer.
According to other embodiments of the invention, the producer and consumer can adopt asynchronous clock.
Referring to Fig. 7, buffer memory management method of the present invention comprises the steps:
S1, when memory management unit allowed to write data, the producer sent to memory management unit and writes the presynchronization notice.
S2, memory management unit receive effectively write presynchronization notice after, calculate the useful space of buffer memory according to writing the presynchronization notice, and feed back to the producer.
S3 after the producer really writes a secondary data in the buffer memory, sends to memory management unit and to write synchronization notice.
S4, memory management unit receive write synchronization notice after, calculate the valid data of buffer memory according to writing synchronization notice, and feed back to the consumer.
S5, when memory management unit allowed reading of data, the consumer sent to memory management unit and reads the presynchronization notice.
S6, memory management unit receive effectively read presynchronization notice after, calculate the valid data of buffer memory according to reading the presynchronization notice, and feed back to the consumer.
S7 after the consumer really reads a secondary data among the consumer, sends to memory management unit and to read synchronization notice.
S8, memory management unit receive read synchronization notice after, calculate the useful space of buffer memory according to reading synchronization notice, and feed back to the producer.
Wherein, write in the presynchronization signal prepsync signal and comprise the information of writing a data synchronization granule size.Read to comprise the information of reading a data synchronization granule size in the presynchronization signal precsync signal.
Fig. 8 is the sequential chart of the cache management that writes a secondary data of buffer memory management method according to an embodiment of the invention.When memory management unit provide to write status signal pstatus signal effective, expression can be in buffer memory write data, the producer sends to memory management unit and keeps one-period and effectively write presynchronization signal prepsync signal, the notice memory management unit, the producer will write the data (as 1024 bytes) of a synchronization granularity in the buffer memory.
Memory management unit receive effectively write presynchronization signal prepsync signal after, calculate the useful space of buffer memory immediately, and give the producer with the fastest velocity feedback.According to one embodiment of present invention, memory management unit receive effectively write presynchronization signal prepsync signal after, the read-write pointer of first counter is added 1, and amended read-write pointer with write max-thresholds relatively.If receiving the current period of writing presynchronization signal prepsync signal, the only remaining useful space that is less than or equal to the data of a synchronization granularity in the buffer memory, the status signal pstatus signal condition of writing that feeds back to the producer so is invalid, i.e. producer's write data again.The useful space of being left in the buffer memory is greater than the data of a synchronization granularity, and what feed back to the producer so writes status signal pstatus signal for effective, and the producer can be to cache writing data.The producer sends to memory management unit and to keep one-period and effectively write synchronizing signal psync signal after really writing a secondary data in the buffer memory, and notice memory management unit data have been write buffer memory and suffered.
Among Fig. 8 with the valid data amount of the buffer memory of the read-write pointer record of psector_cnt parametric representation memory management unit, th_max value representation valid data arrive writes max-thresholds, i.e. the only remaining useful space that is less than or equal to the data of a synchronization granularity in the buffer memory; Th_max-1 represents valid data than the data volume of writing max-thresholds and lack a synchronization granularity, promptly in the buffer memory the remaining useful space greater than the data of a synchronization granularity.In Fig. 8, suppose that at the current period of receiving the prepsync signal also be left the useful space of a secondary data in the buffer memory, the pstatus signal condition that feeds back to the producer so is for effective, the producer can write a secondary data.After the counter of memory management unit is receiving effectively write presynchronization signal prepsync signal, the read-write pointer of valid data in the record buffer memory of counter is increased by 1, and the read-write pointer after increasing with write max-thresholds relatively.Among Fig. 8, receiving the next cycle of writing presynchronization signal prepsync signal, data volume in the buffer memory has reached writes max-thresholds, that is to say, the only remaining useful space that is less than or equal to the data of a synchronization granularity, the status signal pstatus signal condition of writing that feeds back to the producer so is invalid, i.e. producer's write data again.The producer one secondary data is write the same one-period that the operation of buffer memory is finished, the producer to memory management unit send keep one-period write synchronizing signal psync signal.And write synchronizing signal psync signal and can't and write status signal pstatus signal to the read-write pointer of first counter and exert an influence this moment.
Memory management unit is judged the state of writing status signal pstatus signal according to writing presynchronization signal prepsync signal and reading synchronizing signal csync signal.As shown in Figure 8, when the consumer reads a secondary data from buffer memory, and data arrive the consumer when inner, and the consumer sends to memory management unit and keeps one-period and effectively read synchronizing signal csync signal, and notice memory management unit data have been read consumer inside.Memory management unit receive effectively read synchronizing signal csync signal after, calculate the useful space of buffer memory immediately, and give the producer with the fastest velocity feedback.Receiving the current period of reading synchronizing signal csync signal, the space write of data once again in the buffer memory, the valid data amount psector_cnt parameter of promptly reading and writing the buffer memory of pointer record becomes th_max-1 again, what feed back to the producer so writes status signal pstatus signal condition for effective, and promptly the producer can continue to cache writing data.
Fig. 9 is the sequential chart of the cache management that reads a secondary data of buffer memory management method according to an embodiment of the invention.When the consumer sees that the status signals cstatus signal condition that memory management unit provides is effective, expression can be from buffer memory read data, the consumer sends to memory management unit and keeps one-period and effectively read presynchronization signal precsync signal, the notice memory management unit, the consumer will read a secondary data (as 1024 bytes) from buffer memory.
Memory management unit receive effectively read presynchronization signal precsync signal after, calculate the valid data of buffer memory immediately, and give the consumer with the fastest velocity feedback.According to one embodiment of present invention, memory management unit receive effectively read presynchronization signal precsync signal after, the read-write pointer of second counter is subtracted 1, and amended read-write pointer with read minimum threshold relatively.If receiving the current period of reading presynchronization signal precsync signal, remaining valid data arrive and read minimum threshold in the buffer memory, the status signals cstatus signal condition that feeds back to the consumer so is invalid, i.e. consumer's read data again.If valid data remaining in the buffer memory, feed back to consumer's status signals cstatus signal condition greater than reading minimum threshold so for effective, the consumer can be to the cache read data.Memory management unit is according to reading presynchronization signal precsync signal and writing the state that synchronizing signal psync signal is judged status signals cstatus signal.
With the valid data in the csector_cnt parametric representation buffer memory, the valid data in the th_min value representation buffer memory arrive reads minimum threshold among Fig. 9; Th_min+ 1 represents that the interior valid data of buffer memory are than reading the data that minimum threshold exceeds a synchronization granularity.
Among Fig. 8, receiving the next cycle of reading presynchronization signal precsync signal, data volume in the buffer memory has reached reads minimum threshold, that is to say, only be left valid data less than the data of a synchronization granularity, the status signals cstatus signal condition that feeds back to the producer so is invalid, i.e. consumer's read data again.
The consumer sends to memory management unit and to keep one-period and effectively read synchronizing signal csync signal after a secondary data is really read the consumer, and notice memory management unit data have really been read consumer inside.Really read the same one-period that the operation of a secondary data is finished the consumer, the consumer to memory management unit send keep one-period read synchronizing signal csync signal.And this moment, reading synchronizing signal csync signal can't exert an influence to the read-write pointer and the status signals cstatus signal of second counter.
When the producer really writes a write data in the buffer memory, send to memory management unit and to keep the effective psync signal of one-period, the notice memory management unit has been write data in the buffer memory.Memory management unit receive effectively write synchronizing signal psync signal after, calculate the useful space of buffer memory immediately, and give the consumer with the fastest velocity feedback.Receiving the current period of writing synchronizing signal psync signal, data readable once again in the buffer memory, the status signals cstatus state that feeds back to the consumer so is for effectively, and promptly the consumer can continue from the buffer memory read data.
Memory management unit provided by the invention compared to prior art, increased be used for carrying out the producer to the presynchronization operation of cache writing data write the presynchronization circuit and be used for carrying out the consumer from the buffer memory read data read the presynchronization operation read the presynchronization circuit.Because the producer is in the cache writing data process, owing to when sending write order, just carry out in advance synchronously, be equivalent to memory management unit before the write data and just carried out in advance the synchronous operation of writing, memory management unit can be before data writing operation be finished, and just sends to write status signal and give the producer.The producer can begin to prepare data in advance according to writing status signal, makes the producer can the adequate preparation data or the delay of bus etc., and improves buffer efficiency.Similarly, because the consumer is from the buffer memory reading data course, owing to when sending read command, just carry out in advance synchronously, be equivalent to memory management unit before the read data and just carried out in advance the synchronous operation of reading, memory management unit can just be sent status signals and give the consumer before the read data operation be finished.The consumer can send out read command in advance according to status signals, thereby improves buffer efficiency.And,, make that writing the process that the consumer reads from the producer can carry out with the form of streamline, has therefore improved the efficient of buffer memory on the whole because the consumer can know the state of buffer memory in advance before the producer really writes data to buffer memory.And, synchronization granularity the producers and consumers is identical, and under the identical condition of work clock, because adopting hardware circuit realizes, write the presynchronization circuit and read the presynchronization circuit and can adopt monocycle signal work, can make the delay minimization that provides buffer status to the producers or consumers, thereby can make the judgement of buffer status very accurately, reach the clock period level.
According to one embodiment of present invention, in conjunction with Fig. 4, Fig. 7 and Fig. 1, memory management unit of the present invention and buffer memory management method are used for application scenarios shown in Figure 1.The producer's the presynchronization signal prepsync signal of writing sends after the producer is dealt into the write order of a synchronization granularity on the bus.In other embodiments of the invention, also can be opportunity the producer send to first write order before the bus in the transmission of writing presynchronization signal prepsync signal, or after a part of write order sends to bus.Consumer's the presynchronization signal precsync signal of reading sends after the consumer is dealt into the read command of a synchronization granularity on the bus.In other embodiments of the invention, read presynchronization signal precsync signal and also can be the consumer first read command is sent to before the bus, or after a part of read command sends to bus.
When initial, buffer memory is empty, and memory management unit provides writes status signal pstatus signal for high, and the expression producer can be to cache writing data, and status signals cstatus signal is low, and the expression consumer can not be from the buffer memory read data.
The producer sees that writing status signal pstatus signal is height, continue to write data on the bus, the data volume size is a synchronization granularity, and in the end data the time, or afterwards, sending and keeping a clock period is the high presynchronization signal prepsync signal of writing, and the notice memory management unit is dealt into the write data of a synchronization granularity on the bus.
Whether memory management unit is write the management of the laggard row cache of presynchronization signal prepsyncp receiving, and provide in the next clock period and to allow the producer to continue to write status signal pstatus signal to cache writing data.If buffer memory inside also has living space, then the producer can continue to have reached the effect of streamline to cache writing data.
The producer is after the data of guaranteeing a synchronization granularity size are all write buffer memory, will send also that to keep a clock period be the high synchronizing signal psync signal of writing to memory management unit, the notice memory management unit is write the write data of a synchronization granularity in the buffer memory.
Memory management unit is write the management of the laggard row cache of synchronizing signal psync signal receiving, and provides the status signals cstatus signal that whether allows consumer's read data in the Buffer in the next clock period.In this example, status signals is the status height.
The consumer sees that status signals cstatus signal is for high, to continue to send read command, the order number is a synchronization granularity, and in the end read command data the time (or afterwards) send that to keep a clock period be the high presynchronization signal precsync signal of reading, the notice memory management unit is dealt into the read command of a synchronization granularity on the bus.
Whether memory management unit is read the management of the laggard row cache of presynchronization signal precsync signal receiving, and provide in the next clock period and to allow the consumer to continue status signals cstatus signal from the buffer memory read data.If buffer memory inside also has enough data, then the consumer can continue to have reached the effect of streamline from the buffer memory read data.
The consumer is after the data of guaranteeing a synchronization granularity size are all read consumer inside from buffer memory, will send also that to keep a clock period be the high synchronizing signal csync signal of reading to memory management unit, the notice memory management unit is postponed access in the consumer with the read data of a synchronization granularity.
Memory management unit is read the management of the laggard row cache of synchronizing signal csync signal receiving, and the next clock period provide whether allow the producer in buffer memory write data write status signal pstatus signal.
According to one embodiment of present invention, in conjunction with Fig. 4, Fig. 7 and Fig. 2, memory management unit of the present invention and buffer memory management method are used for application scenarios shown in Figure 2.The producer need write the buffer memory by read data on bus again.The producer writes presynchronization signal prepsync signal and can send after the producer is dealt into the read command of a synchronization granularity on the bus, or the producer sends read the data of a synchronization granularity from bus after, or the like.The producer write presynchronization signal prepsync signal can with read synchronizing signal csync signal and send simultaneously.
The producer's the presynchronization signal prepsync signal of writing sends after the producer is dealt into the write order of a synchronization granularity on the bus.Consumer's the presynchronization signal precsync signal of reading sends after the consumer is dealt into the read command of a synchronization granularity on the bus.
When initial, buffer memory is empty, and what memory management unit provided writes status signal pstatus signal for high, and the expression producer can be to cache writing data, and status signals cstatus signal is low, and the expression consumer can not be from the buffer memory read data.
The producer sees that writing status signal pstatus signal is height, begin to produce data, read data on the bus for example, the data volume size is a synchronization granularity, and producing last data, when perhaps last read command or last read data return or the like or send afterwards that to keep a clock period be the high presynchronization signal prepsync signal of writing, the notice memory management unit has produced the write data of a synchronization granularity.
Whether memory management unit is write the management of the laggard row cache of presynchronization signal prepsync signal receiving, and provide in the next clock period and to allow the producer to continue to write status signal pstatus signal to cache writing data.If buffer memory inside also has living space, then the producer can continue to have reached the effect of streamline to cache writing data.
The producer is after the data of guaranteeing a synchronization granularity size are all write buffer memory, as write operation, will send also that to keep a clock period be the high synchronizing signal psync signal of writing to memory management unit, the notice memory management unit is write the write data of a synchronization granularity in the buffer memory.
Memory management unit is write the management of the laggard row cache of synchronizing signal psync signal receiving, and provides the status signals cstatus signal that whether allows consumer's read data in the buffer memory in the next clock period.
The consumer sees that status signals cstatus signal is for high, to continue to send read command, the order number is a synchronization granularity, and in the end read command data the time or send afterwards that to keep a clock period be the high presynchronization signal precsync signal of reading, the notice memory management unit sends the read command of a synchronization granularity.
Whether memory management unit is read the management of the laggard row cache of presynchronization signal precsync signal receiving, and provide in the next clock period and to allow the consumer to continue status signals cstatus signal from the buffer memory read data.If buffer memory inside also has enough data, then the consumer can continue to have reached the effect of streamline from the buffer memory read data.
The consumer is after the data of guaranteeing a synchronization granularity size are all read consumer inside from buffer memory, will send also that to keep a clock period be the high synchronizing signal csync signal of reading to memory management unit, the notice memory management unit is postponed access in the consumer with the read data of a synchronization granularity.
Memory management unit is read the management of the laggard row cache of synchronizing signal csync signal receiving, and the next clock period provide whether allow the producer in buffer memory write data write status signal pstatus signal.
The present invention is not limited to the elaboration that embodiment does, and anyly all should be encompassed within the spirit and scope of claim of the present invention based on modification of the present invention and equivalent of the present invention.
Claims (13)
1. memory management unit comprises:
State calculation circuit in order to the valid data in the buffer memory are calculated, and calculates buffer status according to the valid data value;
Condition indication circuit is in order to export to buffer status the producer and/or consumer;
Write synchronizing circuit, when the producer really writes a secondary data in the buffer memory at every turn, send one and write synchronizing signal state calculation circuit is write synchronous operation;
Read synchronizing circuit, when the consumer receives in the buffer memory secondary data at every turn, send one and read synchronizing signal state calculation circuit is read synchronous operation;
Write the presynchronization circuit, when the producer sends a write order at every turn, send one and write the presynchronization signal state calculation circuit is write presynchronization operation;
Read the presynchronization circuit, when the consumer sends a read command at every turn, send one and read the presynchronization signal state calculation circuit is read presynchronization operation.
2. memory management unit as claimed in claim 1, it is characterized in that, described state calculation circuit comprises according to described to be write the presynchronization signal and reads first counter that the buffer memory valid data are write in synchronizing signal calculating, and reads the presynchronization signal and write second counter that the buffer memory valid data are read in synchronizing signal calculating according to described.
3. memory management unit as claimed in claim 2, it is characterized in that, described state calculation circuit also comprises according to described to be write the buffer memory valid data and writes first comparator circuit that max-thresholds obtains the state of writing of buffer memory, and according to described second comparator circuit of reading the buffer memory valid data and reading the read states of minimum threshold acquisition buffer memory, wherein, write max-thresholds and represent to allow the max-thresholds of the producer, read minimum threshold and represent to allow the minimum threshold of consumer from the buffer memory sense data to buffering write data.
4. as claim 2 or 3 described memory management units, it is characterized in that, the digit of described first counter and second counter is the size of synchronization granularity, and this synchronization granularity writes the data volume of a secondary data or the consumer reads a secondary data from buffer memory data volume for the producer to buffer memory.
5. memory management unit as claimed in claim 4 is characterized in that described synchronization granularity is fixed.
6. memory management unit as claimed in claim 4 is characterized in that described synchronization granularity changes.
7. memory management unit as claimed in claim 4 is characterized in that the data volume N that the producer writes a secondary data to buffer memory fixes, and the consumer fixes from the data volume M of cache read one secondary data, and data volume N is identical with data volume M or have a proportionate relationship.
8. memory management unit as claimed in claim 4, it is characterized in that, the described presynchronization signal of writing is to send after the producer is dealt into the write order of a synchronization granularity on the bus, or before the producer sends to bus with first write order, or a part of write order sends to and sends after the bus.
9. memory management unit as claimed in claim 4, it is characterized in that, the described presynchronization signal of reading is to send after the consumer is dealt into the read command of a synchronization granularity on the bus, or before the consumer sends to bus with first read command, or a part of read command sends to and sends after the bus.
10. memory management unit as claimed in claim 4 is characterized in that, described writing comprises the information of writing a data synchronization granule size in the presynchronization signal, describedly reads to comprise in the presynchronization signal information of reading a data synchronization granule size.
11. a buffer memory management method comprises the steps:
When memory management unit allowed to write data, the producer sent to memory management unit and writes the presynchronization notice;
Memory management unit receive effectively write presynchronization notice after, calculate the useful space of buffer memory according to writing the presynchronization notice, and feed back to the producer;
After the producer really writes a secondary data in the buffer memory, send to memory management unit and to write synchronization notice;
Memory management unit receives to be write after the synchronization notice, calculates the valid data of buffer memory, and feeds back to the consumer;
When memory management unit allowed reading of data, the consumer sent to memory management unit and reads the presynchronization notice;
Memory management unit receive effectively read presynchronization notice after, calculate the valid data of buffer memory according to reading the presynchronization notice, and feed back to the consumer;
After the consumer really reads a secondary data among the consumer, send to memory management unit and to read synchronization notice;
Memory management unit receives to be read after the synchronization notice, calculates the useful space of buffer memory, and feeds back to the producer.
12. a buffer memory management method comprises the steps:
When memory management unit allowed to write data, the producer sent to memory management unit and writes the presynchronization notice;
Memory management unit receive effectively write presynchronization notice after, calculate the useful space of buffer memory according to writing the presynchronization notice, and feed back to the producer;
After the producer really writes a secondary data in the buffer memory, send to memory management unit and to write synchronization notice;
Memory management unit receives to be write after the synchronization notice, calculates the valid data of buffer memory, and feeds back to the consumer.
13. a buffer memory management method comprises the steps:
When memory management unit allowed reading of data, the consumer sent to memory management unit and reads the presynchronization notice;
Memory management unit receive effectively read presynchronization notice after, calculate the valid data of buffer memory according to reading the presynchronization notice, and feed back to the consumer;
After the consumer really reads a secondary data among the consumer, send to memory management unit and to read synchronization notice;
Memory management unit receives to be read after the synchronization notice, calculates the useful space of buffer memory, and feeds back to the producer.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102203753A (en) * | 2011-05-23 | 2011-09-28 | 华为技术有限公司 | Data writing processing method, apparatus and terminal equipment |
| CN102404223A (en) * | 2011-11-28 | 2012-04-04 | 曙光信息产业(北京)有限公司 | System and method for priority control on fine granularity of multi-application packet reception |
| CN102801605A (en) * | 2012-02-13 | 2012-11-28 | 北京星网锐捷网络技术有限公司 | Method and device for displaying information |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0123239B1 (en) * | 1994-07-06 | 1997-11-26 | 김주용 | Fifo memory |
| CN100438480C (en) * | 2005-11-23 | 2008-11-26 | 华为技术有限公司 | Buffer storage managing system and method thereof |
| CN100524323C (en) * | 2005-12-26 | 2009-08-05 | 北京中星微电子有限公司 | Data buffer storage unit and its implementing method |
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2007
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| CN102203753A (en) * | 2011-05-23 | 2011-09-28 | 华为技术有限公司 | Data writing processing method, apparatus and terminal equipment |
| CN102203753B (en) * | 2011-05-23 | 2014-04-16 | 华为技术有限公司 | Data writing processing method, apparatus and terminal equipment |
| CN102404223A (en) * | 2011-11-28 | 2012-04-04 | 曙光信息产业(北京)有限公司 | System and method for priority control on fine granularity of multi-application packet reception |
| CN102404223B (en) * | 2011-11-28 | 2015-03-25 | 曙光信息产业(北京)有限公司 | System and method for priority control on fine granularity of multi-application packet reception |
| CN102801605A (en) * | 2012-02-13 | 2012-11-28 | 北京星网锐捷网络技术有限公司 | Method and device for displaying information |
| CN104516832A (en) * | 2013-10-08 | 2015-04-15 | 国际商业机器公司 | Method for operating data processing system, data processing system and processor |
| CN104516832B (en) * | 2013-10-08 | 2018-06-12 | 格芯公司 | Method, data processing system and the processor of operating data processing system |
| CN107003937A (en) * | 2014-10-22 | 2017-08-01 | Netapp股份有限公司 | For the cache optimization technology of large-scale work data set |
| CN112153054A (en) * | 2020-09-25 | 2020-12-29 | 山东超越数控电子股份有限公司 | Method and system for realizing splicing cache with any byte length |
| CN115643205A (en) * | 2021-07-19 | 2023-01-24 | 平头哥(上海)半导体技术有限公司 | Communication control unit for data producing and consuming entities, and related devices and methods |
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