CN101123113A - Access method and control device for synchronous dynamic random access memory - Google Patents
Access method and control device for synchronous dynamic random access memory Download PDFInfo
- Publication number
- CN101123113A CN101123113A CNA2007100461455A CN200710046145A CN101123113A CN 101123113 A CN101123113 A CN 101123113A CN A2007100461455 A CNA2007100461455 A CN A2007100461455A CN 200710046145 A CN200710046145 A CN 200710046145A CN 101123113 A CN101123113 A CN 101123113A
- Authority
- CN
- China
- Prior art keywords
- read
- write
- address
- dynamic random
- random access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Dram (AREA)
Abstract
The invention discloses a synchronized dynamic random access memory access method and a control device in a digital integrated circuit system. The invention first stores the read and write event description information sent by a user, then sets the initial address of the read and write event description information as the target address of the SDRAM read or write command, activates the storing row in the storing matrix appointed by the target address, sends a read or write command to SDRAM, updates the target address of the read or write command and the accumulated number of visited units, and then detects whether next visit requires closing the storing row of the present storing matrix. If required, a close command is sent, then the storing row in the storing matrix appointed by the new target address is activated, and a new round of visit is started; if not required, a close command is not needed before a new round of visit. The invention allows the user to appoint an address increment when suddenly visiting an external memory, so as to adapt the requirements on address increment when suddenly visiting an external memory in the circuit system.
Description
Technical field
The present invention relates to the method and the device in a kind of digital circuit technique field, specifically is a kind of access method and control device of synchronous dynamic random access memory.
Background technology
Synchronous dynamic random access memory (SDRAM) is right and wrong usefulness usually in the digital integrated circuit system; the speed of SDRAM is generally slow than SRAM (static random-access memory), and the bandwidth of access sdram is a key and a difficult point in the digital integrated circuit (IC) system design through regular meeting.Want certain basic unit of storage in the access sdram, certain storage line in certain storage array among the SDRAM at this basic unit of storage place of activation if having another storage line opening in this storage array before this, must be closed it earlier earlier.Activating and closing these actions all needs the regular hour to finish, reduce this part time occupied ratio in whole access sdram process, just real data transmission period occupied ratio in whole access sdram process can be improved, the efficient of access sdram can be improved.
Prior art is when access sdram, and its burst-length can only be set at limited several length that the SDRAM chip is supported, such as 1,2, and 4,8 or the full page formula.Though the mode of burst access can improve the access efficiency of storer effectively, the burst-length option that the SDRAM chip is provided very little, and length is shorter, is not enough to support the situation of high memory bandwidth requirements.In addition, order according to visit basic unit of storage in the burst access, the SDRAM chip is only supported increment type and the burst access of two types on the type of interweaving, the burst access class limitations of underaction the adaptable occasion of burst access, thereby reduce memory access efficient.
Literature search through prior art finds that the article " SDRAM controller for real timedigital image processing systems " (being applicable to the controller of the synchronous dynamic random access memory of real-time digital image treatment system) that the people such as Tomasz Szymanski deliver namely adopts prior art on VI-thInternational Conference the Experience of Designning and Application ofCAD Systems in Microelecronics (design of the 4th microelectronic computer aided design system and application experience International Academic Conference). This system mainly is divided into four parts, is responsible for initialization respectively, refresh, and the control of read and write, the control section of its core--read and write is decided to be increment type to the burst access type, and burst-length is decided to be 4, to improve reference-to storage efficient.Although compare burst-length and be the visit of 1 single basic unit of storage, the efficient of this sdram controller increases to some extent, and for the design of the contour external memory storage bandwidth requirement of for example Video Decoder, such efficient still is nowhere near.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, the access method and the control device of a kind of synchronous dynamic random access memory (SDRAM) is provided.The present invention allows SDRAM user to describe visiting demand to SDRAM with one group of read-write affairs descriptor, send a series of SDRAM according to this group read-write affairs descriptor to SDRAM then and order the visiting demand of finishing SDRAM, can improve the efficient of access sdram significantly.
The present invention is achieved by the following technical solutions:
The access method of the synchronous dynamic random access memory that the present invention relates to specifically may further comprise the steps:
The first step obtains Client-initiated read-write affairs descriptor, comprises read-write transactions access type (reading or writing), read-write affairs start address S, read-write transaction address increment I and read-write affairs burst-length L;
In second step, setting read-write affairs start address S is SDRAM destination address A, and destination address A is by storage array (bank) address BA, and storage line (row) address RA and basic unit of storage (col) address CA form;
In the 3rd step, storage array address BA that is implied in destination address A and storage line address RA send activation command;
The 4th step, after waiting for the time of the desired necessity of SDRAM chip, send read command according to the specified access type of the information of read-write affairs and the addressed location that is arranged in destination address A among the SDRAM is sent to the user or sends write order the destination address A place that the addressed location that the user is provided deposits SDRAM in; Setting new SDRAM destination address simultaneously is that former SDRAM destination address adds read-write transaction address increment A=A+I and upgrades the addressed location quantity that accumulative total is visited;
The 5th step, detect according to destination address A whether needs send necessary shutdown command, then send if desired; The criterion that detects is, if the addressed location quantity of accumulative total visit equal to read and write the burst-length of affairs or upgrade BA among the destination address A of back in the 4th step or the RA part with upgrade before BA or RA part among the destination address A different, then being judged to needs to send shutdown command; Otherwise repeated for the 4th step;
In the 6th step, after the time of the desired necessity of wait SDRAM chip, repeat the 3rd to the 5th step equaled to read and write affairs up to the addressed location quantity of accumulative total visit burst-length.
Described SDRAM can be SDR (haploidy number is according to speed) SDRAM, a kind of among DDR (Double Data Rate) SDRAM or DDR2 (2 generations of the Double Data Rate) SDRAM.
Described addressed location is meant the combination of the SDRAM chip being sent the basic unit of storage that once reads or writes order and had access to, and equals the basic unit of storage to the specified quantity of burst-length of SDRAM configuration.Addressed location can transmit in several cycles and finish, if haploidy number is according to the SDRAM of speed, then transmitted the needed cycle book of addressed location and equaled burst-length to SDRAM configuration, if the SDRAM of Double Data Rate, then transmitted the needed cycle book of addressed location and equaled half to the burst-length of SDRAM configuration.
The invention still further relates to a kind of control device of synchronous dynamic random access memory, promptly sdram controller comprises the information register heap, three modules of finite state machine and command decoder.The information register heap is gathered the read-write affairs descriptor of outside input, these information are outputed to finite state machine and in handling the process of whole read-write affairs, remain unchanged, finish signal up to receiving the read-write affairs that finite state machine sends out, just empty the information register heap.Finite state machine comes into operation after receiving the read-write affairs descriptor of piling from information register, and it is responsible for producing the address that a series of SDRAM orders and these orders are acted on according to read-write affairs descriptor, sends command decoder to; After finishing the described visiting demand of read-write affairs descriptor, transmission read-write affairs are finished signal and are piled to information register.Command decoder receives behind the address that is acted on from the SDRAM of finite state machine order and these orders the address that these command translations is become order wire signal that the SDRAM chip can discern and these orders are acted on and outputs to the SDRAM chip together.
Described information register heap comprises read-write transactions access type register, read-write affairs initial address register, and read-write transaction address increment register and read-write affairs burst-length register be totally four registers.The input data of read-write transactions access type register are the read-write transactions access type signals in the read-write affairs descriptor of SDRAM user's input; The input data of read-write affairs initial address register are the read-write affairs starting address signals in the read-write affairs descriptor of SDRAM user's input; The input data of read-write transaction address increment register are the read-write transaction address increment signals in the read-write affairs descriptor of SDRAM user's input; The input data of read-write affairs burst-length register are the read-write affairs burst length signal in the read-write affairs descriptor of SDRAM user's input; Above-mentioned four registers are responsible for gathering and preserving every descriptor of read-write affairs in the processing procedure of whole read-write affairs, send finite state machine then to, make the usefulness of the foundation of state exchange for finite state machine.When limited state machine sent the read-write affairs and finishes signal and pile to information register, above-mentioned four registers all emptied.
The input signal of described finite state machine is the read-write affairs descriptor from the input of information register heap, comprises read-write transactions access type, read-write affairs start address, read-write transaction address increment and read-write affairs burst-length.Finite state machine produces a series of output signals to finish the described request of access of this information according to read-write affairs descriptor.The output signal of finite state machine comprises that the read-write affairs that output to information register heap finish signal, output to the SDRAM order of command decoder, the storage array address BA that comprises read command, write order, activation command and shutdown command and output to command decoder equally, storage line address RA and basic unit of storage address CA.
Described finite state machine comprises Current Address Register (cur_addr), residue burst-length register (cur_bl), interim storage array address register (BA_tmp), interim storage line address register (RA_tmp) and major state register (state) totally five status registers.
The residing state of described major state register (state) expression finite state machine comprises read states, writes state, state after the state of activation, closed condition, activation, closes back state and idle condition, altogether seven states.When whole device resets, major state register (state) is in idle condition, when detecting from the read-write transactions access type signal in the read-write affairs descriptor of information register heap to effectively reading or writing rather than during sky, major state register (state) enters state of activation from idle condition, when being in state of activation, BA that is implied among finite state machine output activation command and the cur_addr and RA are to command decoder, and state of activation is only kept one-period; Next cycle state enters the back state that activates at once, wait for that several cycles are after the time interval of the desired necessity of SDRAM chip satisfies, state enters the state of writing or read states according to the read-write transactions access type decided in the read-write affairs descriptor, when being in the state of writing or read states, finite state machine sends the CA that implied among read command or write order and the cur_addr to command decoder, simultaneously cur_addr and cur_bl or upgrade.The state that state determines following one-period according to the cur_addr that upgrades and cur_bl, if cur_bl equals 0, then send the read-write affairs and finish signal, the read-write task has been finished in expression, if cur_bl is not equal to 0, then relatively among the cur_addr implicit BA and RA with preserve the BA that implied before the cur_bl renewal and BA_tmp and the RA_tmp register of RA respectively, if BA or RA are inequality, then state enters closed condition following one-period, if BA is identical with RA, then next cycle still keeps original read states or writes state; When being in closed condition, finite state machine sends shutdown command and BA_tmp and RA_tmp to command decoder, and closed condition is only kept one-period; Next cycle state enters at once and closes the back state, waits for several cycles after the time interval of the desired necessity of SDRAM chip satisfies, and state enters state of activation once more, forms circulation thus, finishes signal up to the read-write affairs and is issued.
Described Current Address Register (cur_addr) is when finite state machine detects information register heap and sends effective read-write affairs descriptor, deposit read-write affairs starting address signal wherein, when being in read states or writing state, finite state machine increases progressively the read-write transaction address increment of incremental change then for from the information register heap, sending here.It is in order to obtain the address of next SDRAM addressed location that cur_addr increases progressively.Cur_addr has comprised storage array address BA, storage line address RA and three fields of basic unit of storage address CA, when so cur_addr upgrades, these three fields have equally also been upgraded, BA and RA can send to command decoder when finite state machine is in state of activation or closed condition, BA and CA can send to command decoder when finite state machine is in read states or writes state.
Described residue burst-length register (cur_bl) is when finite state machine detects information register heap and sends effective read-write affairs descriptor, deposit read-write affairs burst length signal wherein, when finite state machine is in read states or writes state, successively decrease 1 then.It is for the request of access that has sent is counted that cur_bl successively decreases, when the request of access number that sends reaches read-write affairs burst-length, the value that promptly remains in the burst-length register is 0 o'clock, and the current read-write of expression affairs have been finished, and at this moment finite state machine should enter closed condition.
Described interim storage array address register (BA_tmp) and interim storage line address register (RA_tmp) are when finite state machine is in read states or writes state, deposit BA part and RA part in the one-period Current Address Register (cur_addr), be used for partly comparing with BA part and the RA of this cycle cur_addr, be not equal at cur_bl under 0 the situation, if BA_tmp is different with BA or RA_tmp is different with RA, then finite state machine need enter closed condition, otherwise finite state machine keeps original read states or writes state.After entering closed condition, finite state is confidential to send shutdown command to command decoder, sends the storage array that the value in the BA_tmp has been specified shutdown command and acted on to command decoder simultaneously.
Described command decoder comprises a code translator, a selector switch, one or and a storage array address register.The input signal of code translator is the SDRAM order from finite state machine, comprises read command, write order, activation command and shutdown command, the command signal that code translator can be discerned its decoding output SDRAM chip; Or the input of door is read command signal and write command signal from finite state machine, and output is as the selection signal of selector switch; The input data of selector switch are from the storage line address RA of finite state machine and basic unit of storage address CA, the selection signal of input selector is or the output of door that selector switch is the address signal ADDR that outputs to the SDRAM chip according to selecting signal to select RA or CA; The input data of storage array address register are the storage array address signal BA from finite state machine, and the storage array address register plays preserves one-period to BA, delivers to the SDRAM chip with ADDR in the same cycle then.
The method that the present invention proposes a kind of access sdram efficiently improve and SDRAM between data transmission efficiency.The present invention allows SDRAM user to describe visiting demand to SDRAM with one group of read-write affairs descriptor, sends a series of SDRAM according to this group read-write affairs descriptor to SDRAM then and orders the visiting demand of finishing SDRAM.
The present invention can improve the efficient of access sdram significantly, all considers under the situation of an activation command in each burst access, and under the 166MHz situation, activation command needs three cycles.Even the prior art access efficiency is made as the highest by 8, also can only reach 72.7%.Adopt the present invention, the length of burst access can be very long, not necessarily is subject to the burst access of the basic unit of storage of neighbor address simultaneously, so just strengthened the adaptability of burst access, makes it to follow to be employed easily, thereby improved the efficient of access sdram.
Description of drawings
Fig. 1 is the position view of sdram controller;
Fig. 2 is the state transitions synoptic diagram of finite state machine;
Fig. 3 is the synoptic diagram that has the image among the SDRAM with different address increment burst access;
Fig. 4 is a sdram controller inner structure block diagram;
Fig. 5 is a command decoder inner structure synoptic diagram.
Specific implementation
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment has provided detailed embodiment and process being to implement under the prerequisite with the technical solution of the present invention, but protection scope of the present invention is not limited to following embodiment.
Below describe the embodiment of the present invention when access images in detail.
The method of present embodiment, at first deposit down the read-write affairs descriptor that the user sends, to read and write the destination address that read-write affairs start address in the affairs descriptor is set at SDRAM read command or write order then, activate the storage line in the specified storage array of this destination address, send read command or write order and upgrade read command or the quantity of the addressed location of the destination address of write order and accumulative total visit to SDRAM again, next detect and visit the storage line that whether needs to close in the current storage array next time, then send shutdown command if desired, and then activate the storage line in the specified storage array of new destination address and carry out the visit of a new round, if do not need to send shutdown command then directly visit next addressed location.
The control device of access synchronized dynamic RAM comprises information register heap, three modules of finite state machine and command decoder (Fig. 4) in the present embodiment.
The information register heap comprises read-write transactions access type register, read-write affairs initial address register, and read-write transaction address increment register and read-write affairs burst-length register be totally four registers.The input signal of information register heap comprises that the read-write affairs descriptor of SDRAM user's input and the read-write affairs of finite state machine module input finish signal.Described read-write affairs descriptor comprises read-write transactions access type, read-write affairs start address, read-write transaction address increment and read-write affairs burst-length.Information register heap output read-write affairs descriptor is to finite state machine module (Fig. 4).The workflow of information register heap is as follows: when finding that SDRAM user sends request of access and information register heap idle the time, deposits above-mentioned read-write affairs descriptor in the relevant register, and sends finite state machine to.After finite state machine was finished the desired read-write task of these read-write affairs, the signal that transmission read-write affairs are finished the work was piled to information register.Information register heap receives after read-write affairs that finite state machine sends finish signal, and all register zero clearings, expression information register heap is in idle condition.
Finite state machine comprises Current Address Register (cur_addr), residue burst-length register (cur_bl), interim storage array address register (BA_tmp), interim storage line address register (RA_tmp) and major state register (state) totally five status registers.Finite state machine comprises read states, writes state, state of activation, and closed condition activates the back state, closes back state and idle condition, altogether seven states (Fig. 2).The input signal of finite state machine is the read-write affairs descriptor from the information register heap, comprises read-write transactions access type, read-write affairs start address, read-write transaction address increment and read-write affairs burst-length.The output signal of finite state machine comprises that the read-write affairs that output to information register heap finish signal, output to the SDRAM order of command decoder, comprise read command, write order, activation command and shutdown command and the storage array address BA that outputs to command decoder equally, storage line address RA and basic unit of storage address CA (Fig. 4).The workflow of finite state machine following (Fig. 2): major state register (state) is initially located in idle condition, when detecting from the read-write transactions access type signal in the read-write affairs descriptor of information register heap to reading or writing rather than during sky, Current Address Register (cur_addr) is deposited the read-write affairs starting address signal in the read-write transaction information, comprising BA, RA and CA, residue burst-length register (cur_bl) is deposited the read-write affairs burst length signal in the read-write transaction information, major state register (state) enters state of activation from idle condition, when being in state of activation, BA that is implied among finite state machine output activation command and the cur_addr and RA are to command decoder, and state of activation is only kept one-period; Next cycle state enters the back state that activates at once, wait for that several cycles are after the time interval of the desired necessity of SDRAM chip satisfies, state enters the state of writing or read states according to the read-write transactions access type decided in the read-write affairs descriptor, when being in the state of writing or read states, finite state machine sends the CA that implied among write order or read command and the cur_addr to command decoder, cur_addr is from the read-write transaction address increment that increases in the read-write affairs descriptor simultaneously, and cur_bl is from subtracting 1; When being in read states or writing state, the state that finite state machine determines following one-period according to the cur_addr that upgrades and cur_bl, if cur_bl equals 0, then send the read-write affairs and finish signal, the read-write task has been finished in expression, if cur_bl is not equal to 0, then compare the BA and the RA that are implied before BA implicit among the cur_addr and RA and cur_bl upgrade, RA is inequality if BA is identical, represent that then next addressed location is in the different storage lines of same storage array, must close this storage array earlier, promptly state enters closed condition following one-period, preserve the BA that implied before cur_addr upgrades and RA simultaneously to BA_tmp and RA_tmp, if BA difference, no matter whether RA is identical, represent that then next addressed location is in another storage array, in order to simplify finite state machine, so also allow state enter closed condition in this case, preserve the BA that implied before cur_addr upgrades and RA simultaneously to BA_tmp and RA_tmp, if BA is identical with RA, then next cycle still keeps original read states or writes state; When being in closed condition, finite state machine sends shutdown command and BA_tmp and RA_tmp to command decoder, and closed condition is only kept one-period; Next cycle state enters at once and closes the back state, waits for several cycles after the time interval of the desired necessity of SDRAM chip satisfies, and state enters state of activation once more, forms circulation thus, finishes signal up to the read-write affairs and is issued.
Command decoder comprises a code translator, a selector switch, one or and a storage array address register.The input signal of command decoder comprises SDRAM order and storage array address BA, storage line address RA and the basic unit of storage address CA of finite state machine input.The output signal of command decoder comprises the command signal that the SDRAM chip that outputs to the SDRAM chip can be discerned, the storage array address BS (Fig. 4) of SDRAM address AD DR and SDRAM.The workflow of command decoder is as follows: after the SDRAM order of finite state machine input enters code translator, be translated as the command signal that the SDRAM chip can be discerned; The storage array address BA of finite state machine input after depositing as the output of command decoder; The SDRAM command signal input selector of finite state machine input, if this order is read command or write order, then the output SDRAM address AD DR of command decoder equals CA, otherwise equals RA.
In the present embodiment, suppose that certain Video Decoder will read a width of cloth with the form of vertical burst and have that width is n among the SDRAM, length is the limit (Fig. 3) on the longitudinal direction in the image of m addressed location, this device is in system between Video Decoder and the SDRAM chip (Fig. 1), Video Decoder installs to this, it is the request that sdram controller sends the access sdram chip that comprises read-write affairs descriptor, sdram controller sends the order that a series of SDRAM chips institute can discern according to read-write affairs descriptor and gives the SDRAM chip, finishes the requirement of reading and writing the described reference-to storage of affairs descriptor.Detailed process is as follows:
First step Video Decoder initiates to comprise the request of read-write affairs descriptor, and read-write affairs descriptor comprises read-write transactions access type, read-write affairs start address S, read-write transaction address increment n and read-write affairs burst-length L.The information register heap of sdram controller is received after the request of Video Decoder, deposits down above-mentioned information (Fig. 4);
The second step information register heap is passed to finite state machine (Fig. 4) with the read-write affairs descriptor of being deposited, and it is S that finite state machine is set temporary address register cur_addr, and residue burst-length register cur_bl is L, and finite state machine is started working;
The 3rd step major state register (state) enters state of activation (Fig. 2) from idle condition, storage array address BA and the storage line address RA of finite state machine in command decoder transmission activation command and cur_addr, state of activation is only kept one-period, and next cycle major state register (state) enters the back state (Fig. 2) that activates; Command decoder receives (Fig. 4) behind activation command and BA and the RA, code translator is translated into the activation command that the SDRAM chip can be discerned with activation command, the storage array address register is deposited down BA, selector switch is composed the signal of storage line address RA to address AD DR (Fig. 5) according to being the selection signal of 0 value;
After the time restriction of the desired necessity of the 4th step wait SDRAM chip satisfied, major state register (state) was read or writes according to the read-write transactions access type signal in the read-write affairs descriptor to determine that entering read states still writes state (Fig. 2); Finite state machine sends the reading of corresponding major state buffer status (read) to command decoder and orders or write basic storage array element address CA among (write) order and the cur_addr; Preserve BA part among the cur_addr simultaneously in interim storage array address register BA_tmp, the RA part is in interim storage line address register RA_tmp; Upgrading cru_addr is that former cur_addr adds read-write transaction address increment cur_addr=cur_addr+I; Upgrade the remaining addressed location quantity cur_bl=cur_bl-1 that will visit; Command decoder receives (Fig. 4) behind read command or write order and the CA, code translator with read command or write order translate into read command or the write order that the SDRAM chip can be discerned, selector switch is composed basic unit of storage address CA to address AD DR (Fig. 5) according to being the selection signal of 1 value;
If the 5th step finite state machine finds that cur_bl equals 0, find that perhaps BA or RA part among the cur_addr are different with BA_tmp or RA_tmp part, then being judged as needs to send shutdown command, major state register (state) enters closed condition (Fig. 2), the storage array address BA of finite state machine in command decoder transmission shutdown command and cur_addr, closed condition is only kept one-period, next cycle major state register (state) enters the back state (Fig. 2) of cutting out, do not need to send shutdown command if be judged as, then repeated for the 4th step; Command decoder receives (Fig. 4) behind shutdown command and the BA, code translator is translated into the shutdown command that the SDRAM chip can be discerned with shutdown command, the storage array address register is deposited down BA, and selector switch is composed storage line address RA to address AD DR (Fig. 5) according to being the selection signal of 0 value;
After the 6th step waited for that the time restriction of the desired necessity of SDRAM chip satisfied, repeated for the 3rd to the 5th step and equal at 0 o'clock up to detecting cur_bl, finite state machine sends the read-write affairs to the information register heap and finishes signal (Fig. 4), and the information register heap empties.
So, once finished for vertical visit of image.
In Video Decoder, filtration module tends to visit the vertical pixel of a row of finishing filtering.Because the address of neighbor is not adjacent on vertical row's direction, surpass 1 burst access so can't carry out burst-length to it with prior art, and visit pixel that can only be single, at 166MHz with under the condition that needs once to activate, the efficient of reference-to storage has only 25%.And use the present invention can visit 16 pixels of a macro block easily, and under the similarity condition, the efficient of reference-to storage reaches 84.2%.
The Contrast on effect of the present invention and prior art sees the following form:
| Use the present invention and improve burst-length | Prior art can not improve burst-length | |
| Burst-length | Data transmission efficiency | |
| 1 | 25％ | 25％ |
| 2 | 40％ | 25％ |
| 3 | 50％ | 25％ |
| 4 | 57％ | 25％ |
| 5 | 62.5％ | 25％ |
| 6 | 66.7％ | 25％ |
| 7 | 70％ | 25％ |
| 8 | 72.7％ | 25％ |
| 9 | 75％ | 25％ |
| 10 | 76.9％ | 25％ |
| 11 | 78.6％ | 25％ |
| 12 | 80％ | 25％ |
| 13 | 81.25％ | 25％ |
| 14 | 82.4％ | 25％ |
| 15 | 83.3％ | 25％ |
| 16 | 84.2％ | 25％ |
Claims (10)
1. the access method of a synchronous dynamic random access memory is characterized in that, comprises the steps:
The first step obtains Client-initiated read-write affairs descriptor, comprises read-write transactions access type, read-write affairs start address S, read-write transaction address increment I and read-write affairs burst-length L;
In second step, setting read-write affairs start address S is synchronous dynamic random access memory destination address A, and destination address A is by storage array address BA, and storage line address RA and basic unit of storage address CA form;
In the 3rd step, storage array address BA that is implied in destination address A and storage line address RA send activation command;
The 4th step, after waiting for the time of the desired necessity of synchronous dynamic random access memory chip, send read command according to the specified access type of the information of read-write affairs and the addressed location that is arranged in destination address A in the synchronous dynamic random access memory is sent to the user or sends write order the destination address A place that the addressed location that the user is provided deposits synchronous dynamic random access memory in, setting new synchronous dynamic random access memory destination address simultaneously is the addressed location quantity that former synchronous dynamic random access memory destination address adds read-write transaction address increment A=A+I and the visit of renewal accumulative total;
The 5th step, detect according to destination address A whether needs send necessary shutdown command, then send if desired; The criterion that detects is, if the addressed location quantity of accumulative total visit equal to read and write the burst-length of affairs or upgrade BA among the destination address A of back in the 4th step or the RA part with upgrade before BA or RA part among the destination address A different, then being judged to needs to send shutdown command; Otherwise repeated for the 4th step;
In the 6th step, after the time of the desired necessity of wait synchronous dynamic random access memory chip, repeat the 3rd to the 5th step equaled to read and write affairs up to the addressed location quantity of accumulative total visit burst-length.
2. the access method of synchronous dynamic random access memory according to claim 1, it is characterized in that, described synchronous dynamic random access memory be haploidy number according to the synchronization of rate dynamic RAM, a kind of in Double Data Rate synchronous dynamic random access memory or the Double Data Rate 2 generation synchronous dynamic random access memory.
3. the access method of synchronous dynamic random access memory according to claim 1, it is characterized in that, described addressed location is meant the combination of the synchronous dynamic random access memory chip being sent the basic unit of storage that once reads or writes order and had access to, and equals the basic unit of storage to the specified quantity of burst-length of synchronous dynamic random access memory configuration.
4. according to the access method of claim 1 or 2 or 3 described synchronous dynamic random access memories, it is characterized in that, described addressed location transmits in several cycles and finishes, if haploidy number is according to the synchronous dynamic random access memory of speed, then transmitted the needed cycle book of addressed location and equaled burst-length to synchronous dynamic random access memory configuration, if the synchronous dynamic random access memory of Double Data Rate, then transmitted the needed cycle book of addressed location and equaled half to the burst-length of synchronous dynamic random access memory configuration.
5. the control device of a synchronous dynamic random access memory, it is characterized in that, comprise information register heap, finite state machine and command decoder, described information register heap is gathered the read-write affairs descriptor of outside input, these information are outputed to finite state machine and in handling the process of whole read-write affairs, remain unchanged, finish signal up to receiving the read-write affairs that finite state machine sends out, just empty the information register heap; After described finite state machine receives the read-write affairs description of piling from information register, come into operation, it is responsible for describing the address that a series of SDRAM of generation orders and these orders are acted on according to the read-write affairs, send command decoder to, after finishing read-write affairs describe described visiting demand, send the read-write affairs and finish signal and pile to information register; Described command decoder receives behind the address that order is acted on from the synchronous dynamic random access memory order of finite state machine and these and these command translations to be become order wire signal that the synchronous dynamic random access memory chip can discern and these order the address that is acted on to output to the synchronous dynamic random access memory chip together.
6. the control device of synchronous dynamic random access memory according to claim 5, it is characterized in that, described information register heap comprises read-write transactions access type register, read-write affairs initial address register, read-write transaction address increment register and read-write affairs burst-length register, wherein:
The input data of described read-write transactions access type register are the read-write transactions access type signals in the read-write affairs descriptor of synchronous dynamic random access memory user input;
The input data of described read-write affairs initial address register are the read-write affairs starting address signals in the read-write affairs descriptor of synchronous dynamic random access memory user input;
The input data of described read-write transaction address increment register are the read-write transaction address increment signals in the read-write affairs descriptor of synchronous dynamic random access memory user input;
The input data of described read-write affairs burst-length register are the read-write affairs burst length signal in the read-write affairs descriptor of synchronous dynamic random access memory user input;
Above-mentioned four registers are responsible for gathering and preserving every descriptor of read-write affairs in the processing procedure of whole read-write affairs, send finite state machine then to, make the usefulness of the foundation of state exchange for finite state machine, when limited state machine sent the read-write affairs and finishes signal and pile to information register, above-mentioned four registers all emptied.
7. the control device of synchronous dynamic random access memory according to claim 5, it is characterized in that, described finite state machine, its input signal is the read-write affairs descriptor from the input of information register heap, comprise read-write transactions access type, read-write affairs start address, read-write transaction address increment and read-write affairs burst-length, finite state machine produces a series of output signals to finish the described request of access of this information according to read-write affairs descriptor, the output signal of finite state machine comprises that the read-write affairs that output to information register heap finish signal, output to the synchronous dynamic random access memory order of command decoder, comprise read command, write order, activation command and shutdown command and the storage array address BA that outputs to command decoder equally, storage line address RA and basic unit of storage address CA.
8. according to the control device of claim 5 or 7 described synchronous dynamic random access memories, it is characterized in that, described finite state machine comprises Current Address Register cur_addr, residue burst-length register cur_bl, interim storage array address register BA_tmp, interim storage line address register RA_tmp and major state register state totally five status registers, wherein:
Described major state register state represents the residing state of finite state machine, comprise read states, write state, state of activation, closed condition, activate the back state, close back state and idle condition totally seven states, when whole device resets, major state register state is in idle condition, when detecting from the read-write transactions access type signal in the read-write affairs descriptor of information register heap to effectively reading or writing rather than during sky, major state register state enters state of activation from idle condition, when being in state of activation, BA that is implied among finite state machine output activation command and the cur_addr and RA are to command decoder, state of activation is only kept one-period, next cycle state enters the back state that activates at once, wait for that several cycles are after the time interval of the desired necessity of synchronous dynamic random access memory chip satisfies, state enters the state of writing or read states according to the read-write transactions access type decided in the read-write affairs descriptor, when being in the state of writing or read states, finite state machine sends the CA that implied among read command or write order and the cur_addr to command decoder, simultaneously cur_addr and cur-bl or upgrade, the state that state determines following one-period according to the cur_addr that upgrades and cur_bl;
Described Current Address Register cur_addr is when finite state machine detects information register heap and sends effective read-write affairs descriptor, deposit read-write affairs starting address signal wherein, when being in read states or writing state, finite state machine increases progressively then, the read-write transaction address increment of incremental change for from the information register heap, sending here, it is in order to obtain the address of next SDRAM addressed location that cur_addr increases progressively, cur_addr has comprised storage array address BA, storage line address RA and three fields of basic unit of storage address CA, when so cur_addr upgrades, these three fields have equally also been upgraded, BA and RA can send to command decoder when finite state machine is in state of activation or closed condition, BA and CA can send to command decoder when finite state machine is in read states or writes state;
Described residue burst-length register cur_bl is when finite state machine detects information register heap and sends effective read-write affairs descriptor, deposit read-write affairs burst length signal wherein, when being in read states or writing state, finite state machine successively decreases 1 then, it is for the request of access that has sent is counted that cur_bl successively decreases, when the request of access number that sends reaches read-write affairs burst-length, the value that promptly remains in the burst-length register is 0 o'clock, the current read-write of expression affairs have been finished, and at this moment finite state machine should enter closed condition;
Described interim storage array address register BA_tmp and interim storage line address register RA_tmp are when finite state machine is in read states or writes state, deposit BA part and RA part among the one-period Current Address Register cur_addr, be used for partly comparing with BA part and the RA of this cycle cur_addr, be not equal at cur_bl under 0 the situation, if BA_tmp is different with BA or RA_tmp is different with RA, then finite state machine need enter closed condition, otherwise finite state machine keeps original read states or writes state, after entering closed condition, finite state is confidential to send shutdown command to command decoder, sends the storage array that the value in the BA_tmp has been specified shutdown command and acted on to command decoder simultaneously.
9. the control device of synchronous dynamic random access memory according to claim 8, it is characterized in that, the state that described major state register state determines following one-period according to the cur_addr that upgrades and cur_bl, be meant: if cur_bl equals 0, then send the read-write affairs and finish signal, the read-write task has been finished in expression, if cur_bl is not equal to 0, then relatively among the cur_addr implicit BA and RA with preserve the BA that implied before the cur_bl renewal and BA_tmp and the RA_tmp register of RA respectively, if BA or RA are inequality, then state enters closed condition following one-period, if BA is identical with RA, then next cycle still keeps original read states or writes state; When being in closed condition, finite state machine sends shutdown command and BA_tmp and RA_tmp to command decoder, closed condition is only kept one-period, next cycle state enters the back state of closing at once, wait for that several cycles are after the time interval of the desired necessity of SDRAM chip satisfies, state enters state of activation once more, forms circulation thus, finishes signal up to the read-write affairs and is issued.
10. the control device of synchronous dynamic random access memory according to claim 5 is characterized in that, described command decoder comprise a code translator, selector switch, one or and a storage array address register, wherein:
The input signal of described code translator is the synchronous dynamic random access memory order from finite state machine, comprise read command, write order, activation command and shutdown command, the command signal that code translator can be discerned its decoding output synchronous dynamic random access memory chip;
Input described or door is read command signal and the write command signal from finite state machine, and output is as the selection signal of selector switch;
The input data of described selector switch are from the storage line address RA of finite state machine and basic unit of storage address CA, the selection signal of input selector is or the output of door that selector switch is the address signal ADDR that outputs to the synchronous dynamic random access memory chip according to selecting signal to select RA or CA;
The input data of described storage array address register are the storage array address signal BA from finite state machine, the storage array address register plays preserves one-period to BA, delivers to the synchronous dynamic random access memory chip with ADDR in the same cycle then.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100461455A CN101123113B (en) | 2007-09-20 | 2007-09-20 | Access method and control device for synchronous dynamic random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100461455A CN101123113B (en) | 2007-09-20 | 2007-09-20 | Access method and control device for synchronous dynamic random access memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101123113A true CN101123113A (en) | 2008-02-13 |
| CN101123113B CN101123113B (en) | 2010-07-14 |
Family
ID=39085404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007100461455A Expired - Fee Related CN101123113B (en) | 2007-09-20 | 2007-09-20 | Access method and control device for synchronous dynamic random access memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101123113B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103337251A (en) * | 2012-01-09 | 2013-10-02 | 联发科技股份有限公司 | Dynamic random access memory and access method thereof |
| CN103810125A (en) * | 2012-11-12 | 2014-05-21 | 国际商业机器公司 | Active memory device gather, scatter, and filter |
| CN104778013A (en) * | 2014-01-15 | 2015-07-15 | 三星电子株式会社 | Method and device for tracking activations to rows of memory |
| CN106201363A (en) * | 2016-07-26 | 2016-12-07 | 四川大学 | The memorizer of the random real time access of video flowing Pixel-level data and storage method |
| CN103731313B (en) * | 2012-10-10 | 2017-07-14 | 华为技术有限公司 | Counter and its implementation based on DDR SDRAM |
| CN108139992A (en) * | 2016-08-09 | 2018-06-08 | 华为技术有限公司 | Access the method and storage device of storage device |
| CN108139994A (en) * | 2016-05-28 | 2018-06-08 | 华为技术有限公司 | Memory pool access method and Memory Controller Hub |
| CN108153485A (en) * | 2017-11-20 | 2018-06-12 | 天津津航技术物理研究所 | A kind of more equipment collaborations access the method and system of SRAM |
| CN111033623A (en) * | 2017-07-31 | 2020-04-17 | 美光科技公司 | Data state synchronization |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112783519A (en) * | 2019-11-04 | 2021-05-11 | 航天科工惯性技术有限公司 | Application program updating method and system for measuring pup joint |
| CN112965816A (en) * | 2020-07-17 | 2021-06-15 | 华为技术有限公司 | Memory management technology and computer system |
| CN114563995A (en) * | 2022-01-17 | 2022-05-31 | 潍柴动力股份有限公司 | Reset detection method, device and equipment of electronic control unit and storage medium |
| WO2022111013A1 (en) * | 2020-11-27 | 2022-06-02 | 安徽寒武纪信息科技有限公司 | Device supporting multiple access modes, method and readable storage medium |
| CN115081366A (en) * | 2022-06-13 | 2022-09-20 | 杭州云合智网技术有限公司 | Modeling method for burst access of register |
| CN115148015A (en) * | 2022-06-30 | 2022-10-04 | 广州为乐信息科技有限公司 | Intelligent air switch isolation terminal control system |
-
2007
- 2007-09-20 CN CN2007100461455A patent/CN101123113B/en not_active Expired - Fee Related
Cited By (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9448737B2 (en) | 2012-01-09 | 2016-09-20 | Mediatek Inc. | Memory including controller for controlling access signals via memory buses and operating method thereof |
| CN106169303B (en) * | 2012-01-09 | 2019-04-05 | 联发科技股份有限公司 | Dynamic random access memory and its access method |
| CN103337251A (en) * | 2012-01-09 | 2013-10-02 | 联发科技股份有限公司 | Dynamic random access memory and access method thereof |
| US9214201B2 (en) | 2012-01-09 | 2015-12-15 | Mediatek Inc. | DRAM and access and operating method thereof |
| CN103337251B (en) * | 2012-01-09 | 2016-08-17 | 联发科技股份有限公司 | Dynamic random access memory and access method thereof |
| US9423974B2 (en) | 2012-01-09 | 2016-08-23 | Mediatek Inc. | Memory and access and operating method thereof |
| CN103731313B (en) * | 2012-10-10 | 2017-07-14 | 华为技术有限公司 | Counter and its implementation based on DDR SDRAM |
| US10049061B2 (en) | 2012-11-12 | 2018-08-14 | International Business Machines Corporation | Active memory device gather, scatter, and filter |
| CN103810125A (en) * | 2012-11-12 | 2014-05-21 | 国际商业机器公司 | Active memory device gather, scatter, and filter |
| CN104778013A (en) * | 2014-01-15 | 2015-07-15 | 三星电子株式会社 | Method and device for tracking activations to rows of memory |
| CN104778013B (en) * | 2014-01-15 | 2019-06-25 | 三星电子株式会社 | The method and apparatus for tracking the activation to the row of memory |
| CN108139994A (en) * | 2016-05-28 | 2018-06-08 | 华为技术有限公司 | Memory pool access method and Memory Controller Hub |
| CN108139994B (en) * | 2016-05-28 | 2020-03-20 | 华为技术有限公司 | Memory access method and memory controller |
| CN106201363A (en) * | 2016-07-26 | 2016-12-07 | 四川大学 | The memorizer of the random real time access of video flowing Pixel-level data and storage method |
| CN108139992A (en) * | 2016-08-09 | 2018-06-08 | 华为技术有限公司 | Access the method and storage device of storage device |
| CN108139992B (en) * | 2016-08-09 | 2020-06-16 | 华为技术有限公司 | Method for accessing storage device and storage device |
| CN111033623A (en) * | 2017-07-31 | 2020-04-17 | 美光科技公司 | Data state synchronization |
| CN111033623B (en) * | 2017-07-31 | 2021-04-23 | 美光科技公司 | Data state synchronization |
| CN108153485B (en) * | 2017-11-20 | 2021-06-22 | 天津津航技术物理研究所 | Method and system for multi-device cooperative access to SRAM |
| CN108153485A (en) * | 2017-11-20 | 2018-06-12 | 天津津航技术物理研究所 | A kind of more equipment collaborations access the method and system of SRAM |
| CN112783519A (en) * | 2019-11-04 | 2021-05-11 | 航天科工惯性技术有限公司 | Application program updating method and system for measuring pup joint |
| CN112783519B (en) * | 2019-11-04 | 2023-10-20 | 航天科工惯性技术有限公司 | Application program updating method and system for measuring nipple |
| CN112965816B (en) * | 2020-07-17 | 2023-06-02 | 华为技术有限公司 | Memory management technology and computer system |
| CN112965816A (en) * | 2020-07-17 | 2021-06-15 | 华为技术有限公司 | Memory management technology and computer system |
| CN112416823A (en) * | 2020-11-15 | 2021-02-26 | 珠海市一微半导体有限公司 | Sensor data read-write control method, system and chip in burst mode |
| CN112416823B (en) * | 2020-11-15 | 2024-05-03 | 珠海一微半导体股份有限公司 | Sensor data read-write control method, system and chip in burst mode |
| WO2022111013A1 (en) * | 2020-11-27 | 2022-06-02 | 安徽寒武纪信息科技有限公司 | Device supporting multiple access modes, method and readable storage medium |
| CN114563995A (en) * | 2022-01-17 | 2022-05-31 | 潍柴动力股份有限公司 | Reset detection method, device and equipment of electronic control unit and storage medium |
| CN114563995B (en) * | 2022-01-17 | 2024-03-19 | 潍柴动力股份有限公司 | Reset detection method, device, equipment and storage medium of electronic control unit |
| CN115081366B (en) * | 2022-06-13 | 2024-04-05 | 云合智网(上海)技术有限公司 | Modeling method for sudden access of register |
| CN115081366A (en) * | 2022-06-13 | 2022-09-20 | 杭州云合智网技术有限公司 | Modeling method for burst access of register |
| CN115148015A (en) * | 2022-06-30 | 2022-10-04 | 广州为乐信息科技有限公司 | Intelligent air switch isolation terminal control system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101123113B (en) | 2010-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101123113B (en) | Access method and control device for synchronous dynamic random access memory | |
| US8687456B2 (en) | Multi-port memory based on DRAM core | |
| TWI485714B (en) | System and method of page buffer operation for memory devices | |
| CN102193866B (en) | Memory storage and storage system | |
| CN100570739C (en) | Be used for method and system at the dynamic RAM hiding refreshes | |
| CN108694964B (en) | Data storage device | |
| CN1988034A (en) | Multi-path accessible semiconductor memory device having data transfer mode between ports | |
| TW200302965A (en) | Memory system | |
| TW200407769A (en) | Semiconductor memory apparatus, and method for writing data in the flush memory device | |
| US8880745B2 (en) | Efficient scheduling of transactions from multiple masters | |
| CN101233575A (en) | Memory control method and memory system | |
| US9026746B2 (en) | Signal control device and signal control method | |
| CN101556541B (en) | Method for manufacturing intelligent card, device, master card and system | |
| CN100392760C (en) | Semiconductor storage device | |
| US20080126691A1 (en) | Apparatus and method of partially accessing dynamic random access memory | |
| CN102257568B (en) | Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation | |
| CN101944075A (en) | Bus system and method and device for reading and writing low-speed bus device | |
| CN103019988B (en) | Computer, embedded controller and method thereof | |
| CN107507644A (en) | Storage arrangement and its operating method | |
| CN111462793B (en) | Data storage system and precharge policy setting method thereof | |
| US8886844B2 (en) | Efficient scheduling of read and write transactions in dynamic memory controllers | |
| CN100370436C (en) | Method for improving storage access efficiency and storage coutroller | |
| AU722780B2 (en) | Data base for persistent data | |
| CN206178765U (en) | SSD unit and SSD equipment | |
| US20180276126A1 (en) | Interface device and control method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100714 Termination date: 20170920 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |