CN108139994A - Memory pool access method and Memory Controller Hub - Google Patents

Memory pool access method and Memory Controller Hub Download PDF

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Publication number
CN108139994A
CN108139994A CN201680058616.1A CN201680058616A CN108139994A CN 108139994 A CN108139994 A CN 108139994A CN 201680058616 A CN201680058616 A CN 201680058616A CN 108139994 A CN108139994 A CN 108139994A
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access
address
memory
controller hub
memory controller
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CN108139994B (en
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肖世海
邹乔莎
杨伟
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

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Abstract

The embodiment of the invention discloses a kind of memory pool access method, including：Memory Controller Hub determines the first access set in access queue, includes continuous multiple access requests in the first access set；It is revised as the 2nd bank group addresses in the first bank group addresses that the Memory Controller Hub accesses the part access request in multiple access requests in set by described first；The first access request in the modified first access set and the second access request generate the first access instruction and the second access instruction to the Memory Controller Hub respectively；The Memory Controller Hub sends first access instruction and second access instruction to the memory respectively according to preset first time interval.Above-mentioned set memory access method can reduce internal storage access delay, improve the read or write speed of memory.

Description

Memory pool access method and Memory Controller Hub Technical field
The present invention relates to field of computer technology, more particularly to a kind of memory pool access method and Memory Controller Hub.
Background technique
With the development of computer technology, Double Data Rate synchronous DRAM (English: Double Data Rate, abbreviation: DDR) bus has had evolved to DDR4.Memory is divided into multiple regions by the bank group in DDR4 standard, each bank group can independently read and write data, so internal data throughout is significantly promoted, and can read a large amount of data simultaneously, the equivalent frequency of memory also obtains huge promotion under this configuration.
However inventor it has been investigated that, in the sequence for the memory access request that processor is initiated to Memory Controller Hub in traditional technology, bank group site homogeneous in usually all memory access requests is same, the address bank group that this allows for the internal storage access instruction of the generation of the Memory Controller Hub in traditional technology is also all the same, and since the Memory Controller Hub of standard setting is longer in the time interval for the access instruction for sending the same row address being directed toward in the register of memory to memory, this access for allowing for memory needs to expend longer time, it is lower so as to cause memory read-write speed.
Summary of the invention
This application provides a kind of memory pool access method and Memory Controller Hub, the access delay in memory access process can be shortened, improve internal storage access efficiency.
In a first aspect, this method is applied to computer system, and the computer system includes Memory Controller Hub and memory, and the memory includes control circuit and multiple registers this application provides a kind of memory pool access method.
In the above-mentioned methods, Memory Controller Hub first determines the first access set in access queue, it include continuous multiple access requests in the first access set, and, it include the first address bank group and the first row address in multiple access requests in the first access set, it should be noted that the first row address is used In a line register being directed toward in the memory.
For example, A, B and C respectively include different row but the request of bank group site homogeneous together, then Memory Controller Hub can determine that the first access collection is combined into the request sequence of BBBBB if the request in access queue is ABBBBBC.
The 2nd address bank group is revised as in first address bank group of the part access request in multiple access requests in the first determining access set by Memory Controller Hub；That is, if the address bank group of the access request in the first access set is BG0, it can then randomly select or BG1 is revised as in the address bank group according to preset tactful selected part access request, if Memory Controller Hub supports more bank group, then the address bank group of part access request can also be revised as BG2 or BG3 etc. by Memory Controller Hub.If herein, the 2nd address bank group is only used for the first address bank group to show difference, and is not limited to some address specific bank group.
Memory Controller Hub is respectively according to the first access request and the second access request the first access instruction of generation and the second access instruction in modified first access set, wherein, first access request and second access request are access request adjacent in the first access set, include the first address bank group in first access request and first access instruction, includes the 2nd address bank group in second access request and second access instruction.
The Memory Controller Hub sends first access instruction and second access instruction to the memory respectively according to preset first time interval, first time interval is less than the time interval for continuously transmitting two access instructions with the address identical bank group of standard setting, the control circuit that first access instruction is used to indicate the memory accesses first access request the first register to be visited, and the control circuit that second access instruction is used to indicate the memory accesses second access request the second register to be visited.
Optionally, the minimum value of first time interval can be tCCD_S, the delay that column address i.e. under the address different bank group is operated to column address, and the time interval that the Memory Controller Hub of standard setting continuously transmits two access instructions for same row address with the address identical bank group is tCCD_L.Due to tCCD_S (4 memory timing) < tCCD_L (6 memory timing), the value of first time interval can be less than the time interval for continuously transmitting two access instructions with the address identical bank group of standard setting.
In conjunction with the possible implementation of first aspect of the embodiment of the present invention, in the first possible implementation of first aspect of the embodiment of the present invention, Memory Controller Hub is carried out to the access request in the first access set When the modification of the address bank group, it can first determine the quantity N of the access request in the first access set not less than preset threshold；Then the 2nd address bank group is revised as in the first address bank group of the part access request in multiple access requests in the first access set, so that the first address bank group and the 2nd address bank group is used alternatingly in multiple access requests in modified first access set.
That is, in the continuous access instruction of generation, the address bank group of adjacent access instruction is all different two-by-two for N number of continuous access request in the first access set.For example, can the address bank group of the 2i access instruction be BG0, the address bank group of the 2i+1 access instruction is BG1, and i is natural number.
In conjunction with the possible implementation of the first of first aspect of the embodiment of the present invention and first aspect, in second of possible implementation of first aspect of the embodiment of the present invention, the preset threshold are as follows:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
Wherein, tRP is precharge effective period, Memory Controller Hub is after issuing precharge command, RAS row effective order could be sent by interval of time open new row, this time interval is tRP, tRTP is the delay before memory is issued to tRP from reading order, and tRCD is the time required for operation of the memory to row address after row address activation command issues；TCCD_S is the delay that the column address under the address different bank group is operated to column address, and tCCD_L is the delay operated with the column address under the address bank group to column address.
Second aspect, this application provides another memory pool access method, the method is applied to computer system, and the computer system includes Memory Controller Hub and memory, and the memory includes control circuit and multiple registers.
In above-mentioned memory pool access method, Memory Controller Hub first determines the first access set in access queue, it include continuous multiple access requests in the first access set, and, it include the first address bank group and the first row address in multiple access requests in the first access set, it should be noted that the first row address is used for the first row register being directed toward in the memory.
For example, A, B and C respectively include different row but the request of bank group site homogeneous together, then Memory Controller Hub can determine that the first access collection is combined into the request sequence of BBBBB if the request in access queue is ABBBBBC.
The second access request in access queue is also predefined in Memory Controller Hub, which is located at after the access request of the first access set in the access queue and accesses set with described first Access request is adjacent, includes the first address bank group and the second row address in second access request, and second row address is different from first row address, and second row address is used for the second row register being directed toward in the memory.
In example as above, access request C is different from the row address that access request B includes, but the address bank group is identical, and therefore, Memory Controller Hub can determine that access request C is the second access request.The row address that access request C includes is the second row address, the second row register for being directed toward in memory.
Memory Controller Hub determines that the quantity of the access request in the first access set is less than after preset threshold, then the 2nd address bank group is revised as in the first address bank group in second access request.
In example as above, when the quantity N of access request in the first access set is less than preset threshold, in namely first access set, when the quantity of request B comprising same row address is less than preset threshold, if the access request B and C initial address bank group is BG0, BG1 can be revised as in the address bank group of the second access request C.
Memory Controller Hub sends the first activation instruction and the second activation instruction to the memory respectively according to the second time interval, wherein, it should be noted that, first activation instruction is generated according to the first access request in the first access set, it include the first address bank group and first row address in first activation instruction, first activation instruction is used to indicate the row address of first access request the first register to be visited；Second activation instruction is generated according to second access request, it include the 2nd address bank group and second row address in second activation instruction, second activation instruction is used to indicate the row address of second access request the second register to be visited.
The minimum value of second time interval postpones tRRD between can be row address.That is, Memory Controller Hub is after having activated corresponding first row address of the first access request, withouting waiting for the first access request in the first access set, all access finishes, corresponding second activation instruction of the second access request of reactivation, but it can be during responding the first access instruction, the second row address asynchronously is activated in the 2nd bank group, to reduce the waiting time, improves internal storage access speed.
In conjunction with the possible implementation of second aspect of the embodiment of the present invention, in the first possible implementation of the third aspect of the embodiment of the present invention, which be can be set are as follows:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
Wherein, tRP is precharge effective period, and tRTP is that memory is issued to before tRP from reading order Delay, tRCD are the time required for operation of the memory to row address after row address activation command issues；TCCD_S is the delay that the column address under the address different bank group is operated to column address, and tCCD_L is the delay operated with the column address under the address bank group to column address.
In conjunction with the possible implementation of second aspect of the embodiment of the present invention, in second of possible implementation of the third aspect of the embodiment of the present invention, Memory Controller Hub determines the preferential row address for reaching idle state in first row address and the second row address；When the Memory Controller Hub determines that first row address preferentially reaches idle state, the Memory Controller Hub sends first activation instruction to the memory, after second time interval, the Memory Controller Hub sends second activation instruction to the memory.
In conjunction with the possible implementation of second aspect of the embodiment of the present invention, in the third possible implementation of the third aspect of the embodiment of the present invention, Memory Controller Hub determines the preferential row address for reaching idle state in first row address and the second row address；When the Memory Controller Hub determines that second row address preferentially reaches idle state, the Memory Controller Hub sends second activation instruction to the memory, after second time interval, the Memory Controller Hub sends first activation instruction to the memory.
That is, Memory Controller Hub is when sending the first activation instruction and the second activation instruction to the memory respectively according to the second time interval, it can determine preferentially to send the first activation instruction or the second activation instruction, the foundation of decision is whose preferential arrival idle state in the first row address and the second row address, if the first row address is arrived first up to idle state, Memory Controller Hub preferentially sends the first activation instruction；Second row address first reaches idle state, then Memory Controller Hub preferentially sends the second activation instruction.It can reduce in this way and row address is waited to become the time of idle state, to reduce internal storage access time-consuming, improve the access speed of memory.
Second aspect, the embodiment of the invention also provides a kind of Memory Controller Hub, for the Memory Controller Hub in computer system and Memory linkage, the memory includes control circuit and multiple registers.The Memory Controller Hub can be used for executing the memory pool access method that above-mentioned first aspect provides.
Fourth aspect, the embodiment of the invention also provides another Memory Controller Hub, for the Memory Controller Hub in computer systems with Memory linkage, the memory includes control circuit and multiple registers.The Memory Controller Hub can be used for executing the memory pool access method that above-mentioned second aspect provides.
In above-mentioned memory pool access method and Memory Controller Hub, same content of registers in register space corresponds at least one register address, only the address memory bank group bank group is different at least one described register address, and the register address of the access request uses the first address bank group.Memory Controller Hub is by dynamically selecting access request to set the address bank group as the 2nd address bank group, so that Memory Controller Hub The internal storage access instruction for carrying the address different bank group can be generated according to the memory access request for carrying the address same bank group originally, so that partial memory access instruction can access with internally depositing into line asynchronous, improve the concurrency of internal storage access, and the minimum interval tCCD_S that the internal storage access instruction that Memory Controller Hub sends the address different bank group is utilized is less than the characteristic for sending the minimum interval tCCD_L instructed with the internal storage access of the address bank group, to reduce memory read-write delay, the read-write efficiency of memory is improved.
5th aspect, this application provides a kind of computer program products, the computer readable storage medium including storing program code, and the instruction that said program code includes is for executing the dispatching method of the instruction of any one internal storage access described in above-mentioned first aspect.
6th aspect, this application provides a kind of computer program products, the computer readable storage medium including storing program code, and the instruction that said program code includes is for executing the dispatching method of the instruction of any one internal storage access described in above-mentioned second aspect.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, the drawings to be used in the description of the embodiments or prior art will be briefly described below, it should be evident that the attached drawing that drawings in the following description are only some embodiments of the invention.
Fig. 1 is a kind of hardware architecture diagram of memory working environment provided in an embodiment of the present invention；
Fig. 2 is a kind of flow chart of memory pool access method provided in an embodiment of the present invention；
Fig. 3 is the built-in function schematic diagram of Memory Controller Hub provided in an embodiment of the present invention；
Fig. 4 is the schematic diagram of more same content of registers of BG address of cache provided in an embodiment of the present invention；
The timing diagram of memory access process when Fig. 5 is the address group bank of unmodified access request provided in an embodiment of the present invention；
The timing diagram of internal storage access when Fig. 6 is the address group bank of the access request of the multiple same row addresses of access of interval modification provided in an embodiment of the present invention；
Fig. 7 is the flow chart of another memory pool access method provided in an embodiment of the present invention；
The timing diagram of internal storage access when Fig. 8 is adjacent modification provided in an embodiment of the present invention but the address group bank of access different row access request；
Fig. 9 is the schematic diagram of a variety of modification modes provided in an embodiment of the present invention in request queue when the selection access request modification address bank group.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.
In order to solve the waste of the caused access delay when generating access instruction access memory according to multiple memory access requests with same row address of the Memory Controller Hub in above-mentioned traditional technology, the lower technical problem of memory read-write speed, in one embodiment it is proposed that a kind of memory pool access method.This method is applied to computer system, which includes Memory Controller Hub and memory, and the memory includes control circuit and multiple registers, and this method can be executed by Memory Controller Hub.In computer system architecture in the conventional technology, Memory Controller Hub is usually located inside the north bridge chips of board chip set, or is integrated in north bridge chips built-in on CPU (central processing unit, Central Processing Unit) substrate.
Specifically, with reference to shown in Fig. 1, in a NVM (English: NonVolatile Memory, Chinese: nonvolatile storage)/FLASH (i.e. Flash EEPROM Memory, flash memory) DIMM (English: Dual In-line Memory Module, Chinese: dual inline memory module) it accesses in the embodiment of standard memory interface (DDR4), CPU is to carry out data exchange with memory, it then needs to be transmitted across by CPU → Memory Controller Hub (in north bridge chips) → rambus (such as DDR4 bus) → NVM/FLASH controller (register space of NVM/FALSH DIMM) → rambus → Memory Controller Hub → CPU data Journey.CPU can pass through the memory access request in transmitter register space to Memory Controller Hub, the register address of the content of registers in the register space of access in need is carried in the access request, a register address includes the address bank group, row address, column address, the address Bank, the address Rank etc..After Memory Controller Hub receives the memory access request, then NVM/FLASH controller can be sent to according to the internal storage access instruction on the register address of memory access request generation rambus and be written and read.
And the embodiment of the present invention is the waste of caused access delay when solving multiple memory access request access memories for carrying the address same bank group above-mentioned, the lower technical problem of memory read-write speed, using modifying CPU in Memory Controller Hub to the address bank group of the register address of the memory access request in register space, so that Memory Controller Hub can send the skill of asynchronous internal storage access instruction to memory Art means, so that the delay of internal storage access substantially reduces.
Specifically, as shown in Fig. 2, the memory pool access method includes:
Step S102: Memory Controller Hub determines the first access set in access queue, it include continuous multiple access requests in first access set, it include the first address bank group and the first row address in multiple access requests in first access set, the first row address is used for a line register being directed toward in memory.
As previously mentioned, processor CPU is by realizing to Memory Controller Hub transmission to the access request of the register space of memory to the read-write operation of memory.Then process that the access request that Memory Controller Hub receives CPU generates the access instruction on rambus can refer to shown in Fig. 3.
In Fig. 3, then the access request that Memory Controller Hub is sent by the interface with CPU to CPU is buffered in request queue, then further, the access request for dividing the storage of Bank to belong to each bank.Then store the current state for recording each Bank in Bank status register.Bank state includes several states such as READ/WRITE (read/write status), ACT (state of activation), PRECHARGE (pre-charge state), IDLE (idle state).It is also stored with the row address in ACT (activation) state in Bank status register, if there is row to be active in Bank, then records the currently active row address.Access address generator then generates access instruction according to the sequencing of the access request in Bank queue and the register address of carrying, is then sent to NVM/FLASH DIMM by rambus (such as DDR4).It is understood that received memory access request can also not distinguished Bank and cached by Memory Controller Hub in practical application, that is to say, that the Bank queue in Fig. 3 is not required.
In the present embodiment, first access set is the subqueue of the same row address of access in the request queue cached in Memory Controller Hub, such as, if the request sequence in the request queue of caching is ABBBBBC, wherein, A, B and C respectively indicates different row addresses, A, B and C the row register being respectively directed in memory, then BBBBB is then one first access set, row address B is the first row address that multiple access requests in the first access set include, and the address bank group of these memory access requests is identical.
In the present embodiment, the same content of registers in register space corresponds at least one register address, and only the address bank group is different at least one corresponding register address of the content of registers.In addition, the register address of received access request uses the first address bank group.
Refering to what is shown in Fig. 4, in the register space of NVM/FLASH DIMM, the same content of registers can be accessed by two register address in an application scenarios, that is, use the first address bank group The register address of (the hereinafter referred to as address BG) and the register address for using the 2nd address BG, the two addresses only need the address BG different, but the address Bank, the address Rank, row address and column address needs are identical (that is, the same content of registers is only related to the address Bank, the address Rank, row address and column address, it is unrelated with the address BG, in other embodiments or application scenarios, the register address of the corresponding same content of registers can be multiple, such as, greater than 2, the different addresses BG is used respectively).
And Memory Controller Hub is generating internal storage access instruction, by rambus (such as, DDR4 bus) access NVM/FLASH DIMM register space when, for accessing the register address of same content of registers, both the first address BG can be used, the 2nd address BG can also be used, it is only necessary to which the address Bank of the two register address, the address Rank, row address and column address are identical.
And in the present embodiment, for CPU when to the access request in Memory Controller Hub transmitter register space, the first address BG is used only in the register address carried in access request, as shown in Figure 4, the address BG0 can be used only, consistent with traditional technology.
That is, for CPU side, the embodiment of the present invention does not need the computer program of modification CPU access Memory Controller Hub, CPU still can conventionally in access Memory Controller Hub mode to Memory Controller Hub send access request, and for certain old-fashioned CPU programs, it may not support the address bank group, therefore, the register address carried in its access request to Memory Controller Hub sent may only include the address Bank, the address Rank, row address and column address, then Memory Controller Hub is when receiving the access request and being buffered in request queue, the default address BG can be arranged for it automatically is the first address BG.
Step S104: the 2nd address bank group is revised as in the first address bank group of the part access request in multiple access requests in the first access set by Memory Controller Hub.
Referring again to shown in Fig. 3, Memory Controller Hub before generating the access instruction on rambus according to access request, can selected part access request, modify the address BG of the access request of selection, the 2nd address BG be revised as by the first default address BG.After the completion of modification, then the access instruction on rambus can be generated according to the access request in request queue.
Step S106: Memory Controller Hub is respectively according to the first access request and the second access request the first access instruction of generation and the second access instruction in modified first access set, wherein, first access request and the second access request are access request adjacent in the first access set, include the first address bank group in first access request and the first access instruction, includes the 2nd address bank group in the second access request and the second access instruction.
Step S108: Memory Controller Hub is deposited respectively inwards according to preset first time interval and sends the first access instruction and the second access instruction, first time interval is less than the time interval for continuously transmitting two access instructions with the address identical bank group of standard setting, the control circuit that first access instruction is used to indicate memory accesses the first access request the first register to be visited, and the control circuit that the second access instruction is used to indicate memory accesses the second access request the second register to be visited.
With reference to shown in Fig. 4, the 2nd address BG can be revised as in the first default address BG of part access request in first access set and BG1 is revised as by BG0, the address BG of unmodified access request is BG0, and the address BG by the access request of selection modification is BG1.After modifying in this way, the different memory access request in the address bank group after continuous but modified for two in the first access set: the first access request and the second access request, the corresponding internal storage access instruction that Memory Controller Hub generates: the first access instruction and the corresponding address BG of the second access instruction are also respectively BG0 and BG1, Memory Controller Hub is when sending the first access instruction and the second access instruction to memory at this time, the first time interval that the time interval for continuously transmitting two access instructions with the address identical bank group less than standard setting can be used sends the first access instruction and the second access instruction.The minimum value of first time interval can be tCCD_S, the delay that column address i.e. under the address different bank group is operated to column address, and the minimum value of the time interval for continuously transmitting two access instructions with the address identical bank group of standard setting is tCCD_L, the delay operated with the column address under the address bank group to column address, and it is delayed since the delay of tCCD_L in memory is greater than tCCD_S, so that the memory read-write of the two continuous access requests, which is delayed, to be reduced, to improve the efficiency of memory read-write.
Such as, in an application scenarios, in one request queue it is continuous three read plus request (execute read and add 1 access request, both containing reading instruction and also contained write command) A, B, C respectively correspond row address R0, R0 and R1, R0 and R1 are the row address in the register address that three requests need to access, that is to say, that, the first two request is the identical request of row address, has abutted the subsequent request that do not go together.
If the mode in conventionally, by Memory Controller Hub access instruction is generated according to access request A, B, C respectively and NVM/FLASH DIMM is sent to by rambus according to the time interval of standard setting respectively, then the memory read-write timing in NVM/FLASH DIMM can refer to shown in Fig. 5.
In Fig. 5, the memory response delay summation of these three access requests is (unit is memory timing unit):
tRCD(16)+tCCD_L(6)+tRTP(6)+tRP(11)tRCD(16)+tCL (16)+4=75
Wherein, tCL (i.e. CAS Latency): CAS, that is, Column Address Strobe, column address signal, it defines the interval time for reading into I/O interface to data after reading order sending.
The meaning of RAS (Row Address Strobe, row address strobe) is similar with CAS, is exactly row (Row) address signal.It define be among a rank (one side of memory) for memory, row address activate (Active) order issue after, the time required for operation of the memory to row address.
TRCD (i.e. DRAM RAS to CAS Delay): interior to have to have an interval with row effective order in the presence of when sending column read write command, this interval is tRCD, the delay of RAS to CAS, briefly, known row address position, finds corresponding column address in this line, so that it may complete addressing, it is written and read, is exactly tRCD from known row address to the column address past time is found.
TRP (Precharge command Period): it is pre-charged effective period.After memory issues precharge command, it could be allowed to send RAS row effective order after a period of time and open new working line, this interval is referred to as tRP.
TRTP (i.e. DRAM Read to Precharge Time): the interval time before memory is issued to tRP from reading order on same rank is defined, but it completes reading and can just come into force after row address closing.
That is, R0 BG0 in the register of Memory Controller Hub enabled memory needs time-consuming tRCD, then the data on A request reading R0 BG0 could be responded, when the B for and then responding colleague requests to access the data of R0 BG0 again, need to wait the delay of tCCD_L can read, when the C for and then responding different row requests to read the data on R1 BG0, need to wait the line precharge time of tRP+tRTP.Then the time that data are write on R1 BG0 is waited again.
And according to the above method, for accessing continuous multiple access requests modifications address bank group with row address, then the time interval for two adjacent but the address bank group access instructions that Memory Controller Hub is sent to memory can then be shortened.
It is still that the address of three access requests A, B, C is respectively as follows: R0 BG0, R0 BG0, R1 BG0 in the queue for example, refering to what is shown in Fig. 6, in Fig. 6；The interval request A, B continuously gone together can be modified, i.e. the address of modification B request is R0 BG1 (being revised as the 2nd address BG, but to still maintain R0 constant for row address).Then in the corresponding access instruction of access request for sending A and B, first time interval tCCD_S shortens Memory Controller Hub and sends adjacent correspondence same row address Memory Controller Hub Access instruction time, and on the whole, the memory response delay summation of these three access requests is (unit is memory timing unit):
TRCD (16)+tRTP (6)+tRP (11) tRCD (16)+tCL (16)+4=69 saves-tCCD_S+tCCD_S delays of tCCD_L.
That is, after having responded the reading instruction of the R0 BG0 of A request, being directly pre-charged for BG0, and proceeds to respond to C request and read R1 BG0, and the R0 BG1 of B request can asynchronously access BG1, to save delay due to belonging to BG1.
And in another embodiment, Memory Controller Hub when the address group bank of access request, can also use following strategy in modifying request queue for the access request of access different row, please refer to shown in Fig. 7, comprising:
Step S202: Memory Controller Hub determines the first access set in access queue, it include continuous multiple access requests in first access set, it include the first address bank group and the first row address in multiple access requests in first access set, the first row address is used for the first row register being directed toward in the memory.
Step S204: Memory Controller Hub determines the second access request in access queue, second access request is located at after the access request of the first access set and adjacent with the access request of the first access set in access queue, it include the first address bank group and the second row address in second access request, second row address is different from the first row address, and the second row address is used for the second row register being directed toward in memory.The first row register and the second row register each mean any a line register in memory.
It is still that the address of three access requests A, B, C is respectively as follows: R0 BG0, R0 BG0, R1 BG0 in the queue in example as above.A and B is requested to access row address R0, request C accesses row address R1, but requesting the address A, B, C corresponding bank group is BG0.Then requesting A and B is the first access request in the first access set, and request C is the second access request after the access request of the first access set and adjacent with the access request of the first access set.R0 is the first row address, executes the first row register in memory, and R1 is the second row address, executes the second row register in memory.
Step S206: Memory Controller Hub determines that the quantity of the access request in the first access set is less than preset threshold.
Step S208: the 2nd address bank group is revised as in the first address bank group in the second access request by Memory Controller Hub.
In example as above, the address bank group for requesting C can be revised as BG1 by Memory Controller Hub, and keep the address bank group of request A and B constant.
Step S210: Memory Controller Hub is deposited respectively inwards according to the second time interval and sends the first activation instruction and the second activation instruction, wherein, first activation instruction is generated according to the first access request in the first access set, it include the first address bank group and first row address in first activation instruction, first activation instruction is used to indicate the row address of first access request the first register to be visited；Second activation instruction is generated according to second access request, it include the 2nd address bank group and second row address in second activation instruction, second activation instruction is used to indicate the row address of second access request the second register to be visited.
The minimum value of second time interval postpones tRRD (DRAM RAS to RAS Delay between can be row address, with the shortest delay of two between rank difference bank continuous activation instructions), that is, Memory Controller Hub to memory when sending for the first activation instruction of the first row address and for the second activation instruction of the second row address, all memories that request access to withouted waiting in the first access set finish the second activation instruction retransmited for the second row address, and the second activation instruction can be sent asynchronously with after waiting shorter the second time interval (such as interval of tRRD), so that can asynchronously be executed to the access of the second row address.
For example, in this embodiment, refering to what is shown in Fig. 8, in fig. 8, the address of three requests A, B, C are respectively as follows: R0 BG0, R0 BG0, R1 BG0 in the queue；The interval request AB and C of continuous different row can be modified, i.e. the address of modification C request is R1BG1 (being revised as the 2nd address BG, but to still maintain R1 constant for row address).Then Memory Controller Hub waits the time of tRRD i.e. transmittable second activation instruction after sending the first activation instruction to memory, shortens the waiting time, and the internal storage access delay summation of these three requests is (unit is memory timing unit):
TRCD (16)+tCL (16)+6+4+4=46
Save-tCCD_S delays of tRTP+tRP+tRCD.
That is, Memory Controller Hub according to the A of BG0 request and B when requesting to initiate the first activation instruction to memory, can corresponding second activation instruction asynchronously be requested to the C that memory initiates BG1, i.e. after activating R0 BG0, although needing to wait the delay of tRRD, R1 BG1 could be activated, but when delay generation, BG0 is still in the delay waiting process of tRCD.And BG0 is when waiting the delay of tCCD_L and tCCD_S, BG1 is also at wait tCL delay during, therefore, delay has been shared on BG0 and BG1 and has obtained asynchronously handling, so that the delay for executing internal storage access instruction greatly reduces.
Further, in one embodiment, there is also for a fairly large number of situation of access request continuously gone together, for example, existing N+1 request in request queue, according to received sequencing, the address of top n request is corresponding with a line R0 BG0, the corresponding R1 BG0 that do not go together of rear 1 request.Memory Controller Hub can select preferably mode in the method for the above two modification address bank group according to the length N of the first access set.
Such as, when Memory Controller Hub determines the quantity N of the access request in the first access set not less than preset threshold, the 2nd address bank group is revised as in first address bank group of the part access request in multiple access requests in the first access set by Memory Controller Hub, so that the first address bank group and the 2nd address bank group is used alternatingly in multiple access requests in modified first access set.
And when Memory Controller Hub determines the quantity N of the access request in the first access set less than preset threshold, then execute above-mentioned steps S208: the 2nd address bank group is revised as in the first address bank group in the second access request by Memory Controller Hub.
Optionally, the preset threshold are as follows:
(tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
Wherein, tRP is precharge effective period, and tRTP is the delay before memory is issued to tRP from reading order, and tRCD is the time required for operation of the memory to row address after row address activation command issues；TCCD_S is the delay that the column address under the address different bank group is operated to column address, and tCCD_L is the delay operated with the column address under the address bank group to column address.
As previously mentioned, rear 1 the second access request corresponds to the case where not going together R1 BG0, then the first subqueue obtained is N number of request for R0 BG0 refering to what is shown in Fig. 9, the address of N number of first access request in the first access set is corresponding with a line R0 BG0.
The mode that the 2nd address bank group is revised as in first address bank group of the part access request in multiple access requests in the first access set is modified according to Memory Controller Hub above-mentioned, then amounts to and saves delay are as follows:
Time saving 1=(tCCD_L-tCCD_S) × N+tCCD_S
And modify in such a way that the 2nd address bank group is revised as in the first address bank group in the second access request by Memory Controller Hub above-mentioned, then save delay are as follows:
Time saving 2=tRTP+tRP+tRCD-tCCD_S delays.
Therefore when time saving 1 > time saving 2, selection is above-mentioned to carry out interval modification for the request continuously gone together Mode set the address BG, when time saving 1 < time saving 2, the mode above-mentioned for be spaced modification for different request in the ranks is selected to set the address BG.
Therefore, queue length threshold is (tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S).
In other embodiments, the same content of registers in register space can be used in the application scenarios greater than 2 addresses BG, such as, the address BG0, BG1 and BG2 can be respectively corresponded, then and so on, for above-mentioned request A, B, C, initial R0 BG0, R0 BG0, R1 BG0 can be revised as R0 BG0, R0 BG1, R1 BG2, then be split in the upper asynchronous execution of BG0, BG1, BG2.Further improve execution efficiency.
Further, if Memory Controller Hub determines that the quantity N of the access request in the first access set is less than preset threshold, i.e. for Memory Controller Hub using when the modification mode of the 2nd address bank group is revised as in the first address bank group in the second access request, Memory Controller Hub may further determine that the sequencing for sending the first activation instruction and the second activation instruction.
That is, Memory Controller Hub determines the preferential row address for reaching idle state in the first row address and the second row address.
When the Memory Controller Hub determines that the first row address preferentially reaches idle state, Memory Controller Hub sends first activation instruction to memory, and after the second time interval, Memory Controller Hub sends the second activation instruction to memory；
When Memory Controller Hub determines that the second row address preferentially reaches idle state, Memory Controller Hub sends the second activation instruction to memory, and after second time interval, Memory Controller Hub sends the first activation instruction to the memory.
Refering to what is shown in Fig. 3, Bank status register is additionally provided in Memory Controller Hub, wherein the state for the register row address being stored in memory.In Bank state according to apart from idle state by as far as close sequence be READ/WRITE (read/write status), ACT (state of activation), PRECHARGE (pre-charge state), IDLE (idle state).It is preferential to send the first activation instruction if the first row address faster reaches idle state, the first access instruction is quickly responded by memory；And when the second address faster reaches idle state, then the second activation instruction of preferential transmission, enables the second access instruction to be quickly responded by memory.If still preferentially sending the first activation instruction when the second address faster reaches idle state, then timely Memory Controller Hub activates the row address in register, it is also desirable to the row address be waited to reach idle state ability It is accessed, therefore it needs to wait the additional time, and the second activation instruction is first sent at this time, then while waiting the second time interval, the first row address has been waited to arrive at idle state, to incorporate the time of waiting, also just reduce the time of access memory, to improve the access speed of memory.
To sum up, implement the embodiment of the present invention, will have the following beneficial effects:
In above-mentioned set memory access method and Memory Controller Hub, same content of registers in register space corresponds at least one register address, only the address memory bank group bank group is different at least one described register address, and the register address of the access request uses the first address bank group.Memory Controller Hub is by dynamically selecting access request to set the address bank group as the 2nd address bank group, Memory Controller Hub is enabled to generate the internal storage access instruction for carrying the address different bank group according to the memory access request for carrying the address same bank group originally, so that partial memory access instruction can access with internally depositing into line asynchronous, improve the concurrency of internal storage access, and the minimum interval tCCD_S that the internal storage access instruction that Memory Controller Hub sends the address different bank group is utilized is less than the characteristic for sending the minimum interval tCCD_L instructed with the internal storage access of the address bank group, to reduce memory read-write delay, improve the read-write efficiency of memory.
Simultaneously, the method and device of the address setting bank group in the embodiment of the present invention does not modify to the computer program of CPU request Memory Controller Hub, for CPU side, the mode that Memory Controller Hub sets the address bank group is transparent, for developer, it does not need to modify to the computer program of CPU side and adaptation can be completed, to improve scalability yet.
The above disclosure is only the preferred embodiments of the present invention, and of course, the scope of rights of the present invention cannot be limited by this, therefore equivalent changes made in accordance with the claims of the present invention, is still within the scope of the present invention.

Claims (14)

  1. A kind of memory pool access method, which is characterized in that the method is applied to computer system, and the computer system includes Memory Controller Hub and memory, and the memory includes control circuit and multiple registers, which comprises
    The Memory Controller Hub determines the first access set in access queue, it include continuous multiple access requests in the first access set, it include the first address bank group and the first row address in multiple access requests in the first access set, first row address is used for a line register being directed toward in the memory；
    The 2nd address bank group is revised as in first address bank group of the part access request in multiple access requests in the first access set by the Memory Controller Hub；
    The Memory Controller Hub is respectively according to the first access request and the second access request the first access instruction of generation and the second access instruction in modified first access set, wherein, first access request and second access request are access request adjacent in the first access set, include the first address bank group in first access request and first access instruction, includes the 2nd address bank group in second access request and second access instruction；
    The Memory Controller Hub sends first access instruction and second access instruction to the memory respectively according to preset first time interval, the first time interval is less than the time interval for continuously transmitting two access instructions with the address identical bank group of standard setting, the control circuit that first access instruction is used to indicate the memory accesses first access request the first register to be visited, and the control circuit that second access instruction is used to indicate the memory accesses second access request the second register to be visited.
  2. The method according to claim 1, wherein the first address bank group of the part access request in multiple access requests in the first access set is revised as the 2nd address bank group and includes: by the Memory Controller Hub
    The Memory Controller Hub determines the quantity of the access request in the first access set not less than preset threshold；
    The 2nd address bank group is revised as in first address bank group of the part access request in multiple access requests in the first access set by the Memory Controller Hub, so that the first address bank group and the 2nd address bank group is used alternatingly in multiple access requests in modified first access set.
  3. According to the method described in claim 2, it is characterized in that, the preset threshold are as follows:
    (tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
    Wherein, tRP is precharge effective period, and tRTP is the delay before memory is issued to tRP from reading order, and tRCD is the time required for operation of the memory to row address after row address activation command issues；TCCD_S is the delay that the column address under the address different bank group is operated to column address, and tCCD_L is the delay operated with the column address under the address bank group to column address.
  4. A kind of memory pool access method, which is characterized in that the method is applied to computer system, and the computer system includes Memory Controller Hub and memory, and the memory includes control circuit and multiple registers, which comprises
    The Memory Controller Hub determines the first access set in access queue, it include continuous multiple access requests in the first access set, it include the first address bank group and the first row address in multiple access requests in the first access set, first row address is used for the first row register being directed toward in the memory；
    The Memory Controller Hub determines the second access request in access queue, second access request is located at after the access request of the first access set and adjacent with the access request of the first access set in the access queue, it include the first address bank group and the second row address in second access request, second row address is different from first row address, and second row address is used for the second row register being directed toward in the memory；
    The Memory Controller Hub determines that the quantity of the access request in the first access set is less than preset threshold；
    The 2nd address bank group is revised as in the first address bank group in second access request by the Memory Controller Hub；
    The Memory Controller Hub sends the first activation instruction and the second activation instruction to the memory respectively according to the second time interval, wherein, first activation instruction is generated according to the first access request in the first access set, it include the first address bank group and first row address in first activation instruction, first activation instruction is used to indicate the row address of first access request the first register to be visited；Second activation instruction is generated according to second access request, it include the 2nd address bank group and second row address in second activation instruction, second activation instruction is used to indicate the row address of second access request the second register to be visited.
  5. According to the method described in claim 4, it is characterized in that, the preset threshold are as follows:
    (tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
    Wherein, tRP is precharge effective period, and tRTP is the delay before memory is issued to tRP from reading order, and tRCD is the time required for operation of the memory to row address after row address activation command issues；TCCD_S is the delay that the column address under the address different bank group is operated to column address, and tCCD_L is the delay operated with the column address under the address bank group to column address.
  6. According to the method described in claim 4, it is characterized in that, the Memory Controller Hub sends the first activation instruction to the memory respectively according to the second time interval and the second activation instruction includes:
    The Memory Controller Hub determines the preferential row address for reaching idle state in first row address and the second row address；
    When the Memory Controller Hub determines that first row address preferentially reaches idle state, the Memory Controller Hub sends first activation instruction to the memory, after second time interval, the Memory Controller Hub sends second activation instruction to the memory.
  7. According to the method described in claim 4, it is characterized in that, the Memory Controller Hub sends the first activation instruction to the memory respectively according to the second time interval and the second activation instruction includes:
    The Memory Controller Hub determines the preferential row address for reaching idle state in first row address and the second row address；
    When the Memory Controller Hub determines that second row address preferentially reaches idle state, the Memory Controller Hub sends second activation instruction to the memory, after second time interval, the Memory Controller Hub sends first activation instruction to the memory.
  8. A kind of Memory Controller Hub, the Memory Controller Hub is in computer systems with Memory linkage, and the memory includes control circuit and multiple registers, which is characterized in that the Memory Controller Hub is used for:
    Determine the first access set in access queue, it include continuous multiple access requests in the first access set, it include the first address bank group and the first row address in multiple access requests in the first access set, first row address is used for a line register being directed toward in the memory；
    The 2nd address bank group is revised as in first address bank group of the part access request in multiple access requests in the first access set；
    Respectively according to the first access request and the second access request the first access instruction of generation and the second access instruction in modified first access set, wherein, first access request and second access request are access request adjacent in the first access set, and first access request and first access refer to Include the first address bank group in order, includes the 2nd address bank group in second access request and second access instruction；
    First access instruction and second access instruction are sent to the memory respectively according to preset first time interval, the first time interval is less than the time interval for continuously transmitting two access instructions with the address identical bank group of standard setting, the control circuit that first access instruction is used to indicate the memory accesses first access request the first register to be visited, and the control circuit that second access instruction is used to indicate the memory accesses second access request the second register to be visited.
  9. Memory Controller Hub according to claim 8, which is characterized in that the Memory Controller Hub is used for:
    Determine the quantity of the access request in the first access set not less than preset threshold；
    The 2nd address bank group is revised as in first address bank group of the part access request in multiple access requests in the first access set, so that the first address bank group and the 2nd address bank group is used alternatingly in multiple access requests in modified first access set.
  10. Memory Controller Hub according to claim 9, which is characterized in that the preset threshold are as follows:
    (tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
    Wherein, tRP is precharge effective period, and tRTP is the delay before memory is issued to tRP from reading order, and tRCD is the time required for operation of the memory to row address after row address activation command issues；TCCD_S is the delay that the column address under the address different bank group is operated to column address, and tCCD_L is the delay operated with the column address under the address bank group to column address.
  11. A kind of Memory Controller Hub, the Memory Controller Hub is in computer systems with Memory linkage, and the memory includes control circuit and multiple registers, which is characterized in that the Memory Controller Hub is used for:
    Determine the first access set in access queue, it include continuous multiple access requests in the first access set, it include the first address bank group and the first row address in multiple access requests in the first access set, first row address is used for the first row register being directed toward in the memory；
    Determine the second access request in access queue, second access request is located at after the access request of the first access set and adjacent with the access request of the first access set in the access queue, it include the first address bank group and the second row address in second access request, second row address is different from first row address, and second row address is used for the second row register being directed toward in the memory；
    Determine that the quantity of the access request in the first access set is less than preset threshold；
    The 2nd address bank group is revised as in the first address bank group in second access request；
    The first activation instruction and the second activation instruction are sent to the memory respectively according to the second time interval, wherein, first activation instruction is generated according to the first access request in the first access set, it include the first address bank group and first row address in first activation instruction, first activation instruction is used to indicate the row address of first access request the first register to be visited；Second activation instruction is generated according to second access request, it include the 2nd address bank group and second row address in second activation instruction, second activation instruction is used to indicate the row address of second access request the second register to be visited.
  12. Memory Controller Hub according to claim 11, which is characterized in that the preset threshold are as follows:
    (tRTP+tRP+tRCD-tCCD_S-tCCD_S)/(tCCD_L-tCCD_S)；
    Wherein, tRP is precharge effective period, and tRTP is the delay before memory is issued to tRP from reading order, and tRCD is the time required for operation of the memory to row address after row address activation command issues；TCCD_S is the delay that the column address under the address different bank group is operated to column address, and tCCD_L is the delay operated with the column address under the address bank group to column address.
  13. Memory Controller Hub according to claim 11, which is characterized in that the Memory Controller Hub is used for:
    The preferential row address for reaching idle state is determined in first row address and the second row address；
    When the Memory Controller Hub determines that first row address preferentially reaches idle state, Xiang Suoshu memory sends first activation instruction, and after second time interval, the Memory Controller Hub sends second activation instruction to the memory.
  14. Memory Controller Hub according to claim 11, which is characterized in that the Memory Controller Hub is used for:
    The preferential row address for reaching idle state is determined in first row address and the second row address；
    When the Memory Controller Hub determines that second row address preferentially reaches idle state, Xiang Suoshu memory sends second activation instruction, and after second time interval, the Memory Controller Hub sends first activation instruction to the memory.
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