CA1270574A - Method for operating a memory apparatus serving as a clock interface and an apparatus for carrying out the method - Google Patents
Method for operating a memory apparatus serving as a clock interface and an apparatus for carrying out the methodInfo
- Publication number
- CA1270574A CA1270574A CA000505353A CA505353A CA1270574A CA 1270574 A CA1270574 A CA 1270574A CA 000505353 A CA000505353 A CA 000505353A CA 505353 A CA505353 A CA 505353A CA 1270574 A CA1270574 A CA 1270574A
- Authority
- CA
- Canada
- Prior art keywords
- partial
- memory
- data
- memories
- clock frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Vehicle Body Suspensions (AREA)
Abstract
Abstract of the Disclosure:
Method for operating a memory apparatus, including first, second and third memories, which serves as a clock frequency interface in transfer of at least one data packet includes buffer storing data for writing and reading the first and second partial memories; writing the data alternatingly with a first working clock frequency into the first and second partial memory; and reading-out alternatingly any one of the partial memories in response to an indication from a respective one of the partial memories that it is completely written or in response to an indication that and end-of-packet signal has been received by a respective one of the partial memories, under control of a second working clock frequency operatively engaging at least one of the partial memories and an apparatus for carryout the method.
Method for operating a memory apparatus, including first, second and third memories, which serves as a clock frequency interface in transfer of at least one data packet includes buffer storing data for writing and reading the first and second partial memories; writing the data alternatingly with a first working clock frequency into the first and second partial memory; and reading-out alternatingly any one of the partial memories in response to an indication from a respective one of the partial memories that it is completely written or in response to an indication that and end-of-packet signal has been received by a respective one of the partial memories, under control of a second working clock frequency operatively engaging at least one of the partial memories and an apparatus for carryout the method.
Description
~2 7 METHOD FOR OPERATING A MEMORY APPARATUS SERVING AS
A CLO_K INTERFACE AND AN APPARATUS FOR CARRYING O~T 'l'HE METHOD
Specification:
The invention relates to a method for operating a memory apparatus serving as a clock interface in the transmission of data packets, wherein the data for writing-in or reading-out are buffered in two independent memory sections, and an apparatus for carrying out the method.
In data processing systems with distributed intelligence or in systems with peripheral units and a central unit, a clock interface must be inserted into the data transmission paths if the individual units are operated with different operating clocks.
One known synchronization method is based on the use of a single port RAM which is operated as a so-called tandem-fifo memory (fifo = first in - first out). The memory is divided here into two regions, which are written alternatingly from both sides with a first clock frequency and are read out with a faster second clock frequency. For the time in which the one region is read out, it must, of course, be ensured that all data present on the input side are read into the other memory region and are not lost.
~ ~ ~0 ~7~
For this purpose it is sufficient in transmission methods with fixed packet lengths, if the two memory regions can accept the fixed, given quantity of data. In transmission methods with variable packet lengths, the problem can arise, however, that the capacity of the receiving memory region is not sufficient for picking up the entire packet. In such a case, one switches, after the first region is written full, to the second region which takes over the rest of the data packet while the first region is already being read out.
This, however, has the disadvantage that the entire clock interface is blocked for further writing-in until the first region is released again. This blocking has a detrimental effect if the writing of the second region is completed before the first region is read out completely. In the worst case, the second region is occupied only by a single data word, so that the data transmission is interrupted for the entire read-out time.
It is accordingly an object of the invention to provide a method for operating a memory apparatus serving as a clock interface and an apparatus for carrying out the method, which overcomes the hereinafore mentioned disadvantages of the heretofore known methods and devices of this general type through which the transmission of data packets of variable block lengths is possible without the danger of blocking.
~7(~574
A CLO_K INTERFACE AND AN APPARATUS FOR CARRYING O~T 'l'HE METHOD
Specification:
The invention relates to a method for operating a memory apparatus serving as a clock interface in the transmission of data packets, wherein the data for writing-in or reading-out are buffered in two independent memory sections, and an apparatus for carrying out the method.
In data processing systems with distributed intelligence or in systems with peripheral units and a central unit, a clock interface must be inserted into the data transmission paths if the individual units are operated with different operating clocks.
One known synchronization method is based on the use of a single port RAM which is operated as a so-called tandem-fifo memory (fifo = first in - first out). The memory is divided here into two regions, which are written alternatingly from both sides with a first clock frequency and are read out with a faster second clock frequency. For the time in which the one region is read out, it must, of course, be ensured that all data present on the input side are read into the other memory region and are not lost.
~ ~ ~0 ~7~
For this purpose it is sufficient in transmission methods with fixed packet lengths, if the two memory regions can accept the fixed, given quantity of data. In transmission methods with variable packet lengths, the problem can arise, however, that the capacity of the receiving memory region is not sufficient for picking up the entire packet. In such a case, one switches, after the first region is written full, to the second region which takes over the rest of the data packet while the first region is already being read out.
This, however, has the disadvantage that the entire clock interface is blocked for further writing-in until the first region is released again. This blocking has a detrimental effect if the writing of the second region is completed before the first region is read out completely. In the worst case, the second region is occupied only by a single data word, so that the data transmission is interrupted for the entire read-out time.
It is accordingly an object of the invention to provide a method for operating a memory apparatus serving as a clock interface and an apparatus for carrying out the method, which overcomes the hereinafore mentioned disadvantages of the heretofore known methods and devices of this general type through which the transmission of data packets of variable block lengths is possible without the danger of blocking.
~7(~574
2~365 255~
With the foregoiny and other objects in view, there i5 provided, in accordance with the invention, ~ method for operatlng a memory apparatus, including first, second and third partial memories, which serves as a clock frequency interface in transfer of at least one data packet comprising: buffering data destined for writing and reading in said partial memories; writing the data with a first working clock frequency into said partial memories, and reading-out at least one of said partial memories with a second clock frequency in response to at least an indication from said at least one of said partial memories that it is completely written full and that an end-of-packet signal has been received by a respective one of said partial memories, under control of said second working clock frequency operatively engaging at least one of said partial memories.
In accordance with another mode of the invention there is provided a method which includes reloading into the third partial memor~ data stored in either one of the first and second partial memorles in response to an indication from a respective one of the first and second partial memories that it is completely written or in response to an indication that an end-of-packet signal has been received by a respective one of the first and second partial memories, the third partlal memory operating as a buffer memory.
~ 5~
In accordance with an additional mode of the invention there is provided a method which includes only the third partial memory with the second working clock frequency and reloading the third memory under control of the first working clock frequency.
In accordance with an added mode of the invention there is provided a method including the steps of:
a) writing a data word into the first partial memory with the working clock frequency, b) transferring of the data word into the second partial memory with the working clock frequency, c) transferring of the data word from the second partial memory into the third partial memory with the working clock frequency, d) repeating thè process steps a) to c) until the third partial memory is either completely written or the end of the packet is reached, e) reading the third partial memory with the second working clock frequency, and upon receipt of further data words:
f~ repeating the steps a) and e) until the second partial 3L~7057fl~
memory is completely written or the end oE the packet has been reached, and g) completing transfer of the data in the second partial memory into the third partial memory, repeating step e), and upon receipt of further data words:
h) writing data into the first partial memory until the latter is completely written or the end of the packet has been reached, i~ completing transfer of the memory contents of the first partial memory into at least the third partial memory j) repeating step e~.
In accordance with the objects of the invention, there is also provided an apparatus for operating a memory which serves as a clock frequency interface, comprising: a write/read memory which includes first, second and third partial memories which are functionall.y separated from one another, a control unit for alternatingly driving the partial memories, where data is transferred from one of the partial memories to another in response to at least one of the indications: "partial memory full", "end of packet", or "partial memory empty" from a respective one of the partial memories, and wherein the -" lZ-~057d~
transfer of data is controlled by a second clock, at least during reading out of a partial memory, and wherein the trans-fer of data is controlled by a first working clock during writing the partial memories, and wherein the second working clock has a higher frequency than the first working clock.
In accordance with again another feature of the invention, the third partial memory operates as an output buffer memory, from the output side of the third partial memory being read out to an output data bus under control of the second working clock, and wherein at least one of the first and second partial memories is connected at the input side to an input dsta bus.
In accordance with again a further feature of the invention, the three partial memories are wired as fifo-memories.
In accordance with a concomitant feature of the invention, the memory capacity of the third partial memory on the output side is twice as large as the respective memory capacity of the first and second partial memories.
The invention is based on the principle to organize the entire buffer memory of the clock interface by multiple subdivision in such a way that a respective buffer is provided for writing-in and reading out as well as an independent further buffer which can take up overrunning sections of a data packet until at ~ 70 ~7~
least one of the other regions is again ready to receive data.
This intermediate storage and reloading or reading out by sections makes it possible to buffer also longer data packets without interruption in a memory, the capacity of which can be laid out independently of the data packet length. The data packets are passed on in data blocks of constant length which is determined by the capacity of the reading-out memory, and the remaining rest, i.e., the packet structure is preserved.
The invention is directly applicable to data processing systems which are based on direct working memory access, a configura-tion with input/output modules or a single-chip central unit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for operating a memory apparatus serving as a clock interface and apparatus for carrying out the method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood ~rom the following description of specific embodiments when read in connection with the accompanying drawings, in which:
Fig. 1 is a schematic circuit diagram of a data processing system with distributed intelligence and several operating clocks;
Fig. 2 is a circuit diagram of a clock interface according to the invention; and Fig. 3 is a graph of the data flow on the input and output side of the apparatus according to Fig. 2.
Referring now to the figures of the drawings in detail and first, particularly, to Fig. 1 thereof, there is seen a data processing system for data coded in binary code which includes several peripheral units 1 operating in parallel and a central unit 2 for controlling and coordinating the data transmission via a common parallel data bus 3 as well as the access to a common operating memory 4. The peripheral units 1 are acted upon by an operating clock frequency CLKl, while the common devices such as the central unit 2 and the memory 4 work with a faster clock frequency CLK2. For synchronizing the two working clock frequencies, the peripheral units 1 are each followed by clock interfaces 5 which are shown in detail in Fig. 2. On ~0 57~
their parallel data buses 6 on the input side, the data trans-mission proceeds with the first operating clock frequency CLKl, while the data are read out on the output side in parallel via data buses 7 to the common bus 3 with the second operating clock frequency CLK2.
As is shown in Fig. 2, each clock interface 5 consists of a write/read memory with three memory parts 8, 9, 10 and a control unit 11. The three submemories can be operated func-tionally independently of each other. In the advantageous embodiment example shown here, the entire memory apparatus is constructed as a fifo-memory, which is assembled from the three partial memories 8, 9, 10 which are likewise constructed as fifo-memories. The data transfer and data output from the buses and from one submemory to the other take place in parallel data word-wise. .
Since the capacity of the third partial memory 10 on the output side determines the maximum block length, into which a data packet running through the clock interface is subdivided in the case of exeess length, it also determines the frequency of aeeess to the eommon data bus 3. Advantageously, the third partial memory 3 is twiee as large as the respeetive two remaining submemories 8 ancl 9 ~ ~70S7fl~
Each of the three submemories 8, 9, 10, indicates to the control unit 11 its state "full" or "empty" via signals F8, F9, F10, and E8, E9, E10, respectively.
The control unit 11 is designed, for instance, as a PLA (PLA =
programmable logic erray), which controls the course of the memory accesses by means of arriving control signals. It receives from the corresponding peripheral unit 1, via a control line 24, a control signal WR, which indicates if a data word present on the data bus ~ should be written into the first partial memory 8. The end of the packet is furthermore indicat-ed via a control line 25 by a control signal PE. The control unit 11 signals to the central unit 2 via control lines 21, 22, by control signals IP, IB interruption requests if either the third submemory 10 is written full or when it has received the end of the packet. Vice versa, the control unit 11 receives from the central unit 2 via a control line 23 that the third submemory 10 is read out, i.e. the receipt of a data block or the entire data packet.
The first submemory 8 receives from the control unit 11 a write signal WR8 and a read signal RW9 which is, at the same time, interpreted by the second submemory 9 as the write signal.
Similarly, a read signal RW10 is interpreted by the second submemory 9 as a read signal and by the third submemory 10 as a write signal. The command RD10 for reading the third memory ~L2~57~
region 10 is given by the central unit 2 via the control line 26. This signal represents for the submemory 10 the second worklng cl~ck frequency CLK2 during the state "read" in as much as the command RD10 is repeated with the frequency of the working clock frequency CLK2, until the partial memory is read out.
Fig. 3 shows on the top line an example for the pulse diagram of a data flow such as can be taken off at the data bus 6. It is composed of three data packets A, B, C each of which com-prise any desired number of data words. The individual data packets are separated from each other by control symbols. On the line at the bottom, a pulse diagram of the same data flow is plotted versus time such as can be taken off on the data bus 7 after passing through the clock interface 5. It shows, under the assumption made as an example, that the capacity of the third submemory 10 is not sufficient for receiving the data packets B, C, how the data packets B, C are transmitted in data blocks Bl, B2 and the rest B3 or in one data block C1 and the remainder C2. Finally, the effective edges of the corresponding interruption signals IP, IB are given.
In the following, the method and the operation of the apparatus will be described, referring to the figures. By the drive from the control unit 11, the three partial memories are written alternatingly with the first working clock frequency CLKl and ~7~57~
completely written partial memories which may also be acted upon by the end of the packet are read out alternatingly; the third partial memory 10 is acted upon by the second working clock frequency CLK2. Assuming a suitably long data packet, the entire memory apparatus is filled from the bottom up, that means the partial memory 9 after the partial memory 10 and as the last, the partial memory 8. As soon as the partial memory 10 on the output side is written completely, or if the data packet ends during the writing, it is functionally separated from the partial memory 9. While the partial memory 10 can be read out with the faster working clock frequency CLK2, the partial memory 9 can be written full with the working clock frequency CLKl, until it is likewise full or the data packet has come to an end. Subsequently, the partial memories 8 and 9 are separated as to their functions. If further data words arrive, the partial memory 8 is written in the corresponding manner. As soon as the data are read out of the partial memory 10 and therefore this memory is released again, the separation from the partial memory 9 is cancelled and its contents are transferred to the partial memory 10, while, at the same time, the partial memory 8 can be written. As soon as the data transfer from the partial memory 9 to the partial memory 10 is completed, the partial memory 8 is transferred into the partial memory 9, while the partial memory 10 is separated. This method is not limited to the use of a fifo-memory.
1~
7~)57~
In detail, the apparatus of Fig. 2 works as follows. The presence of a data word on the data bus 6 is indicated to the control unit ll by a signal on the control line 24. After it is checked by interrogation of the control signal E8, that the partial memory 8 is empty, the writing of the data word into the partial memory 8 is caused by the write signal WR8.
Before the next data word is written-in, the control unit ll checks via the control signal E9 the state of the partial memory 9 and transfers the data word from the partial memory 8 if the partial memory 9 is empty. The data word is transferred from the partial memory 9 into the partial memory lO in a similar manner.
For the example showrl in Fig. 3 of a data packet A of which the number of data words does not exceed the capacity of the third partial memory lO, this process is repeated until the end of the packet is indicated via the control signal PE. As soon as the data packet A is completely contained in the third partial memory lO, the central unit 2 is requested by the interrupt command JP to transfer the contents of the partial memory lO
into the working memory 4. This process is brought about by the read signal RDlO with the second working clock frequency CLK2.
The transfer of the entire data packet is acknowledged via the control line 23.
In the example of the data packet C, the partial memory is written full completely, which is signalled to the control unit 11 via the control signal F10. The latter then sends the interrupt request JB to the central unit 2 which is interpreted as a notice that only a first block Cl of the data packet is ready. While the third partial memory 10 is being read out, the rest C2 of the data packet C is interim-buffered in the partial memory 9 in the manner described above, interim-storing each data word in the first partial memory 8. As soon as the third partial memory lO is empty, the contents of the partial memory 9 are transferred. At the same time, the writing of a further data packet into the first partial memory 8 can be started.
In the example of the data packet B, the partial memory 9 is written with the first half and the partial memory 8 with the second half of the data block B2 after the first block Bl is written into the partial memory 10. While writing into the partial memory 8 continues, the data are shifted from the partial memory 9 into the partial memory 10. Subsequently, the content of the partial memory 8 is transferred into the partial memory 9, and simultaneously, the rest B3 of the data packet is written into the partial memory 8.
The foregoing is a description corresponding in substance to German Application P 35 11 626.9, dated March 29, 1985, the International priority of which is being claimed for the 1i~7~S74 instant application, and which is hereby made part of this application. Any material discrepancies between the foregoi.ng specification and the aforementioned corresponding German application are to be resolved in favor Or the latter.
With the foregoiny and other objects in view, there i5 provided, in accordance with the invention, ~ method for operatlng a memory apparatus, including first, second and third partial memories, which serves as a clock frequency interface in transfer of at least one data packet comprising: buffering data destined for writing and reading in said partial memories; writing the data with a first working clock frequency into said partial memories, and reading-out at least one of said partial memories with a second clock frequency in response to at least an indication from said at least one of said partial memories that it is completely written full and that an end-of-packet signal has been received by a respective one of said partial memories, under control of said second working clock frequency operatively engaging at least one of said partial memories.
In accordance with another mode of the invention there is provided a method which includes reloading into the third partial memor~ data stored in either one of the first and second partial memorles in response to an indication from a respective one of the first and second partial memories that it is completely written or in response to an indication that an end-of-packet signal has been received by a respective one of the first and second partial memories, the third partlal memory operating as a buffer memory.
~ 5~
In accordance with an additional mode of the invention there is provided a method which includes only the third partial memory with the second working clock frequency and reloading the third memory under control of the first working clock frequency.
In accordance with an added mode of the invention there is provided a method including the steps of:
a) writing a data word into the first partial memory with the working clock frequency, b) transferring of the data word into the second partial memory with the working clock frequency, c) transferring of the data word from the second partial memory into the third partial memory with the working clock frequency, d) repeating thè process steps a) to c) until the third partial memory is either completely written or the end of the packet is reached, e) reading the third partial memory with the second working clock frequency, and upon receipt of further data words:
f~ repeating the steps a) and e) until the second partial 3L~7057fl~
memory is completely written or the end oE the packet has been reached, and g) completing transfer of the data in the second partial memory into the third partial memory, repeating step e), and upon receipt of further data words:
h) writing data into the first partial memory until the latter is completely written or the end of the packet has been reached, i~ completing transfer of the memory contents of the first partial memory into at least the third partial memory j) repeating step e~.
In accordance with the objects of the invention, there is also provided an apparatus for operating a memory which serves as a clock frequency interface, comprising: a write/read memory which includes first, second and third partial memories which are functionall.y separated from one another, a control unit for alternatingly driving the partial memories, where data is transferred from one of the partial memories to another in response to at least one of the indications: "partial memory full", "end of packet", or "partial memory empty" from a respective one of the partial memories, and wherein the -" lZ-~057d~
transfer of data is controlled by a second clock, at least during reading out of a partial memory, and wherein the trans-fer of data is controlled by a first working clock during writing the partial memories, and wherein the second working clock has a higher frequency than the first working clock.
In accordance with again another feature of the invention, the third partial memory operates as an output buffer memory, from the output side of the third partial memory being read out to an output data bus under control of the second working clock, and wherein at least one of the first and second partial memories is connected at the input side to an input dsta bus.
In accordance with again a further feature of the invention, the three partial memories are wired as fifo-memories.
In accordance with a concomitant feature of the invention, the memory capacity of the third partial memory on the output side is twice as large as the respective memory capacity of the first and second partial memories.
The invention is based on the principle to organize the entire buffer memory of the clock interface by multiple subdivision in such a way that a respective buffer is provided for writing-in and reading out as well as an independent further buffer which can take up overrunning sections of a data packet until at ~ 70 ~7~
least one of the other regions is again ready to receive data.
This intermediate storage and reloading or reading out by sections makes it possible to buffer also longer data packets without interruption in a memory, the capacity of which can be laid out independently of the data packet length. The data packets are passed on in data blocks of constant length which is determined by the capacity of the reading-out memory, and the remaining rest, i.e., the packet structure is preserved.
The invention is directly applicable to data processing systems which are based on direct working memory access, a configura-tion with input/output modules or a single-chip central unit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for operating a memory apparatus serving as a clock interface and apparatus for carrying out the method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood ~rom the following description of specific embodiments when read in connection with the accompanying drawings, in which:
Fig. 1 is a schematic circuit diagram of a data processing system with distributed intelligence and several operating clocks;
Fig. 2 is a circuit diagram of a clock interface according to the invention; and Fig. 3 is a graph of the data flow on the input and output side of the apparatus according to Fig. 2.
Referring now to the figures of the drawings in detail and first, particularly, to Fig. 1 thereof, there is seen a data processing system for data coded in binary code which includes several peripheral units 1 operating in parallel and a central unit 2 for controlling and coordinating the data transmission via a common parallel data bus 3 as well as the access to a common operating memory 4. The peripheral units 1 are acted upon by an operating clock frequency CLKl, while the common devices such as the central unit 2 and the memory 4 work with a faster clock frequency CLK2. For synchronizing the two working clock frequencies, the peripheral units 1 are each followed by clock interfaces 5 which are shown in detail in Fig. 2. On ~0 57~
their parallel data buses 6 on the input side, the data trans-mission proceeds with the first operating clock frequency CLKl, while the data are read out on the output side in parallel via data buses 7 to the common bus 3 with the second operating clock frequency CLK2.
As is shown in Fig. 2, each clock interface 5 consists of a write/read memory with three memory parts 8, 9, 10 and a control unit 11. The three submemories can be operated func-tionally independently of each other. In the advantageous embodiment example shown here, the entire memory apparatus is constructed as a fifo-memory, which is assembled from the three partial memories 8, 9, 10 which are likewise constructed as fifo-memories. The data transfer and data output from the buses and from one submemory to the other take place in parallel data word-wise. .
Since the capacity of the third partial memory 10 on the output side determines the maximum block length, into which a data packet running through the clock interface is subdivided in the case of exeess length, it also determines the frequency of aeeess to the eommon data bus 3. Advantageously, the third partial memory 3 is twiee as large as the respeetive two remaining submemories 8 ancl 9 ~ ~70S7fl~
Each of the three submemories 8, 9, 10, indicates to the control unit 11 its state "full" or "empty" via signals F8, F9, F10, and E8, E9, E10, respectively.
The control unit 11 is designed, for instance, as a PLA (PLA =
programmable logic erray), which controls the course of the memory accesses by means of arriving control signals. It receives from the corresponding peripheral unit 1, via a control line 24, a control signal WR, which indicates if a data word present on the data bus ~ should be written into the first partial memory 8. The end of the packet is furthermore indicat-ed via a control line 25 by a control signal PE. The control unit 11 signals to the central unit 2 via control lines 21, 22, by control signals IP, IB interruption requests if either the third submemory 10 is written full or when it has received the end of the packet. Vice versa, the control unit 11 receives from the central unit 2 via a control line 23 that the third submemory 10 is read out, i.e. the receipt of a data block or the entire data packet.
The first submemory 8 receives from the control unit 11 a write signal WR8 and a read signal RW9 which is, at the same time, interpreted by the second submemory 9 as the write signal.
Similarly, a read signal RW10 is interpreted by the second submemory 9 as a read signal and by the third submemory 10 as a write signal. The command RD10 for reading the third memory ~L2~57~
region 10 is given by the central unit 2 via the control line 26. This signal represents for the submemory 10 the second worklng cl~ck frequency CLK2 during the state "read" in as much as the command RD10 is repeated with the frequency of the working clock frequency CLK2, until the partial memory is read out.
Fig. 3 shows on the top line an example for the pulse diagram of a data flow such as can be taken off at the data bus 6. It is composed of three data packets A, B, C each of which com-prise any desired number of data words. The individual data packets are separated from each other by control symbols. On the line at the bottom, a pulse diagram of the same data flow is plotted versus time such as can be taken off on the data bus 7 after passing through the clock interface 5. It shows, under the assumption made as an example, that the capacity of the third submemory 10 is not sufficient for receiving the data packets B, C, how the data packets B, C are transmitted in data blocks Bl, B2 and the rest B3 or in one data block C1 and the remainder C2. Finally, the effective edges of the corresponding interruption signals IP, IB are given.
In the following, the method and the operation of the apparatus will be described, referring to the figures. By the drive from the control unit 11, the three partial memories are written alternatingly with the first working clock frequency CLKl and ~7~57~
completely written partial memories which may also be acted upon by the end of the packet are read out alternatingly; the third partial memory 10 is acted upon by the second working clock frequency CLK2. Assuming a suitably long data packet, the entire memory apparatus is filled from the bottom up, that means the partial memory 9 after the partial memory 10 and as the last, the partial memory 8. As soon as the partial memory 10 on the output side is written completely, or if the data packet ends during the writing, it is functionally separated from the partial memory 9. While the partial memory 10 can be read out with the faster working clock frequency CLK2, the partial memory 9 can be written full with the working clock frequency CLKl, until it is likewise full or the data packet has come to an end. Subsequently, the partial memories 8 and 9 are separated as to their functions. If further data words arrive, the partial memory 8 is written in the corresponding manner. As soon as the data are read out of the partial memory 10 and therefore this memory is released again, the separation from the partial memory 9 is cancelled and its contents are transferred to the partial memory 10, while, at the same time, the partial memory 8 can be written. As soon as the data transfer from the partial memory 9 to the partial memory 10 is completed, the partial memory 8 is transferred into the partial memory 9, while the partial memory 10 is separated. This method is not limited to the use of a fifo-memory.
1~
7~)57~
In detail, the apparatus of Fig. 2 works as follows. The presence of a data word on the data bus 6 is indicated to the control unit ll by a signal on the control line 24. After it is checked by interrogation of the control signal E8, that the partial memory 8 is empty, the writing of the data word into the partial memory 8 is caused by the write signal WR8.
Before the next data word is written-in, the control unit ll checks via the control signal E9 the state of the partial memory 9 and transfers the data word from the partial memory 8 if the partial memory 9 is empty. The data word is transferred from the partial memory 9 into the partial memory lO in a similar manner.
For the example showrl in Fig. 3 of a data packet A of which the number of data words does not exceed the capacity of the third partial memory lO, this process is repeated until the end of the packet is indicated via the control signal PE. As soon as the data packet A is completely contained in the third partial memory lO, the central unit 2 is requested by the interrupt command JP to transfer the contents of the partial memory lO
into the working memory 4. This process is brought about by the read signal RDlO with the second working clock frequency CLK2.
The transfer of the entire data packet is acknowledged via the control line 23.
In the example of the data packet C, the partial memory is written full completely, which is signalled to the control unit 11 via the control signal F10. The latter then sends the interrupt request JB to the central unit 2 which is interpreted as a notice that only a first block Cl of the data packet is ready. While the third partial memory 10 is being read out, the rest C2 of the data packet C is interim-buffered in the partial memory 9 in the manner described above, interim-storing each data word in the first partial memory 8. As soon as the third partial memory lO is empty, the contents of the partial memory 9 are transferred. At the same time, the writing of a further data packet into the first partial memory 8 can be started.
In the example of the data packet B, the partial memory 9 is written with the first half and the partial memory 8 with the second half of the data block B2 after the first block Bl is written into the partial memory 10. While writing into the partial memory 8 continues, the data are shifted from the partial memory 9 into the partial memory 10. Subsequently, the content of the partial memory 8 is transferred into the partial memory 9, and simultaneously, the rest B3 of the data packet is written into the partial memory 8.
The foregoing is a description corresponding in substance to German Application P 35 11 626.9, dated March 29, 1985, the International priority of which is being claimed for the 1i~7~S74 instant application, and which is hereby made part of this application. Any material discrepancies between the foregoi.ng specification and the aforementioned corresponding German application are to be resolved in favor Or the latter.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Method for operating a memory apparatus, including first, second and third partial memories, which serves as a clock frequency interface in transfer of at least one data packet comprising: buffering data destined for writing and reading in said partial memories; writing the data with a first working clock frequency into said partial memories, and reading-out at least one of said partial memories with a second clock frequency in response to at least an indication from said at least one of said partial memories that it is completely written full and that an and-of-packet signal has been received by a respective one of said partial memories, under control of said second working clock frequency operatively engaging at least one of said partial memories.
2. Method according to claim 1, which comprises: reloading into the third partial memory data stored in either one of said first and second partial memories in response to an indication from a respective one of said first and second partial memories that it is completely written or in response to an indication that an end-of-packet signal has been received by a respective one of said first and second partial memories, said third partial memory operating as a buffer memory.
3. Method according to claim 2, which comprises: only the third partial memory with the second working clock frequency and reloading the third memory under control of the first working clock frequency.
4. Method according to claim 2, comprising the steps of:
a) writing a data word into the first partial memory with the working clock frequency, b) transferring of the data word into the second partial memory with the working clock frequency, c) transferring of the data word from the second partial memory into the third partial memory with the first working clock frequency, d) repeating the process steps a) to c) until the third partial memory is either completely written or the end of the packet is reached, e) reading the third partial memory with the second working clock frequency, and upon receipt of further data words:
f) repeating the steps a) and e) until the second partial memory is completely written or the end of the packet has been reached, and g) completing transfer of the data in the second partial memory into the third partial memory, repeating step e), and upon receipt of further data words:
h) writing data into the first partial memory until the latter is completely written or the end of the packet has been reached, i) completing transfer of the memory contents of the first partial memory into at least the third partial memory j) repeating step e).
a) writing a data word into the first partial memory with the working clock frequency, b) transferring of the data word into the second partial memory with the working clock frequency, c) transferring of the data word from the second partial memory into the third partial memory with the first working clock frequency, d) repeating the process steps a) to c) until the third partial memory is either completely written or the end of the packet is reached, e) reading the third partial memory with the second working clock frequency, and upon receipt of further data words:
f) repeating the steps a) and e) until the second partial memory is completely written or the end of the packet has been reached, and g) completing transfer of the data in the second partial memory into the third partial memory, repeating step e), and upon receipt of further data words:
h) writing data into the first partial memory until the latter is completely written or the end of the packet has been reached, i) completing transfer of the memory contents of the first partial memory into at least the third partial memory j) repeating step e).
5. Apparatus for operating a memory which serves as a clock frequency interface, comprising: a write/read memory which includes first, second and third partial memories which are functionally separated from one another, a control unit for alternatingly driving said partial memories, where data is transferred from one of said partial memories to another in response to at least one of the indications: "partial memory full", "end of packet", or "partial memory empty" from a respective one of said partial memories, and wherein said transfer of data is controlled by a second clock, at least during reading out of a partial memory, and wherein said transfer of data is controlled by a first working clock during writing the partial memories, and wherein said second working clock has a higher frequency than the first working clock.
6. Apparatus according to claim 5 wherein said third partial memory operates as an output buffer memory, the data from the output side of said third partial memory being read out to an output data bus under control of said second working clock, and wherein at least one of said first and second partial memories is connected at the input side to an input data bus.
7. Apparatus according to claim 6, wherein the three partial memories are wired as fifo-memories.
8. Apparatus according to claim 5 wherein the memory capacity of the third partial memory on the output side is twice as large as the respective memory capacity of the first and second partial memories.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3511626.9 | 1985-03-29 | ||
| DE3511626 | 1985-03-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1270574A true CA1270574A (en) | 1990-06-19 |
Family
ID=6266831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000505353A Expired - Fee Related CA1270574A (en) | 1985-03-29 | 1986-03-27 | Method for operating a memory apparatus serving as a clock interface and an apparatus for carrying out the method |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0196532A1 (en) |
| JP (1) | JPS61226861A (en) |
| CA (1) | CA1270574A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2249199A (en) * | 1990-10-25 | 1992-04-29 | Lo Kun Nan | Peripheral-computer interface apparatus |
| EP0483441B1 (en) * | 1990-11-02 | 1998-01-14 | STMicroelectronics S.r.l. | System arrangement for storing data on a FIFO basis |
| GB2386306B (en) * | 1998-02-13 | 2003-12-24 | Intel Corp | Method and apparatus for minimizing asynchronous transmit fifo under-run and receive fifo over-run conditions |
| US5991304A (en) * | 1998-02-13 | 1999-11-23 | Intel Corporation | Method and apparatus for minimizing asynchronous transmit FIFO under-run and receive FIFO over-run conditions |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4044335A (en) * | 1974-09-23 | 1977-08-23 | Rockwell International Corporation | Memory cell output driver |
| US4056851A (en) * | 1976-09-20 | 1977-11-01 | Rca Corporation | Elastic buffer for serial data |
| JPS5939051B2 (en) * | 1980-02-12 | 1984-09-20 | 日本電気株式会社 | data buffer circuit |
| JPS5952464B2 (en) * | 1980-07-31 | 1984-12-19 | 富士通株式会社 | Data buffer control method |
| JPS5759243A (en) * | 1980-09-26 | 1982-04-09 | Toshiba Corp | Buffer circuit |
-
1986
- 1986-03-17 EP EP86103566A patent/EP0196532A1/en not_active Ceased
- 1986-03-27 CA CA000505353A patent/CA1270574A/en not_active Expired - Fee Related
- 1986-03-27 JP JP6972486A patent/JPS61226861A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61226861A (en) | 1986-10-08 |
| EP0196532A1 (en) | 1986-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4138732A (en) | Data transfer control system | |
| US5020020A (en) | Computer interconnect system with transmit-abort function | |
| US5187780A (en) | Dual-path computer interconnect system with zone manager for packet memory | |
| US3761879A (en) | Bus transport system for selection information and data | |
| US5590304A (en) | Circuits, systems and methods for preventing queue overflow in data processing systems | |
| US4884192A (en) | Information processor capable of data transfer among plural digital data processing units by using an active transmission line having locally controlled storage of data | |
| JPS607306B2 (en) | Sequential storage interface device | |
| JPS581465B2 (en) | Data signal buffering method | |
| US5574885A (en) | Modular buffer memory with separately controllable logical output queues for use in packet switched networks | |
| JPS5847050B2 (en) | I/O interrupt system | |
| EP0433520A1 (en) | Elastic configurable buffer for buffering asynchronous data | |
| US4271480A (en) | Apparatus enabling the transfer of data blocks of variable lengths between two memory interfaces of different widths | |
| CA1270574A (en) | Method for operating a memory apparatus serving as a clock interface and an apparatus for carrying out the method | |
| US5008880A (en) | Data transmission apparatus | |
| US6341313B1 (en) | Flow controlling method and apparatus for network between processors | |
| JPH04297942A (en) | Output queue which can perform double interruptions and method thereof | |
| US3387280A (en) | Automatic packing and unpacking of esi transfers | |
| JP2773198B2 (en) | Data transfer device | |
| JPS58103043A (en) | Stack forming method | |
| JPS5922979B2 (en) | Buffer memory control method | |
| KR950014088B1 (en) | Fifo circuit used with general memory | |
| JPS60186151A (en) | Data communicating method between processors | |
| JP2671768B2 (en) | DMA data transfer method | |
| JPH06284453A (en) | Atm cell switch | |
| JPH0713910A (en) | Adaptor for transfer of data block of variable size to other adapetors via system bus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKLA | Lapsed |