GB2386306B - Method and apparatus for minimizing asynchronous transmit fifo under-run and receive fifo over-run conditions - Google Patents

Method and apparatus for minimizing asynchronous transmit fifo under-run and receive fifo over-run conditions

Info

Publication number
GB2386306B
GB2386306B GB0312960A GB0312960A GB2386306B GB 2386306 B GB2386306 B GB 2386306B GB 0312960 A GB0312960 A GB 0312960A GB 0312960 A GB0312960 A GB 0312960A GB 2386306 B GB2386306 B GB 2386306B
Authority
GB
United Kingdom
Prior art keywords
run
minimizing
fifo
over
under
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0312960A
Other versions
GB2386306A (en
GB0312960D0 (en
Inventor
Darren L Abramson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/023,394 external-priority patent/US5991304A/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB0312960D0 publication Critical patent/GB0312960D0/en
Publication of GB2386306A publication Critical patent/GB2386306A/en
Application granted granted Critical
Publication of GB2386306B publication Critical patent/GB2386306B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
GB0312960A 1998-02-13 1999-02-01 Method and apparatus for minimizing asynchronous transmit fifo under-run and receive fifo over-run conditions Expired - Fee Related GB2386306B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/023,394 US5991304A (en) 1998-02-13 1998-02-13 Method and apparatus for minimizing asynchronous transmit FIFO under-run and receive FIFO over-run conditions
GB0019761A GB2351209B (en) 1998-02-13 1999-02-01 Method and apparatus for minimizing asynchronous transmit fifo under-run and receive fifo over-run conditions

Publications (3)

Publication Number Publication Date
GB0312960D0 GB0312960D0 (en) 2003-07-09
GB2386306A GB2386306A (en) 2003-09-10
GB2386306B true GB2386306B (en) 2003-12-24

Family

ID=27736184

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0312960A Expired - Fee Related GB2386306B (en) 1998-02-13 1999-02-01 Method and apparatus for minimizing asynchronous transmit fifo under-run and receive fifo over-run conditions

Country Status (1)

Country Link
GB (1) GB2386306B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0196532A1 (en) * 1985-03-29 1986-10-08 Siemens Aktiengesellschaft Method for operating a memory used as a clock interface and arrangement for the realization of the method
US4907225A (en) * 1987-04-03 1990-03-06 Advanced Micro Devices, Inc. Data protocol controller
US5602537A (en) * 1994-05-13 1997-02-11 Zilog, Inc. Technique for eliminating data transmit memory underruns
US5860119A (en) * 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0196532A1 (en) * 1985-03-29 1986-10-08 Siemens Aktiengesellschaft Method for operating a memory used as a clock interface and arrangement for the realization of the method
US4907225A (en) * 1987-04-03 1990-03-06 Advanced Micro Devices, Inc. Data protocol controller
US5602537A (en) * 1994-05-13 1997-02-11 Zilog, Inc. Technique for eliminating data transmit memory underruns
US5860119A (en) * 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags

Also Published As

Publication number Publication date
GB2386306A (en) 2003-09-10
GB0312960D0 (en) 2003-07-09

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