JPS5952464B2 - Data buffer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention uses a data buffer consisting of multiple stages of buffers to sequentially shift a predetermined number of data blocks as one group. This invention relates to a data buffer control method that imposes operational timing restrictions on data transfer between buffers.

To explain the conventional data buffer, an input/output device and a channel are connected via a line, and when data is transmitted from the input/output device, the data is divided into two blocks, for example, two
It is assumed that bytes are transferred one byte at a time as one group. Four data buffers are provided on the channel side, each buffer capable of storing one byte of data.

As shown in FIG. 1A, regarding the data buffers, from the read terminal side closer to the channel, the first stage buffer is referred to as the A buffer, and the second stage buffer is referred to as the B buffer, hereinafter referred to as the C buffer and the D buffer. Initially, each buffer is blank because it has not received the transferred data, and when it is first received, it goes into the D buffer, passes through the C buffer and B buffer, goes to the A buffer, and then immediately goes to the B buffer. also contains data (because data is transferred in 2-byte units). When the state shown in FIG. 1B is reached (assuming there is data in the hatched buffer), an interrupt is raised to the channel, and the data in the A buffer is first read and passed through. That is, by shifting the byte data constituting 1 group G1 into the A and B buffers, a continuous output request is raised to the channel. This continuous request causes the channel to
When the data in the buffer is transferred, the data in the B buffer is transferred to the A buffer, and when the channel transfers the data in the A buffer again, a set of data is passed to the channel. When the next data is transferred, it goes through D buffer, C buffer, and then B-A.
It will be stored in the buffer and a second interrupt request will be issued to the channel. In this specification, "READ" refers to the operation of channeling data in a buffer, "FUL" indicates a state in which data exists in the buffer, and "FUL" indicates an empty state.
AST.EMP'' and a shift signal instructing the transfer of the A buffer agitator from the B buffer to AST. BST. D buffer to C buffer is written as CST. In addition, signals indicating that there is data in buffers A, B, C, and D are sent to FLA and F, respectively.
They are written as LB, FLC, and FLD. Conventionally, AST, CST
The signals of FI. It turns on only under the signal conditions of B.] and FLD-Rer.

Similarly, BST was configured to be turned on only under the condition of FLC-FLB. In other words, the shift BST of the data block from the C buffer to the B buffer was performed on the condition that there was data in the C buffer, FLC, and the B buffer was empty. However, this configuration causes the following problems. In other words, one set of 2 bytes (
When the first byte of the data in the gnome G1) is read by the channel node, the state shown in FIG. 1C occurs. The B buffer data is then shifted to the A buffer.
At this time, if the next set of data (data of group G2 in the figure) is stored in the C and D buffers, the result will be as shown in FIG. 1D. At this time, if the above-described condition of the shift BST signal is used, the data in the C buffer will enter the B buffer. This results in the state shown in FIG. 1E. Then, since both the A buffer and the B buffer are FUL, the next interrupt signal will be issued to the channel. Because READ is performed twice with one interrupt, the channel reads the first byte due to the previous interrupt, and receives another interrupt before reading the second byte, which not only disrupts the sequence, but also causes errors in the A buffer and B buffer. Read two different sets of data: the 2nd byte of the 1st process that exists and the 1st byte of the 2nd process, and finish.
Destroys a sequence consisting of 1 block and 2 bytes.

A-
There is a possibility that all the data is present in the D buffer, and problems related to ST signal manipulation as just described arise. SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide a data buffer control system that imposes a timing restriction on data transfer between buffers in data blocks in each group.

Embodiments of the present invention will be described below with reference to the drawings. Second
The figure shows a circuit for controlling data block shift between buffers, and generates signals AST, BST, and CST. FL
A,fLB. fLC and fLD are JK flip-flops, respectively, and when set, FLA and FLD respectively.
It is assumed that LB, FLC, and FLD signals are generated. CRT
is also set when the second byte of the first processor exists in the A or B buffer of the flip-flop. Data is received, the RVD signal sets flip-flop FLD, and the data enters the D buffer. At the same time, CST becomes ゜゜1゛, so the data is transferred to the C buffer and the flip-flop FLC is set. Next, under the conditions described later, BST becomes ゜゜1゛ and the data becomes B
Move to buffer and set FLB. AST becomes 1 and the data is transferred to the A buffer and FLA is set.
When CST, BST, and AST become "1", the condition is that they are H-top and A-top, respectively. And FL
D, fLC, fLB flip-flops have data C,
It is reset at the timing of transition to the B and A buffers, and FLA is reset when the channel is in READ mode. Free, Soft, Soft 0CTR (Set only when the first byte of data moves from the C buffer to the B buffer, and an interrupt request REQ is possible under the conditions that CTR is set and FL and C are set. At that timing, CR
Q itself is reset. A set of 2 bytes of data sends an interrupt request R to the channel located in the A and B buffers.
EQ is issued and becomes "READ" from the channel.

Here, the conditions of BST will be explained. The conditions under which data can be transferred from buffer C to buffer B are that the data is in the second byte of CTR, H, FLC, or that reading has finished and both buffers A and B are empty. This is limited to FLC. In the case of the above-mentioned case C in Fig. 1, the condition becomes D in Fig. 1 under the conditions of FLB, and the flip-flop state is FLA, top, FLC, FL.
D, CTk. If the 1st byte of the next data set enters the B buffer before the 2nd byte data of the A buffer shown in Fig. 1D is read, and becomes the data shown in Fig. 1E, then the circuit shown in Fig. 2 is used. Unless this is done, the conditions for the interrupt request REQ will be met. In the present invention, the circuit shown in FIG. 2 prevents the transfer of the first byte of data from the C buffer to the B buffer described above immediately, that is, the state shown in FIG. 1E does not occur. Then, data is transferred to the B buffer only when the above-mentioned BST conditions are met. The table below summarizes the conditions under which each flip-flop is set and reset. Table 3 shows the setup/reset conditions of the flip-flop and the time chart of each state of each circuit/buffer.

Diagonal lines in the buffer indicate that data exists, and blank areas indicate that there is no data. That is, initially, all A-D buffers are in five empty states. Next, data is received from the input/output device, RVD is turned on, data is entered into the D buffer, FLD is set, and FLD is turned on. When the C buffer is empty and the FLDnhr conditions are met and CST is turned on, data is transferred to the C buffer, FLC is set, and FLC is turned on. (First half of time T1 in FIG. 3) Here, there are two conditions for data to be transferred from the C buffer to the B buffer.

One of these is that both the A and B buffers are empty, which necessarily means that the 1st byte of the 1st block and the previous data do not remain. Number 2 indicates that there is data in the A buffer and that CTR is on, which is the second byte of the plotter. This prevents the first byte of the next process from being set in the B buffer while the second byte of the first process still remains in the A buffer. The data for C Batsuhua is 1
When the second condition, FLCn, is satisfied and BST is turned on, the process moves to the B buffer, and at this time, FLB is turned on, and CRT is also turned on.

(Second half of time T1 in Figure 3) Furthermore, AS under the AnFLB condition
T turns on and data moves to A buffer. Furthermore, FLD
, fLC, and fLB are set by CST, BST, and AST, respectively. Next, when the second byte of the block is received at the beginning of time T2 in FIG. 3, RVD is turned on again, and the data is transferred to the C buffer in the same way as the first byte.
Here, the second condition of FLcnn top NcTR is satisfied and set in the B buffer, and at the same time, CTR is reset. In the latter half of time T2, A, B
There is data for one program in the buffer, and an interrupt REQ is raised for the channel. However, suppose that the channel side does not read the data for some reason until it receives the next plotter at the beginning of time T3. When the first byte of the next block is received, the data moves to the C buffer, but since the previous data exists in the B buffer and FLB is on, it remains in the C buffer. At the beginning of time T4 in FIG. 3, a second byte is received and set in the D buffer, and the A, B, C, and D buffers all become FUL. When the channel finally reads data from the A buffer, the FLA is reset and becomes F[X, and the data in the B buffer is transferred to the A buffer.

Here, it becomes FLB, but the data of C buffer does not satisfy the above-mentioned condition and remains there. This is indicated by point α in Figure 3. When the second byte is read from the A buffer, the conditions for the Ainn top NFLC are established, and the first byte of the next block is transferred from the C buffer to the B buffer.

(See the time after point α in FIG. 3) The subsequent operation is the same as described above, and each buffer is passed through each block without breaking the sequence. In this manner, according to the present invention, among the buffer sections consisting of multiple stages of buffers, from the reading side to a predetermined number of buffers, that is, the number of buffers corresponding to the number of data blocks constituting one set (group).
It regulates the conditions under which the next set of data plotters is shifted.

In other words, if a predetermined number of buffers (in the above example, two buffers A and B) are both FUL, and there is data in the subsequent buffer (the same buffer C), the data in the subsequent buffer will be stored in the predetermined number of buffers. This sets a condition so that the shift will not occur unless all of the data in the data are empty. This makes it possible to reliably distinguish the data plotters constituting one set from the data plotters of other consecutive sets and transmit them to the reading side.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the state of data transfer between buffers, FIG. 2 is an example of a circuit configuration when implementing the present invention, and FIG. 3 is a time chart of each state.

Claims (1)

[Claims] 1. It has a buffer section consisting of multiple stages of buffer areas that sequentially shift and store a plurality of data blocks, and every time the number of received data blocks reaches a predetermined number, the predetermined number of blocks stored in the buffer section is In a buffer control method that transfers data blocks to a processing device in the order of reception, a shift control circuit is provided that shifts the next received data block every time the predetermined number of data blocks are transferred to the processing device, and the processing device receives the predetermined number of data blocks. 1. A buffer control method characterized in that, when a predetermined number of data blocks have been transferred, the next received data block is shifted and stored in a buffer area that had previously stored the predetermined number of data blocks.