AU2561192A - Multichip ic design using tdm - Google Patents

Multichip ic design using tdm

Info

Publication number
AU2561192A
AU2561192A AU25611/92A AU2561192A AU2561192A AU 2561192 A AU2561192 A AU 2561192A AU 25611/92 A AU25611/92 A AU 25611/92A AU 2561192 A AU2561192 A AU 2561192A AU 2561192 A AU2561192 A AU 2561192A
Authority
AU
Australia
Prior art keywords
multichip
tdm
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU25611/92A
Inventor
Prabhakar Goel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of AU2561192A publication Critical patent/AU2561192A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Logic Circuits (AREA)
AU25611/92A 1992-08-28 1992-08-28 Multichip ic design using tdm Abandoned AU2561192A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1992/007299 WO1994006210A1 (en) 1992-08-28 1992-08-28 Multichip ic design using tdm

Publications (1)

Publication Number Publication Date
AU2561192A true AU2561192A (en) 1994-03-29

Family

ID=22231338

Family Applications (1)

Application Number Title Priority Date Filing Date
AU25611/92A Abandoned AU2561192A (en) 1992-08-28 1992-08-28 Multichip ic design using tdm

Country Status (2)

Country Link
AU (1) AU2561192A (en)
WO (1) WO1994006210A1 (en)

Families Citing this family (48)

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JP2002526836A (en) * 1998-09-30 2002-08-20 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Data carrier equipment
US6947882B1 (en) 1999-09-24 2005-09-20 Mentor Graphics Corporation Regionally time multiplexed emulation system
US6473726B1 (en) 1999-09-24 2002-10-29 Frederic Reblewski Method and apparatus for concurrent emulation of multiple circuit designs on an emulation system
US6961691B1 (en) 2000-03-30 2005-11-01 Mentor Graphics Corporation Non-synchronized multiplex data transport across synchronous systems
US7379859B2 (en) 2001-04-24 2008-05-27 Mentor Graphics Corporation Emulator with switching network connections
US6658636B2 (en) 2001-07-09 2003-12-02 Eric G. F. Hochapfel Cross function block partitioning and placement of a circuit design onto reconfigurable logic devices
US7305633B2 (en) 2001-10-30 2007-12-04 Mentor Graphics Corporation Distributed configuration of integrated circuits in an emulation system
US7035787B2 (en) 2001-10-30 2006-04-25 Mentor Graphics Corporation Emulation components and system including distributed routing and configuration of emulation resources
US7130788B2 (en) 2001-10-30 2006-10-31 Mentor Graphics Corporation Emulation components and system including distributed event monitoring, and testing of an IC design under emulation
US6817001B1 (en) 2002-03-20 2004-11-09 Kudlugi Muralidhar R Functional verification of logic and memory circuits with multiple asynchronous domains
US7286976B2 (en) 2003-06-10 2007-10-23 Mentor Graphics (Holding) Ltd. Emulation of circuits with in-circuit memory
US7693703B2 (en) 2003-08-01 2010-04-06 Mentor Graphics Corporation Configuration of reconfigurable interconnect portions
US7924845B2 (en) 2003-09-30 2011-04-12 Mentor Graphics Corporation Message-based low latency circuit emulation signal transfer
US7587649B2 (en) 2003-09-30 2009-09-08 Mentor Graphics Corporation Testing of reconfigurable logic and interconnect sources
US7826243B2 (en) 2005-12-29 2010-11-02 Bitmicro Networks, Inc. Multiple chip module and package stacking for storage devices
GB2452271A (en) * 2007-08-29 2009-03-04 Wolfson Microelectronics Plc Reducing pin count on an integrated circuit
US8959307B1 (en) 2007-11-16 2015-02-17 Bitmicro Networks, Inc. Reduced latency memory read transactions in storage devices
US8214192B2 (en) 2008-02-27 2012-07-03 Mentor Graphics Corporation Resource remapping in a hardware emulation environment
US8594966B2 (en) * 2009-02-19 2013-11-26 Advanced Micro Devices, Inc. Data processing interface device
US8665601B1 (en) 2009-09-04 2014-03-04 Bitmicro Networks, Inc. Solid state drive with improved enclosure assembly
US9135190B1 (en) 2009-09-04 2015-09-15 Bitmicro Networks, Inc. Multi-profile memory controller for computing devices
US8447908B2 (en) 2009-09-07 2013-05-21 Bitmicro Networks, Inc. Multilevel memory bus system for solid-state mass storage
US8560804B2 (en) 2009-09-14 2013-10-15 Bitmicro Networks, Inc. Reducing erase cycles in an electronic storage device that uses at least one erase-limited memory device
US9372755B1 (en) 2011-10-05 2016-06-21 Bitmicro Networks, Inc. Adaptive power cycle sequences for data recovery
US9043669B1 (en) 2012-05-18 2015-05-26 Bitmicro Networks, Inc. Distributed ECC engine for storage media
US9423457B2 (en) 2013-03-14 2016-08-23 Bitmicro Networks, Inc. Self-test solution for delay locked loops
US9916213B1 (en) 2013-03-15 2018-03-13 Bitmicro Networks, Inc. Bus arbitration with routing and failover mechanism
US10489318B1 (en) 2013-03-15 2019-11-26 Bitmicro Networks, Inc. Scatter-gather approach for parallel data transfer in a mass storage system
US9501436B1 (en) 2013-03-15 2016-11-22 Bitmicro Networks, Inc. Multi-level message passing descriptor
US9672178B1 (en) 2013-03-15 2017-06-06 Bitmicro Networks, Inc. Bit-mapped DMA transfer with dependency table configured to monitor status so that a processor is not rendered as a bottleneck in a system
US9875205B1 (en) 2013-03-15 2018-01-23 Bitmicro Networks, Inc. Network of memory systems
US9842024B1 (en) 2013-03-15 2017-12-12 Bitmicro Networks, Inc. Flash electronic disk with RAID controller
US9720603B1 (en) 2013-03-15 2017-08-01 Bitmicro Networks, Inc. IOC to IOC distributed caching architecture
US9934045B1 (en) 2013-03-15 2018-04-03 Bitmicro Networks, Inc. Embedded system boot from a storage device
US9798688B1 (en) 2013-03-15 2017-10-24 Bitmicro Networks, Inc. Bus arbitration with routing and failover mechanism
US9734067B1 (en) 2013-03-15 2017-08-15 Bitmicro Networks, Inc. Write buffering
US9430386B2 (en) 2013-03-15 2016-08-30 Bitmicro Networks, Inc. Multi-leveled cache management in a hybrid storage system
US9971524B1 (en) 2013-03-15 2018-05-15 Bitmicro Networks, Inc. Scatter-gather approach for parallel data transfer in a mass storage system
US10120694B2 (en) 2013-03-15 2018-11-06 Bitmicro Networks, Inc. Embedded system boot from a storage device
US9400617B2 (en) 2013-03-15 2016-07-26 Bitmicro Networks, Inc. Hardware-assisted DMA transfer with dependency table configured to permit-in parallel-data drain from cache without processor intervention when filled or drained
US10042792B1 (en) 2014-04-17 2018-08-07 Bitmicro Networks, Inc. Method for transferring and receiving frames across PCI express bus for SSD device
US10055150B1 (en) 2014-04-17 2018-08-21 Bitmicro Networks, Inc. Writing volatile scattered memory metadata to flash device
US10025736B1 (en) 2014-04-17 2018-07-17 Bitmicro Networks, Inc. Exchange message protocol message transmission between two devices
US9811461B1 (en) 2014-04-17 2017-11-07 Bitmicro Networks, Inc. Data storage system
US9952991B1 (en) 2014-04-17 2018-04-24 Bitmicro Networks, Inc. Systematic method on queuing of descriptors for multiple flash intelligent DMA engine operation
US10078604B1 (en) 2014-04-17 2018-09-18 Bitmicro Networks, Inc. Interrupt coalescing
US10552050B1 (en) 2017-04-07 2020-02-04 Bitmicro Llc Multi-dimensional computer storage system
CN110825667B (en) * 2019-11-12 2022-03-11 飞腾信息技术有限公司 Design method and structure of low-speed IO device controller

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4656620A (en) * 1984-09-19 1987-04-07 Itt Corporation Apparatus for obtaining reduced pin count packaging and methods
US4758747A (en) * 1986-05-30 1988-07-19 Advanced Micro Devices, Inc. Programmable logic device with buried registers selectively multiplexed with output registers to ports, and preload circuitry therefor

Also Published As

Publication number Publication date
WO1994006210A1 (en) 1994-03-17

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