AT389609B - TV SIGNAL SCAN SYSTEM - Google Patents

Description

No. 389609

The invention relates to a television signal sampling system with a source of television signals to be sampled, with a clock signal generator for generating clock signals with a sampling frequency of 13.5 MHz ± nx 2.25 MHz, where n = 0, 1, 2 ....., with a scan generator that works with the

Clock signal generator and the source of television signals is connected and provides samples of the television signals at this frequency.

Various properties of a world standard for compatible digital television were examined. It has been variously suggested that the same number of samples should or may be present in both the 525-line 60 Hz system (NTSC) and the 625-line 50 Hz system (PAL / SECAM) during the entire duration of a horizontal line the same number of scans during that part of the line interval in which image information is actually transmitted, which part is referred to as the active part of a line hereinafter.

The sampling interval, which comprises the remaining part of the line interval, is not only formed by the retrace interval, but also contains the dark area (off-screen area) of the trace interval. For such a world standard it should also be borne in mind that the sampling frequency must be suitable for systems with limited bandwidth and nevertheless adequate resolution is available, and whether the standard should be a composite color television system, which is in conflict with component systems such as RGB or YIQ.

It is also desirable to have a digital television standard that is hierarchical. A hierarchical system is one in which different degrees or levels of information can be easily transferred, e.g. B. by filtering or omitting sampling points. Thus, a digital system can enable the generation of signals with a very high sampling rate, which results in a resolution that is suitable for cinema-like use. Such a resolution could be 2000 lines per raster in the vertical direction and 2000 television lines horizontally. TV studios may wish to use a resolution higher than standard television resolution for editing reasons, but may wish to use facilities that cost less than those operating at data speeds corresponding to a 2000 line grid. Thus, a television studio could use facilities that use the second level of the hierarchy, which is 1000-line resolution, if a tape recording originally made at 2000-line resolution is available in a television viewing studio by filtering and omitting every other sampling point in FIG each line the resolution reduced to the 1000-line level. The next level in the hierarchy can be 500-line resolution, which can be used in a television broadcaster to generate analog video signals for broadcasting the broadcast. A television carrier-released record carrier could be used by the television broadcaster in a facility operating at 500-line resolution, with every other scan signal being omitted. A television broadcaster could also transmit a 2000-line resolution record carrier by omitting three out of four consecutive scanning signals. The next level in the hierarchy could be used for electronic cameras with a 250-line resolution, while the next lower level of resolution can be used for surveillance purposes.

It is generally expected that in the United States and other countries that use the NTSC standards, this facility will be generally available for processing television signals in a composite form. With such a device, it is extremely advantageous if the sampling frequency is a multiple of three or four times the color subcarrier frequency (3 x fsc, 4 x fsc). It appears that the world standard for digital television will eventually emerge when it is introduced , is not based on a sampling frequency that is firmly coupled to a color subcarrier. However, it is very desirable if a sampled composite video signal coupled to a subcarrier can be easily encoded so that it will have the characteristics of the standard when this standard is introduced. It is highly likely that this transcoding will require interpolation of the values of the samples in the world standard from the values of the closest samples of the composite NTSC television signal. If the clock frequency samples of the different standards were identical, the sample values would of course also be identical, so that no interpolation would be necessary. Exact interpolation is complex and cumbersome and requires multiplications and additions for each interpolated scan. However, multipliers in particular work slowly, and in order to achieve a workflow with high video data speeds, expensive multipliers are required. It is highly desirable to have a world television digital standard that is compatible with the 625/50 and 525/60 standards in terms of sampling frequency, that is hierarchical, and that is also easily derived from the composite NTSC video signal without the use of multipliers, that is scanned with a multiple of the subcarrier sequence, can be transcoded.

The original NTSC standard horizontal line fire sequence for black and white television was 15,750 Hz. With the introduction of color systems, the line sequence was changed to be related to the 4.5 MHz sound carrier frequency. The exact horizontal line frequency is 1/286 x 4.5 MHz, which the CCIR has standardized to 15,734.264 ± 0.0003% Hz. Recently the FCC has the color carrier frequency in MHz as the. Quotients 315/88 defined, and the line sequence is 2/455 times the color carrier frequency, which results in approximately 15,734,266 In the 625/50 standard, the horizontal line frequency is 15,625 Hz.

It is known that a usual clock frequency of exactly 13.5 MHz exactly 864 samples per horizontal line -2-

No. 389609 in the 625/50 system, and that in the 525/60 system this results in exactly 858 samples per line. The 13.5 MHz sampling frequency (and other sampling frequencies associated with multiples of 2.25 MHz) result in integer samples per line in both systems.

The duration of the horizontal line is 64.00 ps in the 625/50 system and about 63.56 ps in the 525/60 system. The CCIR standards for the 625/50 system provide an active line duration of approximately 52 ps, which corresponds to a blanking or return period of 12 ps. The blanking time for the current NTSC color standard is 10.9 ± 0.2 ps, but proposals have been made to change this standard. The blanking time in the NTSC standard is therefore not clearly defined. Assuming that the active line duration in the 525/60 system is also 52 ps, a 13.5 MHz sampling frequency creates 702 samples in the active portion of each line. However, the number of samples that occur during the blanking section differs by 162 in the 625/50 system from 156 in the 525/60 system.

The aim of the invention is to avoid the disadvantages of the known solutions and to propose a scanning system of the type mentioned at the outset that is suitable for various standards for digital television systems

This is achieved according to the invention in that a sample value selection circuit for selecting a fixed number of sample values of active, image-forming parts of a line interval of the television signal to be processed is coupled to the sample generator, the number corresponding to a number of powers of two

This makes it possible, instead of all active sample values representing image information, which are obtained by sampling at a predetermined sampling rate of e.g. B. 13.5 MHz or another frequency, which is an integer multiple of 2.25 MHz, are generated, only a certain number of

Samples are selected for which number represents a multiple of 16 (= 2 ^) or generally speaking has a multiplicity of powers of the number 2.

This enables simple implementation from one standard to another in a simple manner and with relatively little effort.

The invention will now be explained in more detail with reference to the drawings.

The drawings show in detail:

1 shows the block diagram of a conversion device with a digital section according to one aspect of the invention;

Fig. 2 timing signals used in the arrangement of Fig. 1;

3 shows a time diagram of the relative sampling times in the transcoding of composite NTSC color television signals into signals according to the standards of the arrangement according to FIG. 1;

Fig. 4 is a graph showing the errors that occur in transcoding by interpolating values of the original sample signal at the new sample points;

5 is a block diagram of an embodiment of the invention including transcoding;

Figure 6 is a timing diagram showing the relative sampling times when PAL signals are transcoded into signals according to the standards of the arrangement of Figure 1;

Figure 7 shows a list of interpolation weighting factors for PAL transcoding;

Figures 8, 9 and 10 generalized waveforms showing the errors that generally occur in transcoding by interpolation;

FIG. 11 shows the block diagram of a generalized interpolator similar to the interpolator from FIG. 5;

12 is a more detailed block diagram of a generalized interpolator for improved signal interpolation in PAL 13.5 MHz transcoding;

13 shows the block diagram of a digital arrangement with which an input signal (x) is divided by a number of the form 2r and this result is multiplied by a continuously changing variable (p);

14 is a block diagram of a generalized interpolator in accordance with one aspect of the invention;

15 shows the list of a conversion (s) to (n ') for a specific transcoding; and

16 shows the block diagram of another embodiment of a converter from (n) to (η ').

1 shows an arrangement according to the invention. Analog signals red (R), green (G) and blue (B) come from a signal source (not shown), such as a television camera, together with horizontal synchronizing signals ( H) on. The (H) signal is fed to the preparation input of a counter (150), while the signals (R), (G) and (B) are fed via their special lines to a corresponding “anti-alias” pre-filter (10) in which the bandwidth is limited in order to avoid the occurrence of overlap errors in the output signal. The bandwidth-limited signals (R), (G) and (B) are fed to an analog / digital converter (12) (hereinafter referred to as (ADC)), within which the separate signals (R), (G) and (B ) are sampled and quantized with a 13.5 MHz sequence, for which purpose a clock signal is supplied from a clock generator (14) for control purposes. ADC (12) can output the signals (R), (G) and (B) at its output terminals in the form of many parallel channels for each signal or a single series channel for each signal. In the exemplary embodiment shown, parallel lines are used for each signal (8)

The signals are fed from the ADC (12) to a gate (16) which is prepared by a flip-flop (18) -3-

No. 389609 to allow sample signals to pass through, or to prevent the passage of sample signals for subsequent digital signal processing, shown as block (20). Digital signal processing (20) is not part of the invention. This digital signal processing can perform tape recording, tape cutting, color control or mixing, or other special tasks. The digital signal processing device can also simply be a transmission channel via which the digital signals are fed to a remote location. After the digital signal processing, the signals no longer have to be in digital form, which is why they are fed to a digital / analog converter (hereinafter referred to as DAC (22)), where quasi-analog scanning signals are generated. These quasi-analog signals are input to a compensation filter (24) in order to generate a suitable analog video signal.

The gate (16) is prepared to determine the active path and is controlled so that exactly 704 strobe signals pass through the digital signal processing (20) during each path activation. The timing required for this is derived from the flip-flop (18), a counter (150) and a counter (704). (H) sync signals (204), which define the beginning of each horizontal line, are fed to the preparatory input of the counter (150), the second input of which is input by the 13.5 MHz clock signals from the generator (14). The counter (150) counts 150 clock or sampling pulses and, at the end of this time interval, emits an output pulse which is fed to the reset input of the counter (150), the preparation input of the counter (704) and the set input of the flip-flop (18), whereby the (Q) output of the FF (18) goes to (H) and prepares the gate (16), whereby this begins with the passage of the scanning signals. The counter (704) begins to count synchronously with the scanning signals passing the gate (16), and if exactly 704 strobe signals have been counted, the counter (704) outputs an output signal, whereby this counter is reset; the output signal also comes to the reset input of the flip-flop (18) and thereby sets the (Q) output to (L), whereby the gate (16) is blocked and no further scanning signals are passed, so that the end of an active Part of a line is determined

The operation of the timing arrangement of FIG. 1 and the differences between the 525/60 and 625/50 operations can be seen more clearly from FIG. 2. 2a, the clock sampling signals (202) are shown without a time scale. 2b shows the horizontal synchronization pulses (204) which occur with a nominal frequency of 15,734.266 Hz. At the time (tO), which corresponds to the beginning of the horizontal line, the counter (150) counts up to the time (tl50), as shown in FIG. 2c, which emits an output pulse at the time (1150) through which the passage of samples through the Gate (16) begins and through which the counter (704) is prepared, which counts up to time (t854) as shown in FIG. 2d. Fig. 2e shows the time remaining until the next horizontal synchronization signal that starts at time (t858). The second part of the blanking interval, which is determined by the duration shown in FIG. 2e, takes up 4 scanning signals. Fig. 2f shows that the horizontal synchronization signals occur with a nominal frequency of 15.625 Hz. The duration of the counting process of the counter (150) is shown in FIG. 2g, the duration of the counting process of the counter (704) in FIG. 2h, which latter has ended as in the first case at the time (t854). However, the blanking interval is now longer and extends from time (t854) to time (t864) where the next horizontal synchronization signal occurs and a new cycle begins

Since the active part of a line in the system described is defined by 704 scanning signals, the rest of the line or its interval is by definition the blanking. The 150 counts of counter (150) essentially determine the total blanking interval that would occur if the input signal to the system came from a 525/60 source. For such a source, the portion of the blanking interval determined by the counter (150) is greater than the portion of the blanking interval that occurs after the time (t854) in which the counter (704) and the flip-flop (18 ) are reset until the time (tO) of the next »! Horizontal sync pulse. Thus, the first portion of the blanking interval occurs after each (H) sync pulse and is determined by the counter (150). The second part of the blanking interval begins after the active part of a line and lasts until the next H-sync pulse occurs. Thus, the duration of the second portion of the blanking interval that occurs in each line changes depending on the duration of a horizontal line which is from Source standard is determined.

The meaning of the number 704 results from the fact that 704 contains a larger number of powers of the number 2 (704 = 2 ^ x 11), so that it can determine 6 hierarchical levels. In addition, the number of 704 strobe signals per line enables the 625/50 system to obtain the exact blanking interval and the blanking interval obtained to be extremely close to the limits of the NTSC blanking interval

The arrangement of FIG. 1 represents a digital signal processing system according to the invention, in which the synchronization of the source can correspond to either the 625/50 or the 525/60 standard and in which the input signal is present in analog form. In many cases, however, it may be desirable to transcode from another digital system to the standards described in connection with the arrangement of FIG. 1. So it has already been mentioned that z. For example, in the United States and possibly other countries, it is desirable to have a digital video system in which the standard clock frequency is based on a multiple of the subcarrier frequency, such as 4 x fsc. It will also be described that the number 704 is also advantageous because it allows the transcoding between such a composite NTSC digital standard and the world standard described in connection with FIG. 1 in a simple manner.

For a composite NTSC television signal sampled at 4 x fsc, -4-

No. 389609 complete horizontal line 910 samples. Of these, 754 scans occur during the active part, the remaining 156 during the gating interval. To perform transcoding in accordance with another aspect of the invention, 748 samples per active section of each line are required. The number 748 is chosen because it has the divider 44 (748 = 17 x 44) in common with the number of samples in the world standard (704 = 16 x 44). This means that each horizontal line in the two systems can be divided into 44 transcoding blocks with one block containing 17 strobe signals in one case and 16 in the other. Fig. 3 helps to clarify this scheme. The time is plotted on the horizontal axis in FIG. 3. The length of the line in Fig. 3b is 16 units, each mark representing the time of a scan. The 16 samples in one block of FIG. 3b correspond to one of the 44 identical blocks that occur successively during the active part of a horizontal line in the digital world standard. The block of samples in FIG. 3a takes practically the same duration as the block of FIG. 3b. The block of samples in Fig. 3a, however, now contains 17 samples instead of the 16. Nevertheless, it will be appreciated that 44 blocks of samples as shown in Figure 3a occur within the same time of the 44 blocks of Figure 3b. By selecting the total number of samples so that they can be divided into relatively small blocks, the amount of signal processing required for transcoding can be significantly reduced.

Assuming that digital signals are available that occur with a sequence according to FIG. 3a, it is understandable that interpolation is required in order to obtain a signal according to the clock system of FIG. 3b. For example, the seventh scan signal in FIG. 3b is practically halfway between the seventh and eighth scan signals in FIG. 3a. Consequently, the value of the seventh signal in FIG. 3b can be approximately equal to the mean of the values of the signals (7) and (8) of the incoming signals which have a clock sequence according to FIG. 3a. The second signal (sample No. 1) in FIG. 3b is very close to the second sample signal (sample No. 1) in FIG. 3a, so that it can be assumed that its value is equal to the signal value of the sample signal (1) in FIG. 3 plus 1/16 the difference between the values of the sampling points (1) and (2). Generally speaking, the value (gn ') of the nth linearly interpolated output sample signal is determined by

Sn 85 ίη + @ n + l " in) W »16 where (n) can take the values from 0 -16 and is the number of scanning signals of the newly generated scanning signals. The fact that the factor 17/16 is a ratio of small integers and the denominator of the ratio is a power of 2 is used in the transcoding according to the invention.

In the curve (f (t)) of Fig. 4, assume that (fn) is the sequence of the scan signal values with a frequency of 4 x fsc, which is the frequency (Fj). The straight lines connecting successive sample signal values represent a linear approximation to the analog curve shape (f (t)), and the sample signal values marked with (gn ') form the interpolated values at a clock frequency of 13.5 MHz (F2) . 1 consists of two additions and one multiplication. One of the factors in the multiplication is the fraction n / 16, where (n) is a small integer. Although electronic multiplication of binary numbers is a complex and time consuming process, dividing by two can be accomplished very simply by shifting the contents of a shift register by one place. Any binary number, e.g. B. 234jo = IIIOIOIO2 can easily be divided by two by placing a zero to the left of the highest digit and omitting the lowest digit. The result is OIIIOIOI2 », which is half of the previous number, whereby the initial eight-digit binary number has become a seven-digit number. The multiplication of a scanning signal value by a factor of, for example, 7/16 can be carried out by dividing the initial scanning signal value (S) 4 times by the number 2, with 8/16 S, 4/16 S, 2/16 S and 1 / 16 S of the output sample signal value can be obtained. Then 7/16 times the value is obtained by adding the values obtained for 4/16 S, 2/16 S and 1/16 S one after the other. Each number can be multiplied in digital form by the factor n / 16 by four successive shifts and up to three successive additions. This technique can be generalized to any multiplier n / 2r for any integer (r).

The linear approximation in the technique described above can lead to errors in the interpolation process. The error in Fig. 4 corresponds to the difference between the value of the curve (f (t)) at the time (n) of the sampling point (gn ') and the point on the straight line (410) between (fn + j) and (fn) . This error can be small, especially if the interpolated result is quantized to the same number of levels as the input curve. The errors become particularly large at points of maximum curvature of the input curve and are always in the direction of the inside of the curvature. Such errors do not occur in areas of the image with a constant level or in linearly changing areas, but only in the vicinity of changes (curved downwards or upwards). These interpolation errors only occur in zones with high resolution or at abrupt transitions. The errors have the effect that the curvature is reduced or the picture edges -5-

No. 389609 can be made gentler.

The interpolation error resulting from the curvatures in the analog approximation (f (t)) from which the output samples (fn) were taken can be significantly reduced by using information taken from several of the surrounding points, namely three or four sampling points instead of two are used for interpolation. This is done by taking the extensions (412) and (414) of the approximation line between the two scanning signal points (fn.j) and (fn) and between (f "+ j) and (f" +2). If the time (n) of the occurrence of the new sample signal values (gn ') with the (F2) clock frequency is very close to the time of the sample value (fn> at the beginning of a block of sample values and very close to the time of the sample value (fn + j) can be towards the end of the block of samples, it becomes clear that the weight which the approximations (gn ") or (gn, n) have in determining the actual value (gQ) of the new sample at the time (n) is dependent on the proximity of the point in time of the sample (gn) to the sample (fn) or (fn + j). It can be seen from Figures 3 and 4 that each new sample signal value (gn) within a block of samples in is a one-to-one relation to an existing sample signal value (fn) and consequently the numbering of the new sample values (gn), as shown in FIG. 4, corresponds to the numbering of the old or output sample signal values (f ").

The value of (gn ") equals the known value of the output sample signal value (f ") plus a small part of the difference between the sample signal values (fn) and (fn. J) because this small additional value is the same whether it is between (n- 1) and (n) or between (n) and (n + 1). Thus, gn " = fn + - (fn- < n-l) C2) x 16

In the same way, the value (gn '") on the extension (414) can be determined in that the difference between the scanning signal values between (fn + j) and (fn + 2) to the known value of (fn + j) multiplied by one minus the additional part used to determine (gn "), so that we get: gn " ' = fn + l + - (fn + l-fn + 2) < & 16

It is understood that if the new sample signal value (gn) is close to the time of (fn), the value (gn ") "ώ some weighting can be added to the value determined for (gn ') by make an approximation, and if (gn) is close to the time for (f "+ j), then the value of (gn " *) can be added with a weight to the value of (gn ').

A good approximation for the new sample signal values (gn) is if (gn) is closer to (fn) (if n = 0,1,2, ..... 7) 16-nn (4), gn = Sn + gn 16 16 and if (g ") is closer to (fn + j) (if n = 9,10,11, ..., 15) n 16-n gn = - gn '" + -gn 16 16 -6- (5).

No. 389609 For n = 8 the results for (gn) from equations (4) and (5) are averaged to obtain: 1 1 1 g8 = “(” δδ " + - δδ " + g8 ^ (φ · 2 2 2

It should be noted that equations (4), (5) and (6) are sums of products in which the products have the form K / 16 g. As a result, the quadratic or parabolic approximations (gQ) of the function (f (t)) can be performed by successively dividing by two and summing, as was the case with linear interpolation.

Because of the concave curvature of (f (t)) below a tangent to (f (t)) at point (fQ), the interpolated value of (gn) between (gn ') and (gn ") is near the middle of the interval between (n) and (n + 1) somewhat larger than the actual value of (f (t)) before the sampling to form the values (fn) was performed. The errors made with the quadratic lite polishing method described lie in a direction that exaggerates changes, as a result of which transitions or edges appear more clearly in the television picture.

Fig. 5 shows an arrangement for performing the quadratic interpolation as described above. The clock frequencies (Fj) and (F £ are generated by a clock generator (502) and have a ratio

Fj 2r + l

which gives the desired possibility of dividing the scan signal times in each line into interpolation blocks or groups with temporally coincident scan signals at each end. An analog color television signal mixture (f (t)) is fed to a scanner (504), which samples the incoming analog signal in repeated succession and holds the scanning signals for a period sufficient for an analog / digital converter (506), the scanning signals in M bits quantize per sampling signal. As is known, the M bits can occur simultaneously on parallel lines or in succession on a single line. Each scan signal of M bit represents a scan signal value (fn). The various scan signals (f ") (e.g. fn, fn + j, fn + 2)) are successively stored in a register (508) where they are accessible , so that the different approximations (gn ', gn ", gn' ") and finally (gn) can be calculated.

The synchronization of the various computing processes with the blocks of scanning signals is achieved by the horizontal synchronization signals, which are separated from the analog input signal (f (t)) by a separating circuit (512). The separated synchronizing signals include the (H) synchronizing signal, the blanking, the recovered color carrier and the like. The synchronizing signals are fed to a synchronizer (526) which transmits a signal related to the color carrier to the clock signal generator (502) to lock the sampling clock frequency (Fj) and 4 x fsc. The synchronizer (526) also receives a signal indicating the fully counted state of N an r-stage counter (510) in order to be able to reset the counter (510). The synchronizer (526) also delays the preparation of the counter (510) until the beginning of the active part of each horizontal line. In the arrangement of Fig. 5, it has been assumed that the scan sequences are selected as described earlier in connection with the world digital standard for facilitating transcoding by interpolation from a scan signal sequence related to 4 x fsc, so that the number (r) in equation (7) is known and z. B. can have a whale like r = 4, which means recurring interpolation blocks in a length of 16 new scanning signals (gn) and 17 old scanning signals (fQ). The counter (510) receives signals from the synchronizer (526) indicating the beginning of the blocks and continuously counts (Fj) clock pulses and generates on line (514) a parallel digital signal representing the current value of (n) , which in the example can range from 0 to 15. The counter (510) is also reset, as mentioned, by the synchronizer (526) after each complete cycle counting process η = N. The current value of (n) on line (514) is input to a lookup table (516) which is addressed by a signal on line (514). Information is stored in each memory location as to which scanning signals near (fn) are to be used for the calculation for the respective value of (n). This information is input to a computer (518) in which (gn '), (gn ") and (g "' ") are calculated as determined by those in table (516) for the values of (n) according to equations (1), (2) and (3) -7-

No. 389609 stored commands. These calculations are carried out in the manner described by successively dividing by 2 of the different values (fQ) and summing the results of the different divisions according to the stored instructions.

Rounding errors can be kept small by having S (for the divisions by two and the additions in the shift registers) when performing the shifts. The values of (g "'). (gn ") and (gn " '), which have been calculated in the computer (518), are successively entered into a memory register (520) and are then available for a further calculation circuit (522), where the value of (gn) corresponds accordingly the instructions from the register (516) for the respective value of (n) are calculated to perform equations (4), (5) and (6). After calculating (gQ), the bottom 10 digits are dropped to get an M-bit output and (gn) is inserted into a buffer memory (524). The interpolated signals are emitted from the buffer memory (524) at the frequency (F2) and represent the transcoded signal.

The person skilled in the art learns that YIQ; Y, (B-Y), (R-Y) or components other than the components shown RGB can be used. He also understands that 15 the duration of the blanking interval, which is determined by the counter (150), can be set to the desired duration and position relative to the synchronization signal.

The interpolation device described so far relates to transcoding by interpolation of signals which are related to one another by a sampling frequency ratio Fj / F2 = M / 2r, where M is equal to (2Γ ± 1), as a result of which the (F2) sampling signals progressively over the time interval between consecutive 20 (F1) signals run as shown in Fig. 3 for the duration of a block of scan signals. In the specific example described, a frequency ratio F1 / F2 is determined by the ratio of 4 x fsc / 13.5 MHz, which corresponds to the ratio 35/33 and approximately to the ratio 17/16, so that it corresponds to equation (7) for corresponds to a value of r = 4. This enables the advantage of interpolation by successive shifting and adding. The advantages of interpolation by shifting and adding 25 are not limited to the case where the numerator differs from the denominator by the integer one, but occur with all positive integers M and r as long as M and 2r have no common divisor .

The transcoding or conversion between PAL signals with 625 lines per picture and 50 Hz picture sequence and the proposed 13.5 MHz world standard can be carried out by interpolation using this additional 30 method and can have a reduced interpolation error.

As shown in Fig. 4, the interpolated value for a new sample (gn) in the left half is determined for the interval between the times (n) and (n + 1) in the following manner. First, the incoming scanning signals (fn) and (fQ + j) occur at times (n) and (n + 1). Second, the amplitude differences are determined: between (f "_j) and (f") and between (fn) and (fn + j). Third, the amplitude differences according to the relative time position of the scanning signals under consideration within the

Sample signal blocks weighted. Fourth, each of the weighted differences is added to the value of (fn) to form a strobe signal that is linearly interpolated between (fQ) and (fn + j) and another strobe signal that ranges from (fn.j) and (fQ) is linearly extrapolated. The linearly interpolated and extrapolated scanning signals are then further weighted according to their proximity to (fQ) and summed to form an interpolated value. In the second or right half of the interval between (n) and (n + 1) a corresponding scheme with the points (fn), (f „+ j) and (fn + 2) is used. Thus, the interpolation scheme described in connection with FIG. 4 uses three samples of the incoming signal to determine each interpolated sample signal value. It is also possible to start from four sampling points of the output function at the same time in order to improve the interpolation process for each positive integer of M and r, as described.

A generalized transcoding scheme using any positive integers M and r finds e.g. B. Application when transcoding from the 625/50 PAL system to 13.5 MHz scanning signals according to the proposed world standard. For this transcoding process the PAL signals are sampled at 4 x fsc, whereby 1135.0064 scanning signals are obtained for each complete horizontal line. It is known that these signals can be corrected to exactly 1135 scanning signals per field, which only results in an error of 0.16% skew in the image geometry.

The ratio of 1135 scanning signals per PAL line to 864 scanning signals for the world standard line is the ratio 1135/864 = 1.3136574. This number is very close to the quotient 21/16 = 1.3125. Thus, the active part of the line of 704 samples at the 13.5 MHz world standard with samples from the 55 4 x fsc-PAL system can be made by converting 21 incoming signals with 4 x fsc to 16

Sample signals at 13.5 MHz in each block of sample signals are filled in at exactly 44 blocks per active line. -8th-

No. 389609

The result of the approximations made with such a transcoding is a geometric accuracy of (12/16) (864/1135) = 0.9991186, which leads to a geometric distortion in the form of an elongation of less than 0.1% or horizontal distortion of less than 1% are generally considered acceptable because they are within the tolerance limits that cameras and film projectors can reach. The distortions introduced by the approximations contained in the transcoding are considerably smaller than these limit values and are therefore permissible.

Within each transcoding block of scan signals when converting from NTSC to world standard, as described above, the position of each new scan signal (gn) progressively rises above the time interval between the incoming scan signals with a regular increase. At the beginning of each block (gn) occurs simultaneously with (f ") and with increasing time it moves between the successive scanning signals (fn) and (fn + j) until the end of the block of scanning signals (gn) to be transcoded occurs with (fn + j). This regular progression results from the additional number 1 in the numerator of equation (7). This numerator is designated with M. In the case of the PAL signal, M differs from the denominator by a value greater than 1. When Ttanscoding from PAL to world standard, the quotient is obtained

Fl M 2r + 5 21 - - - ----- (8), F2 2r 2r 16 where the numerator is M 21 and differs from the denominator 16 by 5. This difference means that in each block to be transcoded 21 scanning signals of the incoming signal occur within an interval in which 16 new transcoded scanning signals are generated. This is shown in FIG. 6. As in the case of Fig. 3, the length of line (b) represents the duration of an interpolation block and is divided into 16 positions which represent the sampling times. Points (a) are the sampling signal instants of the incoming signal. The difference M-2r has a second meaning, which is related to the first. This second meaning can be explained with reference to FIG. 6, from which it can be seen that each new scanning signal point (points on line (b) in FIG. 6) between the sampling signal points (a) of the incoming signal in a time position is the (M-2r) / 16 or 5/16 of a sampling signal interval from the previous position. The sampling signal points (0) appear simultaneously, the new (b) signal point (1) therefore appears on 5/16 between the incoming (a) signal points (1) and (2), the new signal point (2) appears 5/16 + 5/16 = 10/16 of the route between the incoming (a) Signal points (2) and (3). In the same way, * new points (3) appear on 15/16 of the path between the incoming signal points (3) and (4), the new signal point (4) appears at a time (15/16 + 5/16) -1 = 20/16 · 16/16 = 4/16 along the time interval between the incoming signal points (5) and (6). The new or outgoing scan signal (5) appears shifted 4/16 + 5/16 = 9/16 between the incoming scan signals (6) and (7) compared to signal (6), and the new scan signal (6) appears at time 9 / 16 + 5/16 = 14/16 shifted from the incoming scanning signal (7) to the scanning signal (8). 7 shows a list of all the positions occurring in FIG. 6. There are no new scanning signals in the time intervals between the incoming scanning signals (4-5; 8-9; 12-13 and 16-17). 15 shows a list of the corresponding information for a transcoding in which r = 4 and M = 25.

The interpolations described in connection with Figure 4 use the approximation for (gn) (where the new value is estimated) (gn ") weighted by a first set of functions in the first half of the interval between successive incoming strobe signals (fn) and a second weighting function in the second half of the interval. This results in an interpolation that is useful under certain conditions, but a better approximation (less error) can be achieved by taking an average of the weighted assumptions (gn ', gn " and g ""') over the entirety of each inter-sampling interval becomes. Such an average is 2r-n ’n’ gn = 1/2 (gn ’+ -gn " + - gn " ·) (9), 2r 2r

No. 389609 wherein n '= [(M-2r) xn] (modulo 2r) (10). (n ') takes into account the position of the new load value (b) in relation to the incoming sample values (a). 6 there is n '= (21-16) n modulo 16 = 5n modulo 16 (11), which means that for each new sample (n) the value for (n') increases by 5 parts of 16, as stated above.

The approximation to (gn) of equation (12) as shown in Fig. 8 represents a parabola that passes through the points (fn, fn + j). As can be seen, the parabola has a higher vertex than a third-order curve that runs through the four points (fn.j, f ", fn + j, fn + 2).

Another interpolation scheme is shown in FIG. 9. A first parabola (900) is placed through the points (fn.l, fn and fn + 1), while a second parabola (902) runs through the points (fn, f "+1, f" +2).

These can be given by the following equations: 2r + n '2r-n' (900) gn = 1/2 (-gn * + -gn ") (12), 2r 2r 2r + ln 'n' (902) gn = 1/2 (-gn '+ - gn' ") (13). 2r 2r

In the interpolation of a new scanning signal (gn) between the time (n) of the scanning signal (fn) and the time (n + 1) of the scanning signal (fn + j), the equation (12) in the first half, as described earlier of the interval and equation (13) in the second half and the average of both in the center. On the other hand, the average over the entire interval gives the equation 2r-n 'n ’gn = l / 4 (3gn' + -gn " + - gn '") (14). 2r 2r

Another approximation of the value of the new strobe signal (gn) interpolated between successive strobe signals (fn) can be made so that equation (12) is weighted more near the beginning of the interval and equation (13) is weighted more becomes near the end of the interval, for which the equation is then: 2r-n 'n' gn = - (right side of Eq. 12) + - (right side of Eq. 13) (15). 2r 2r

Fig. 10 generally shows the differences between the values of new sampling signals (gn) when they are determined by interpolation approximations as given by equations (9) and (14), respectively. The solid curve (1009) has the shape of a parabola according to equation (9), while the dashed curve (1014) has the shape of a parabola according to equation (14). Curve (1009) is relatively strongly curved and falls below points (fn_j) and (fn.2), while curve (1014) is less strongly curved and lies above these points. It was mentioned the fact that interpolation can be set up so that the transitions are amplified and thus an image is created that is less " soft " or its contours are accentuated more sharply. From Fig. 10 it can be seen that interpolation using equation (9) creates new scanning signal values which, in the region of strong curvatures, increase the contour mapping compared to those obtained according to equation (14).

Equations (4) - (6) and (9) - (14) are approximate equations that share the property -10-

No. 389609 have going through points (fn) and (fn + j) and which are the sums of multiplications or products of four scanning signal points fn, fn + j and fn + 2 > and in which the factors have the form p / 2r, where (p) is an integer that lies between the values 0 and 2r + ^. According to the invention, these algorithms can therefore be treated by a sequence of shifts and additions, which can be carried out in a simple manner at high speed

A circuit arrangement as shown in FIG. 11 can be used to carry out a transcoding of a general type, as described above. In Fig. 11, the circuit elements corresponding to those in Fig. 5 are identified by the same reference numerals. Clock pulses with a pulse sequence (F2) are counted in an r-stage n counter (510), which is reset to zero by the timing control (1104) when the last count state of 2r-1 is reached (for the example PAL reset) at 15). For each Wat of (n) from the r-stage counter (510), the fixed value instruction register (516) selects the appropriate instructions for calculating values (gn's gn " and gn " ') from the continuously stored values of (fn) in the storage register (508 ) out.

FIG. 12 shows a more detailed block circuit, an embodiment of a generalized transcoder which is suitable for transcoding PAL signals (approximately 17.7 MHz) to 13.5 MHz sampled with 4 x fsc. Analog composite PAL signals (f (t)) are fed via the input (1210) to a block (1212) which works as a prefilter, sampler and analog / digital converter for 17.7 MHz. The sampling in block (1212) is controlled by the (Fl) clock. The output from block (1212) is a plurality (in this case 8) of parallel signal-carrying channels or lines, one of which is the lowest digit (LSB) and another the highest digit (MSB). The signals on these lines are fed in parallel or simultaneously to an equal number of shift registers in a block (1214). Only the shift registers for the (LSD) and (MSB) signals are shown in block (1214). The clocking of the shift registers (1214) control timing signals generated in a timing circuit (1216). The timing circuit (1216) receives, in addition to the (Fl) clock pulses, certain synchronization information related to the incoming PAL signal so that the processing of the incoming signals is synchronized to transcode blocks that begin with the video signal. The latest signals in the shift registers correspond to (fn + 2) the oldest (f ".]) ≫ while (fn) and (fn + j) are stored at the intermediate locations. These 8-bit signals are used by the

Shift registers (1214) are fed to the inputs of difference generator circuits (1218, 1220 and 1222). Thus (fn) and (f „_j) are given on (1218), (fn + j) and (fn) on (1220) and (fB + 2) UI, d (fn + i) on (1222). These difference generator circuits also receive timing inputs (T) from the timing circuit (1216) so that their workflow is synchronized with the strobe signals. The outputs of the difference generator circuits (1218) and (1220) are input to the inputs of multipliers (1224) and (1226), respectively, which multiply them by n '/ 16, which, as described, by dividing several times by two and adding as a function of Value of the current variable (n ') takes place, which are supplied to the multipliers from the fixed value information table (1228). As mentioned above, (η ') indicates the temporal position of the new sample with respect to the instants of the neighboring incoming samples. With the given transcoding from PAL to 13.5 MHz, the frequency ratio is known, and therefore the one-to-one correspondence from (n ') to the scan number is known, as used e.g. B. are listed in the table of FIG. 7. The read-only memory (1228) is addressed by information which depends on the clock frequency (F2) since new scanning signals which are counted by a counter (1230) as blocks (n). Each memory location addressed in this way is previously provided with information which is related to the value of (η ') and corresponds to an address number (n) for a specific coding. Thus, for each new scanning signal that is generated within a transcoded block, the multipliers (1224 ) and (1226) from the read-only memory (1228) an associated value of (n '), which defines the additions that have to be made with the difference signals divided by two.

The output signal from the multiplier (1226) is fed to an adder (1232) where it is summed with the current value of (fn) to form a linear interpolated sample signal (gn ') as by

Equation (1) described. In the same way, the output signal from the multiplier (1224) is fed to a clock-controlled adding circuit (1234), where it is summed with (f ") to form a linearly extrapolated sample value (gn") according to equation (2). The current (n ') value is transferred from the read-only memory (1228) to a circuit (1236) which forms a differential, and the difference signal is input to a multiplier (1238). The difference signal (fn + j - fn +2) that was created in the difference generator circuit (1222) comes to a second input of the multiplier (1238), which forms a product by dividing it several times by two and adding it depending on the value of (16-n ') to produce a product signal which is supplied to an adder (1240) for summing with the value of (fn + j) to form the value (gn " ') according to equation (3).

The (gn ') value is determined by means of a further multiplier (1242) of a summing circuit (1244) -11-

No. 389609 entered. The multiplier (1242) multiplies by a constant value 11/16, which has the form n / 16 and can therefore be carried out with the aid of circuits and adders divided by two. The (gn ") and (gn '") values are weighted by multipliers (1246) and (1248) according to the position of the new sample (gn) with respect to the adjacent incoming samples.

The multiplier (1248) multiplies by n '/ 16 and receives the running variable (n') from the read-only memory (1228) for this purpose. The multiplier (1246) multiplies by (16-n ') / 16 and receives the difference signal (16-n') as a running variable from the difference generator circuit (1236). These two multipliers are the desirable, high speed, shift and add circuits as described below. These weighted signals (gn ") and (gn" ') are added together in a summing circuit (1250). At the output of summer (1250) the signal is the sum of a small part of (ga ") and a large part of (gn '") > where (η ') is Hein, which is the case when the new sample (gn) is close to the sample (fn). If the new sample (gn) is close to the value (fn + j), i. that is, if (n ') is close to 16, then the summer (1250) generates the signal using a large portion of (gn) and a large portion of (gn'). This weighting brings an approximately calculated value of (f (t)) if the analog

Input signal has strongly protruding peaks. In order to reduce the contrast, the summed signal at the output of the summer (1250) is multiplied by a fixed factor 5/16 in a multiplier (1252), whereby the weight, which is due to the influence of the peak value, compared to the linear approximation (gn ') is reduced. The weighted with 11/16 (gn ') and 5/16 weighted (gn ") and (g "* ") -

Signals are summed in the summer (1244) and its output is rounded off to generate the new, approximately calculated value (gn)

It has become clear that the value of the weighting of the signals by the multipliers (1242) and (1252) can be varied as desired, whereby a desired degree of emphasis on the transitions can be generated. The highlighting effect can be included in the algorithm with which the new scanning signals are formed: 2r-k k 2r-n * n ’

Sn = -gn '+ ~ (-8n " + - gn ") 06). 2r 2r 2r 2r where (k) is a contrast constant that can be zero or a positive value up to the maximum value of 2r. When k = 0, the second expression becomes zero, and the interpolated value of (gn) is only the linear interpolation (gn ') according to equation (1). The part of the right expression of equation (16) in the parentheses represents a parabola which is adapted to the values (fn and fn + j), but a much stronger one

Has curvature than would be expected from the input signal (f (t)). Since (k) lies in the range between zero and 2r, equation (16) gives all possible parabolas that run through the values (fn and fn + 1) and between the straight line (gn ') and the very strongly curved parabola in the bracket of equation (16).

A Wat k = 8 z. B. equation (9) gives a value (k) = 4 equation (14). In Fig. 12, the value (k) is comprised by the fixed constant multipliers (1242) and (1252). The multiplier (1242) multiplied by (16-k) / 16 and the multiplier (1252) by k / 16 , where (k) = 5, and the transcoder operates generally according to equation (16).

The multipliers (1224, 1226, 1238, 1246 and 1248) multiply by the quotient of a running variable divided by 2r, where (r) = 4 and 2T = 16. The multipliers (1242) and (1252) have the same form, but a numerically fixed counter. 13 shows the block diagram of a digital device for dividing the input signal (X) by a number of the form 2r and multiplying the result by a running variable, which is denoted by (p). In FIG. 13, the running variable (p ) to an input terminal (1310) and the multiplicand (X) to an input terminal (1320). The multiplicand (X) reaches (in series or in parallel) a register (1322) which, in the example shown, has an 8-bit digital word 10000001 is loaded, which represents the value 129. The highest position (MSB) of the register (1322) represents the value 128 itself. The division by two is achieved by entering the content of the register (1322) in the last eight stages of a 9-digit second register (1324) becomes. The highest position of the register (1324) also represents the value 128 and is preloaded with the value zero. Consequently, the transition from 10000001 from register (1322) to register (1324) results in a division by two. The value stored in 9-digit register (1324) is transferred to the last 9 digits of 10-digit register (1326), whose highest position is preloaded with the Wen of 128. The transfer of the data from the register (1324) into the register (1326) thus represents a further division by two. The data is again transferred by subsequent transfer to the 11-digit register (1328) and the 12-12-

No. 389 609 digit registers (1330) divided. At the end of the transfer process, the registers (1324, 1326, 1328 and 1330) contain the contents (X / 2, X / 4, X / 8 and X / 16). Since these components represent 8/16 X, 4/16 X, 2/16 X and 1/16 X, it is easy to understand that each partial value of (X) between 1/16 and 15/16 is the sum of the different combinations of the shared values and the registers stored. In the example shown, (p) has the value 7 (digital 0111), so that the content of the registers (1326, 1328 and 1330) must be summed to form a sum of 7/16 X. The value of (p) is read into a register (1332). The content of each stage of the register (1332) is used to control the opening of the registers (1324 to 1330) as represented by the gates (1334 to 1340). A value of one in one stage of the register (1332) enables the associated register (1324 to 1330) to be opened for the subsequent summing circuits. Registers (1324) and (1326) are connected to the inputs of a summing circuit (1342) and registers (1328) to (1330) are connected to the inputs of a summing circuit (1344). The outputs of the summing circuits (1342 and 1344) are in turn connected to the inputs of a further summing circuit (1346), from which the output signal (p / 16 X) is finally formed. The blocks adjacent to the summers (1342, 1344 and 1346) represent the digital values in these points.

The exemplary embodiments described so far take advantage of the multiplication by shifting and adding, but interpolators of a more general form according to FIG. 14 can also be used. The sampling rate of the input and output signals are chosen so that an integer number of transcoding blocks are created during each of the active part of the targets with simultaneous input and output sampling signal instants at the beginning and end of each transcoding block. Such interpolators have advantages compared to the prior art, even if ordinary multipliers are used, since only a few multipliers are required to achieve a certain accuracy. The interpolator according to FIG. 14 with only 4 multipliers corresponds to an arrangement in the prior art with 15 multipliers.

In Fig. 14, an input signal is supplied through an input terminal (1410) to the inputs of a delay element (1412) and a synchronizing or timing circuit (1424). The delay element (1412) delays the signal by a known amount and thus generates a delayed signal (fn) which defines the input signal as (fn.j). The delayed signal (fQ) continues to one

Delay element (1414) and then fed to a delay element (1416), whereby further delayed signals (fn + i and fn + 2) are produced. The signals (fn-l > fn > fn + l and ^ n + 2 ^ are applied to multipliers, which can usually be 8 x 8 multipliers, which convert the signals to a known function (taken from a tabular read-only memory (1420 )) multiply the current variable n generated by a synchronization or timing circuit (1424) The multiplied signals are summed in an adder (1432) to form the desired interpolated output signal at the output terminal (1422).

Instead of a tabular read-only memory such as the memory (1228) of FIG. 12 for the formation of the value of (n ') from the value (n) according to the known pattern of the line position of the new scan signal (gn) between the time positions of adjacent incoming scan signals (fn ) for a given general transcoding, it is possible to use a logic circuit to calculate (n ') from (n) according to the equation n' = (M-2r) xn (modulo 2r). Such a logic circuit is shown in FIG. 16

In FIG. 16, the input clock signals at the output or the new clock signal frequency (F2) are fed to a stage n counter (1230), as in FIG. 12. The (F2) clock signals are also fed to a timing circuit (1616). supplied, the reset pulses for the counter (1230) and for an n'-counter (1618) at the end of a count of 2r (F2) clock pulses generated by the counter (1230). Such a reset signal clears the contents of the counters (1230) and (1618) at the beginning of each recurring block of strobe signals. The counter (1230) counts (F2) clock pulses to determine the current values of (n), the number of output pulses within each interpolation block. The counting status stored in register (1230) is shown at 13 (1101). With each successive (F2) clock pulse, the timing controller (1616) drives a clocked adder (1620) that was at the value of (n ') currently stored in the (n') register (1618) (as shown) the last or previous value of (η ') 13 or 1101), adds a fixed number (M-2r) represented by 5 (0101). The sum of these two is stored in a register 1622, which has r + 1 levels and in which the left level is the highest. The sum of 5 and the previous value of (n ') 13 is 18 or 10010, which is stored in the register (1622) as a running value. The lowest (r) levels of the register (1622) are with corresponding levels of the register (1618 ) to update the value of (n ') to the current value. However, since only the lowest levels or places of the register (1622) are connected, only these are entered into the register «(1618) as a new value (n ').

This arrangement causes the value of (n ') in units of five (M-2r) for each count of (n) -13-

Claims (17)

No. 389609 progresses until the sum exceeds the value (2r-l), where the highest digit in the (r + l) th stage of the register (1622) switches to logic state 1. The transmission of the (r) lowest levels or digits allows advancement in levels of five in a modulo-2r manner. The embodiments described so far relate to interpolation between scan signal values along a horizontal scan line in a digital television system. The same interpolation methods can also be used in the vertical direction with adjacent scan signal values in successive lines to interpolate between signals with different line scan speeds or in the time between scan signals at the same location in successive frames for the interpolation between signals with different frame rate. 1. A television signal sampling system with a source of television signals to be sampled, with a clock signal generator for generating clock signals, with a sampling frequency of 13.5 MHz ± nx 2.25 MHz, where n = 0.1.2, ..., with a sampling generator , which is connected to the clock signal generator and the source of television signals and supplies samples of the television signals at this frequency, characterized in that with the sample generator (12) a sample value selection circuit (16, 18, 150, 704) for selecting a fixed number of Samples of active, image-forming parts of a line interval of the television signal to be processed are coupled, the number of a plurality of powers corresponding to the number 2. 2. TV signal sampling system according to claim 1, characterized in that the sample value selection circuit (16, 18, 150, 704) selects a number of samples which corresponds to a plurality of 16. 3. A television signal sampling system according to claim 1 or 2, characterized in that the sample selection circuit (16, 18, 150, 704) selects a number of samples which has a factor which is an even number close to the number 44. 4. TV signal scanning system according to claim 1, characterized in that the sample value selection circuit (16,18,150, 704) selects 704 values from the active part of the line interval having image signals with a sampling frequency of 13.5 MHz 5. TV signal scanning system according to one of claims 1 to 4, characterized in that the sample value selection circuit has a controllable gate element (16) 6. TV signal scanning system according to claim 5, characterized in that the sample selection circuit has a sample counter (704) which is connected to the controllable gate element (16). 7. television signal scanning system according to claim 5 or 6, characterized in that the controllable gate element (16) responds to digital query values, excludes a certain number of query values occurring after the beginning of the line synchronization pulse in each line interval and then allows a fixed number of query widths. 8. television signal sampling system according to one of claims 1 to 7, characterized in that the sample value selection circuit is connected to a digital signal processing circuit (20) which digitally processes the selected samples at the sampling rate 9. TV signal scanning system according to one of claims 1 · to 8, characterized in that the sample value selection circuit controls the timing of the selected samples to produce a blanking interval. -14- No. 389609 10. TV signal sampling system according to claim 9, characterized in that the sample value selection circuit has a second counter (150) for producing the blanking intervals. 11. TV signal scanning system according to claim 10, characterized in that the second counter (150) can be activated by the line synchronization pulse in each line interval. 12. TV receiver for digital television signals with a frequency of 13.5 MHz with a system according to one of claims 1 to 11 and a digital signal processing circuit which receives the sampled signals, characterized in that the signal processing circuit brings these signals into a format which is an even number N has active query values representing image signals per line, where N is formed by the product of P times Q and P is a multiple of an even power of the number 2 and Q is an even number on the order of 44, and a digital to analog Signal processing circuit (22) for generating an analog signal for transmitting the processing signals is provided 13. TV receiver for digital television signals with a television signal scanning system according to one of claims 1 to 11, with a source of digital signals sampled at 13.5 MHz, a digital signal processing circuit connected to the source of the digital signals and a digital-to-analog converter Arrangement which is connected to the output of the signal processing circuit for the generation of analog television signals, characterized in that the source of the digital signals supplies an even number N of active samples containing image information per line, where N corresponds to the product of P times Q, where P is a multiple of an integer of 2 and Q is an integer with a value close to 44. 14. TV receiver according to claim 12 or 13, characterized in that P has the value 16. 15. A television receiver according to claim 12, 13 or 14, characterized in that the number N of active samples representing image information is selected for simple transcoding of signals composed according to NTSC or PAL, which signals M times during the active part of each line of the composite Signals are sampled, where M is the product of R times Q and the difference D between P and R is a small integer. 16. Digital color television transmission system, characterized in that for simple uncoding of standard television signals, these are sampled at a sampling rate which is equal to the product of a small integer times the frequency of the color subcarrier of the standard television signal, in order to obtain a sampled television signal This system comprises a sample selection circuit for selecting M samples within the active image information portion of each line of the sampled television signal, where M is the product of an integer R times an integer Q and R is a value close to 16 and Q is close to 44 and has a clock generator for generating a 13.5 MHz clock signal as the strobe signal for the digital transmission system, an even number N of the clock signals occurring during each interval of the M samples, where N is the product of P times Q. and P a multiple of a power of 2 and the difference D zwis Chen P and R is a small integer 17. System according to claim 16, characterized in that M has a value equal to 748. Therefor 9 sheet drawings -15-