ZA9510563B - Data recovery circuit - Google Patents

Data recovery circuit

Info

Publication number
ZA9510563B
ZA9510563B ZA9510563A ZA9510563A ZA9510563B ZA 9510563 B ZA9510563 B ZA 9510563B ZA 9510563 A ZA9510563 A ZA 9510563A ZA 9510563 A ZA9510563 A ZA 9510563A ZA 9510563 B ZA9510563 B ZA 9510563B
Authority
ZA
South Africa
Prior art keywords
data recovery
recovery circuit
circuit
data
recovery
Prior art date
Application number
ZA9510563A
Inventor
Fernando Ortiz Saenz
Jose Luis Merino Gonzalez
Maria Del Mar Gutier Serratosa
Rafel Sanz Gomez
Original Assignee
Alcatel Standard Electrica
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Standard Electrica filed Critical Alcatel Standard Electrica
Publication of ZA9510563B publication Critical patent/ZA9510563B/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
ZA9510563A 1994-12-29 1995-12-12 Data recovery circuit ZA9510563B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES9402671 1994-12-29

Publications (1)

Publication Number Publication Date
ZA9510563B true ZA9510563B (en) 1996-06-19

Family

ID=8288422

Family Applications (1)

Application Number Title Priority Date Filing Date
ZA9510563A ZA9510563B (en) 1994-12-29 1995-12-12 Data recovery circuit

Country Status (2)

Country Link
WO (1) WO1996021296A1 (en)
ZA (1) ZA9510563B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2373419A (en) * 2001-03-16 2002-09-18 Matsushita Comm Ind Uk Ltd Digital data decoders
CN101394703B (en) * 2008-10-17 2013-12-04 范红霞 Time clock recovery system and method
CN108011620B (en) * 2016-10-31 2023-08-08 深圳市研祥智慧科技股份有限公司 Fast clock recovery circuit based on FPGA

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3376385A (en) * 1960-08-25 1968-04-02 Ibm Synchronous transmitter-receiver
US3668315A (en) * 1970-05-15 1972-06-06 Hughes Aircraft Co Receiver timing and synchronization system
US3983498A (en) * 1975-11-13 1976-09-28 Motorola, Inc. Digital phase lock loop

Also Published As

Publication number Publication date
WO1996021296A1 (en) 1996-07-11

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