ZA865726B - Clock signal selection and security arrangements - Google Patents
Clock signal selection and security arrangementsInfo
- Publication number
- ZA865726B ZA865726B ZA865726A ZA865726A ZA865726B ZA 865726 B ZA865726 B ZA 865726B ZA 865726 A ZA865726 A ZA 865726A ZA 865726 A ZA865726 A ZA 865726A ZA 865726 B ZA865726 B ZA 865726B
- Authority
- ZA
- South Africa
- Prior art keywords
- clock signal
- signal selection
- security arrangements
- arrangements
- security
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08520035A GB2178926A (en) | 1985-08-09 | 1985-08-09 | Clock signal selection and security arrangements |
Publications (1)
Publication Number | Publication Date |
---|---|
ZA865726B true ZA865726B (en) | 1988-11-30 |
Family
ID=10583551
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ZA865726A ZA865726B (en) | 1985-08-09 | 1986-07-31 | Clock signal selection and security arrangements |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0211674A3 (de) |
JP (1) | JPS62168438A (de) |
FI (1) | FI863224A (de) |
GB (1) | GB2178926A (de) |
ZA (1) | ZA865726B (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6775344B1 (en) | 1999-04-02 | 2004-08-10 | Storage Technology Corporation | Dropout resistant phase-locked loop |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2080251A5 (de) * | 1970-02-27 | 1971-11-12 | Lannionnais Electronique | |
IT1051350B (it) * | 1975-12-09 | 1981-04-21 | Cselt Centro Studi Lab Telecom | Sistema di temporizzazione tripli to per impianti duplicati conte nenti circuiti logici |
US4322580A (en) * | 1980-09-02 | 1982-03-30 | Gte Automatic Electric Labs Inc. | Clock selection circuit |
FR2577087B1 (fr) * | 1985-02-07 | 1987-03-06 | Thomson Csf Mat Tel | Dispositif de distribution d'horloge tripliquee, chaque signal d'horloge comportant un signal de synchronisation |
-
1985
- 1985-08-09 GB GB08520035A patent/GB2178926A/en not_active Withdrawn
-
1986
- 1986-07-31 ZA ZA865726A patent/ZA865726B/xx unknown
- 1986-08-06 FI FI863224A patent/FI863224A/fi not_active IP Right Cessation
- 1986-08-08 JP JP61186695A patent/JPS62168438A/ja active Pending
- 1986-08-08 EP EP86306167A patent/EP0211674A3/de not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP0211674A2 (de) | 1987-02-25 |
FI863224A (fi) | 1987-02-10 |
EP0211674A3 (de) | 1989-01-18 |
GB2178926A (en) | 1987-02-18 |
GB8520035D0 (en) | 1985-09-18 |
JPS62168438A (ja) | 1987-07-24 |
FI863224A0 (fi) | 1986-08-06 |
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