YU293182A - Circuit arrangement for matching input signal to a logical level - Google Patents

Circuit arrangement for matching input signal to a logical level

Info

Publication number
YU293182A
YU293182A YU293182A YU293182A YU293182A YU 293182 A YU293182 A YU 293182A YU 293182 A YU293182 A YU 293182A YU 293182 A YU293182 A YU 293182A YU 293182 A YU293182 A YU 293182A
Authority
YU
Yugoslavia
Prior art keywords
input signal
circuit arrangement
logical level
matching input
matching
Prior art date
Application number
YU293182A
Other languages
English (en)
Inventor
J Kojic
Original Assignee
Iskra Sozd Elektro Indus
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Iskra Sozd Elektro Indus filed Critical Iskra Sozd Elektro Indus
Priority to YU293182A priority Critical patent/YU293182A/xx
Priority to DE19833347484 priority patent/DE3347484A1/de
Priority to CH697283A priority patent/CH663302A5/de
Publication of YU293182A publication Critical patent/YU293182A/xx

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Manipulation Of Pulses (AREA)
YU293182A 1982-12-31 1982-12-31 Circuit arrangement for matching input signal to a logical level YU293182A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
YU293182A YU293182A (en) 1982-12-31 1982-12-31 Circuit arrangement for matching input signal to a logical level
DE19833347484 DE3347484A1 (de) 1982-12-31 1983-12-29 Schaltungsanordnung zum anpassen von eingangssignalen an einen logischen signalpegel
CH697283A CH663302A5 (de) 1982-12-31 1983-12-29 Schaltung zum anpassen von eingangssignalen an einen logischen signalpegel.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
YU293182A YU293182A (en) 1982-12-31 1982-12-31 Circuit arrangement for matching input signal to a logical level

Publications (1)

Publication Number Publication Date
YU293182A true YU293182A (en) 1985-03-20

Family

ID=25559029

Family Applications (1)

Application Number Title Priority Date Filing Date
YU293182A YU293182A (en) 1982-12-31 1982-12-31 Circuit arrangement for matching input signal to a logical level

Country Status (3)

Country Link
CH (1) CH663302A5 (fr)
DE (1) DE3347484A1 (fr)
YU (1) YU293182A (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19724451C1 (de) * 1997-06-10 1998-12-03 Siemens Ag Schaltungsanordnung zum Erzeugen digitaler Signale

Also Published As

Publication number Publication date
CH663302A5 (de) 1987-11-30
DE3347484C2 (fr) 1987-07-23
DE3347484A1 (de) 1984-07-05

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