WO2026075813A1 - Power delivery circuit with damping circuit for plasma processing assemblies - Google Patents

Abstract

Methods and apparatus for delivering power using a power delivery circuit during plasma processing. One example power delivery circuit generally includes (i) one or more first capacitive elements coupled to a first node that is configured to be coupled to a pulsed voltage (PV) waveform generator configured to deliver a non- sinusoidal PV waveform to at least one of an electrode via a first output or a plate via a second output; (ii) a bias compensation circuit coupled to a second node that is configured to be coupled to a direct current (DC) power supply; and (iii) a damping circuit coupled to the first node, wherein the damping circuit includes one or more resistive elements. The one or more resistive elements are generally implemented by at least one resistive element with a resistance between 0.1 ohms and 100 ohms.

Description

PATENT

Attorney Docket No.: 44025357WO01

POWER DELIVERY CIRCUIT WITH DAMPING CIRCUIT FOR PLASMA PROCESSING ASSEMBLIES

BACKGROUND

Field

[0001] Certain aspects described herein generally relate to apparatus and methods used in semiconductor device fabrication. More specifically, aspects of the present disclosure relate to a plasma processing assembly used to plasma process a semiconductor structure and methods of using the same.

Description of the Related Art

[0002] Reliably producing high aspect ratio features is one of the key technology challenges for the next generation of very large-scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. One method of forming high aspect ratio features uses a plasma assisted etching process, such as a reactive ion etch (RIE) plasma process, to form high aspect ratio openings in a material layer, such as a dielectric layer, of a substrate. In a typical RIE plasma process, a plasma is formed in an RIE processing chamber and ions from the plasma are accelerated towards a surface of a substrate to form openings in a material layer disposed beneath a mask layer formed on the surface of the substrate.

[0003] A typical RIE plasma processing chamber includes a radio frequency (RF) bias generator, which supplies an RF voltage to a “power electrode” (e.g., a biasing electrode), such as a metal baseplate embedded into an “electrostatic chuck” (ESC) assembly, more commonly referred to as the “cathode.” The power electrode is capacitively coupled to the plasma of a processing system through a thick layer of dielectric material (e.g., ceramic material), which is a part of the ESC assembly. The application of RF voltage to the power electrode causes an electron-repelling plasma sheath (also referred to as the “cathode sheath”) to form over a processing surface of a substrate that is positioned on a substrate supporting surface of the ESC assembly during processing. The non-linear, diode-like nature of the plasma sheath results in rectification of the applied RF field, such that a direct current (DC) voltage drop, or “self-bias,” appears between the substrate and the plasma, making the substrate PATENT

Attorney Docket No.: 44025357WO01 potential negative with respect to the plasma potential. This voltage drop determines the average energy of the plasma ions accelerated towards the substrate, and thus etch anisotropy. More specifically, ion directionality, the feature profile, and etch selectivity to the mask and the stop-layer are controlled by the Ion Energy Distribution Function (IEDF). In plasmas with RF bias, the IEDF typically has two peaks, one at a low energy and one at a high energy, and some ion population in between. The presence of the ion population in-between the two peaks of the IEDF is reflective of the fact that the voltage drop between the substrate and the plasma oscillates at the RF bias frequency. When a lower frequency, e.g., 2 megahertz (MHz), RF bias generator is used to achieve higher self-bias voltages, the difference in energy between these two peaks can be significant; and because the etch profile due to the ions at low energy peak is more isotropic, this could potentially lead to bowing of the etched feature walls. Compared to the high-energy ions, the low-energy ions are less effective at reaching the comers at the bottom of the etched feature (e.g., due to the charging effect) but cause less sputtering of the mask material. This is important in high aspect ratio etch applications, such as hard mask opening or dielectric mold etch. As feature sizes continue to diminish and the aspect ratio increases, while feature profile control requirements become more stringent, it becomes more desirable to have a well-controlled IEDF at the substrate surface during processing.

[0004] A pulsed voltage waveform generator may be used to create a pulsed voltage waveform at an electrode (e.g., mesh electrode) embedded in the electrostatic chuck (ESC) assembly in a semiconductor plasma chamber in order to maintain a particular substrate voltage waveform, and thus control the sheath voltage and the IEDF at the substrate during plasma processing. A difficulty in controlling the produced waveform may arise from real-time changes in the load, such as drifts in the plasma density, chamber walls conditions, substrate temperature, degree, and state of chemical dissociation, in the case of a plasma chamber used as a load. It has been found that the generated pulsed voltage (PV) waveforms provided to one or more electrodes within a process chamber include ringing and waveform distortion which can affect the process results and/or repeatability of the process results. PATENT

Attorney Docket No.: 44025357WO01

[0005] Accordingly, there is a need in the art for novel apparatus and biasing methods that solves the problems described above.

SUMMARY

[0006] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.

[0007] Certain aspects provided herein generally include apparatus, plasma processing assemblies, and methods for plasma processing of a substrate in a plasma processing chamber.

[0008] Certain aspects of the present disclosure provide a power delivery circuit. The power delivery circuit generally includes (/) one or more first capacitive elements coupled to a first node that is configured to be coupled to a pulsed voltage (PV) waveform generator configured to deliver a non-sinusoidal PV waveform to at least one of an electrode via a first output or a plate via a second output; (//) a bias compensation circuit coupled to a second node that is configured to be coupled to a direct current (DC) power supply; and (Hi) a damping circuit coupled to the first node, wherein the damping circuit includes one or more first resistive elements.

[0009] Certain aspects of the present disclosure provide a plasma processing assembly. The plasma processing assembly generally includes a pulsed voltage (PV) waveform generator configured to deliver PV to at least one of an electrode via a first output or a plate via a second output; one or more first capacitive elements coupled to the PV waveform generator; a direct current (DC) power supply; a bias compensation circuit coupled to the DC power supply; and a damping circuit coupled to the PV waveform generator, wherein the damping circuit includes one or more first resistive elements. PATENT

Attorney Docket No.: 44025357WO01

[0010] Certain aspects of the present disclosure are directed to a method of plasma etching. The method generally includes (/) delivering, using a pulsed voltage (PV) waveform generator, a pulsed voltage waveform to at least one of an electrode via a first output or a plate via a second output, wherein the PV waveform generator is coupled to one or more first capacitive elements; (//) providing, using a direct current (DC) power supply, a chucking voltage to the electrode via the first output; and (Hi) damping, using a damping circuit coupled to the PV waveform generator, the pulsed voltage waveform, wherein the damping circuit includes one or more resistive elements.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective aspects.

[0012] Figure 1 is a schematic, cross-sectional view of a plasma processing assembly, in which aspects of the present disclosure may be practiced.

[0013] Figure 2 illustrates a graph of two separate asymmetric voltage waveforms that are established on a substrate due to a voltage waveform applied to an electrode of a processing chamber, in accordance with certain aspects of the present disclosure.

[0014] Figures 3A-3I are block diagrams of example power delivery circuits that may be included in the plasma processing assembly of Figure 1 , in accordance with certain aspects of the present disclosure.

[0015] Figure 4 is a schematic diagram of an example power delivery circuit that may be included in the plasma processing assembly of Figure 1 , in accordance with certain aspects of the present disclosure. PATENT

Attorney Docket No.: 44025357WO01

[0016] Figures 5A-5C illustrate graphs of example PV waveforms, in accordance with certain aspects of the present disclosure.

[0017] Figure 6 is a flow diagram illustrating example operations for delivering power to a plasma processing assembly using a power delivery circuit, in accordance with certain aspects of the present disclosure.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.

DETAILED DESCRIPTION

[0019] Certain aspects described herein generally relate to apparatus and methods for semiconductor device fabrication using a plasma processing assembly. More specifically, aspects provided herein generally include a power delivery circuit with a damping circuit for use in a plasma processing assembly. The damping circuit may be positioned in one or more different locations within the power delivery circuit. Specifically, the damping circuit may be used in conjunction with a pulsed voltage (PV) waveform generator, a high voltage direct current (DC) supply, and/or a radio frequency (RF) generator included in the plasma processing assembly to route PV from the waveform generator, DC bias from the high voltage DC supply, and/or RF signals from the RF generator to a processing chamber of the plasma processing assembly. The damping circuit may be configured to eliminate (or at least reduce) PV waveform ringing, PV waveform distortion, and/or PV waveform overshoot commonly found in PV waveforms provided in some PV waveform delivery circuits during plasma processing. In some cases, the damping circuit may be implemented using one or more damping resistive elements, whereas in other cases, the damping circuit may be implemented using one or more damping resistive elements coupled in parallel with one or more inductive elements. In certain aspects, the damping circuit (and the one or more included resistive elements) may be coupled in series or in parallel with the PV waveform generator. In some cases, the one or more damping resistive elements may be implemented with resistors having resistances between 0.1 ohms and 1 ,100 PATENT

Attorney Docket No.: 44025357WO01 ohms or between 2.2 ohms and 1 , 100 ohms. For example, the one or more damping resistive elements may be implemented by a 5-ohm resistor.

[0020] The power delivery circuit may be implemented in or as a hybrid junction box that is configured to deliver a PV waveform (using the PV waveform generator) to one or both of an electrostatic chucking electrode (e.g., mesh) and a plate (e.g., an RF plate) that are both disposed in a substrate support within the processing chamber of the plasma processing assembly. The power delivery circuit may be configured to receive and then provide a PV waveform (e.g., a 100 kilohertz (kHz) to 2000 kHz PV waveform) to the electrostatic chucking electrode and also receive and provide an RF waveform (e.g., a >2 megahertz (MHz) waveform, such as a 13.56 MHz RF waveform) to an RF plate disposed within the processing chamber.

Plasma Processing Assembly Examples

[0021] Figure 1 is a schematic representation of an example plasma processing assembly 10, in which aspects of the present disclosure may be practiced. The plasma processing assembly 10 may be configured for plasma-assisted etching processes, such as a reactive ion etch (RIE) plasma processing. The plasma processing assembly 10 can also be configured and used for other plasma-assisted processes, such as plasma-enhanced deposition processes (for example, plasma- enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processing, plasma-based ion implant processing, or plasma doping (PLAD) processing. In certain aspects, and as shown in Figure 1 , the plasma processing assembly 10 may be configured to form a capacitively-coupled-plasma (CCP) source. In other aspects, a plasma may alternatively be generated by an inductively coupled plasma (ICP) source disposed over a processing region of the plasma processing assembly 10.

[0022] The plasma processing assembly 10 includes a processing chamber 100, a substrate support assembly 136, a radio frequency (RF) generator 171 , an RF match 172 (e.g., RF impedance matching network), a high voltage direct current (DC) supply 173, a pulsed voltage (PV) waveform generator 175, a power delivery circuit 180, and PATENT

Attorney Docket No.: 44025357WO01 a gas delivery system 184. The power delivery circuit 180 may be implemented in, for example, a junction box, and may include a damping circuit 182. The processing chamber 100 may include a chamber lid 123, one or more sidewalls, and a chamber base that are configured to withstand the pressures and energy applied to them while a plasma 101 is generated within a vacuum environment maintained in a processing volume 129 of the processing chamber 100 during processing.

[0023] The gas delivery system 184, which may be coupled to the processing volume 129 of the processing chamber 100, may be configured to deliver at least one processing gas from at least one processing gas source 119 to the processing volume 129 of the processing chamber 100. The gas delivery system 184 includes the processing gas source 119 and one or more gas inlets 128 positioned through the chamber lid 123. The gas inlets 128 may be configured to deliver one or more processing gases to the processing volume 129 of the processing chamber 100.

[0024] The chamber lid 123 and the substrate support assembly 136 may be positioned in the processing volume 129 of the processing chamber 100. In certain aspects, the chamber lid 123 is grounded and thus acts as an upper electrode during plasma processing (e.g., to provide a capacitively-coupled-plasma (CCP) source). In certain aspects, the RF generator 171 may be electrically coupled to a first lower electrode, such as an RF baseplate 137. The RF generator 171 may be configured to deliver an RF signal to ignite and maintain the plasma 101 between the upper and lower electrodes. In one example, the RF generator 171 may deliver an RF source power to the RF baseplate 137 within the substrate support assembly 136 (e.g., a cathode assembly) for plasma production. However, in some alternative configurations, the RF generator 171 can be electrically coupled to an upper electrode (e.g., in the chamber lid 123). A center frequency of the RF source power can be from 13.56 megahertz (MHz) to very high frequency band such as 40 MHz, 60 MHz, 120 MHz or 162 MHz. The RF source power can be operated in a continuous mode or a pulsed mode. A pulsing frequency of the RF power can be from 100 to 10 kilohertz (kHz), and duty cycles are ranging from 5% to 95%. The RF generator 171 has a frequency tuning capability and can adjust its RF power frequency within e.g., ±5% or PATENT

Attorney Docket No.: 44025357WO01

±10%. In certain aspects, the RF generator 171 switches the RF power frequency at a predefined speed (e.g., two nanoseconds, fifty nanoseconds, etc.).

[0025] The RF generator 171 may be coupled to the substrate support assembly 136 through the power delivery circuit 180. The RF generator 171 may be configured to deliver an RF signal to the processing volume 129 of the processing chamber 100. The RF generator 171 may be electrically coupled to the RF match 172 disposed between the RF generator 171 and the processing volume 129 of the processing chamber 100. For example, the RF match 172 may be an electrical circuit used between the RF generator 171 and a plasma reactor (e.g., the processing volume 129 of the processing chamber 100) to optimize power delivery efficiency. The RF match 172 may include one or more RF filters designed to only allow powers in a selected frequency range, and to isolate RF power supplies from each other. In some cases, a bandwidth of an RF filter may be larger than a frequency tuning range of the RF generator 171.

[0026] During the plasma processing, the RF generator 171 delivers an RF signal to the RF baseplate 137 of the substrate support assembly 136 via the RF match 172. For example, the RF signal is applied to a load (e.g., gas) in the processing volume 129 of the processing chamber 100. If an impedance of the load is not properly matched to an impedance of a source (e.g., the RF generator 171 ), a portion of a waveform can reflect back in an opposite direction. Accordingly, to prevent a substantial portion of the waveform from being reflected, it may be useful to find a match impedance (e.g., a matching point) by adjusting one or more components of the RF match 172 as the source and load impedances change. The RF match 172 may be electrically coupled to the RF generator 171 , the substrate support assembly 136, and the PV waveform generator 175. The RF match 172 may be configured to receive a synchronization signal from either or both of the RF generator 171 and the PV waveform generator 175.

[0027] The substrate support assembly 136 may be coupled to the high voltage DC supply 173 that supplies a chucking voltage thereto. The high voltage DC supply 173 may be coupled to the substrate support assembly 136 through the power delivery circuit 180. The power delivery circuit 180 may be configured to electrically isolate the PATENT

Attorney Docket No.: 44025357WO01 high voltage DC supply 173 during plasma processing. In one configuration, a static DC voltage is between about -5000V and about +5000V and is delivered using an electrical conductor (such as a coaxial power delivery line). The power delivery circuit 180 may include multiple filtering components or a single common filter.

[0028] The PV waveform generator 175 may be coupled to the substrate support assembly 136 through the power delivery circuit 180. The PV waveform generator 175 may be configured to supply a PV to an electrode 138 within the substrate support assembly 136 to bias a substrate (not shown) disposed on a surface 139 of the substrate support assembly 136. The PV waveform generator 175 may also be coupled to the RF baseplate 137 or a second electrode disposed within the substrate support assembly 136, such as an electrode 138 (e.g., a chucking electrode), through the power delivery circuit 180. The power delivery circuit 180 may be configured to electrically isolate the PV waveform generator 175 from at least the RF signal provided by the RF generator 171 during plasma processing. The RF generator 171 and the PV waveform generator 175 may each be directly coupled to a system controller 126. The system controller 126 may synchronize the respective generated RF signal and PV waveform.

[0029] In some cases, voltage and current sensors can be placed at an input and/or output of the RF match 172 to measure impedance and other parameters. These sensors can be synchronized using an external transistor-transistor logic (TTL) synchronization signal from an advanced waveform generator and/or RF generators or using measured voltage and current data to determine timing internally. For example, an output sensor 117 may be configured to measure the impedance of the processing chamber 100, and other characteristics such as the voltage, current, harmonics, phase, and/or the like. An input sensor 116 is configured to measure the impedance of the RF generator 171 and other characteristics such as the voltage, current, harmonics, phase, and/or the like. Based on either of the synchronization signals or the characteristics of the processing chamber 100, the RF match 172 is able to capture fast impedance changes and optimize impedance matching.

[0030] The PV waveform generator 175 may be used to supply a PV waveform and/or a tailored voltage waveform, which is a sum of harmonic frequencies PATENT

Attorney Docket No.: 44025357WO01 associated with the waveform. The PV waveform generator 175 may output a synchronization TTL signal to the RF match 172. The voltage waveform may be coupled to the electrode 138 through the power delivery circuit 180. Typically, the electrode 138 may be formed of one or more electrically conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof. The high voltage DC supply 173 may be applied to chuck a wafer during a process for a thermal control. In some cases, there can be a third electrode at an edge of the cathode assembly for edge uniformity control.

[0031] In certain aspects, the plasma processing assembly 10 may further include one or more electromagnetic coils 190. The one or more electromagnetic coils 190 may be disposed over the processing volume 129 of the plasma processing assembly 10 (e.g., to provide an inductively coupled plasma (ICP) source). The plasma processing assembly 10 may include an RF generator 194 and an RF match 192 (e.g., RF impedance matching network). The RF generator 194 may be similar to the RF generator 171 , and the RF match 192 may be similar to the RF match 172. The RF generator 194 may be configured to deliver an RF signal to the one or more electromagnetic coils 190 to control (or assist in controlling) the plasma 101 (e.g., to adjust ion flux and/or ion energy) during plasma processing.

[0032] The system controller 126 may include a programmable central processing unit (CPU) and/or one or more processors which are operable with a memory (e.g., non-volatile memory). The CPU may be one of any form of general purpose computer processor used in an industrial setting, such as a programmable logic controller (PLC), for controlling various components and sub-processors of the processing system. The memory, which may be coupled to the CPU, is non-transitory and is typically one or more of readily available memories such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of digital storage, local or remote. The memory may store instructions that when executed by the CPU and/or the one or more processors included in the system controller 126 perform processes, such as the operations 600 described below, in the processing chamber 100.

[0033] Typically, the memory is in the form of a non-transitory computer-readable storage media containing instructions (e.g., non-volatile memory), which when PATENT

Attorney Docket No.: 44025357WO01 executed by the CPU, facilitates the operation of the processing chamber 100. The instructions in the memory are in the form of a program product such as a program that implements the methods of the present disclosure. The program code may conform to any one of a number of different programming languages. In one example, the disclosure may be implemented as a program product stored on computer- readable storage media for use with a computer system. The program(s) of the program product may define functions of the aspects (including the operations described herein).

Voltage Waveform Examples

[0034] Figure 2 illustrates a graph 200 of two separate non-sinusoidal voltage waveforms established at a substrate disposed on the surface 139 of the substrate support assembly 136 (illustrated in Figure 1 ) of the processing chamber 100 due to the delivery of voltage waveforms to the electrode 138 of the processing chamber 100. It is to be understood that the two waveforms in Figure 2 are merely example waveforms that have any shape, including, for example, bipolar (e.g., having positive and negative peaks or swings), positive unipolar (e.g., having only positive peaks or swings), or negative unipolar (e.g., having only negative peaks or swings). A first waveform (e.g., waveform 225) is an example of a non-compensated voltage waveform established at the substrate during the plasma processing. A second waveform (e.g., waveform 226) is an example of a compensated voltage waveform established at the substrate by applying a negative slope waveform to the electrode 138 of the processing chamber 100 during an “ion current stage” portion of the voltage waveform cycle by use of a current source. The compensated voltage waveform may alternatively be established by applying a negative voltage ramp during the ion current stage of the voltage waveform generated by the RF generator 171 , the RF generator 194, and/or the PV waveform generator 175. The voltage waveform cycle of the waveforms 225 and 226 each have a period T_P, which may be, for example, between 2 microseconds (ps) and 10 ps, such as 2.5 ps. The ion current stage of the voltage waveform cycle may take up between about 50% and about 95% of the period T_P, such as from about 80% to about 90% of the period T_P. PATENT

Attorney Docket No.: 44025357WO01

[0035] The waveforms 225 and 226 include two main stages: an ion current stage and a sheath collapse stage. Both portions (e.g., the ion current stage and the sheath collapse stage) of the waveforms 225 and 226, can be alternately and/or separately established at the substrate during the plasma processing. At a beginning of the ion current stage, a drop in the voltage at the substrate is created, due to the delivery of a negative portion of the voltage waveform (e.g., the ion current portion) provided to the electrode 138 by the RF generator 171 , the RF generator 194, and/or the PV waveform generator 175, which may create a high voltage sheath above the substrate. The high voltage sheath allows the plasma generated positive ions to be accelerated towards the biased substrate during the ion current stage, and thus, for reactive ion etching (RIE) processes, controls the amount and characteristics of the etching process that occurs on the surface of the substrate during the plasma processing. The sheath collapse stage includes a positive voltage swing 228 (e.g., as a result of the positive wafer voltage), and the ion current stage includes a negative voltage swing (e.g., as a result of the positive wafer voltage), as illustrated in Figure 2.

[0036] In certain aspects, it is desirable for the ion current stage to include a region of the voltage waveform that achieves the voltage at the substrate that is stable or minimally varying throughout the stage, as illustrated in Figure 2 by the waveform 226. One will note that significant variations in the voltage established at the substrate during the ion current stage, such as shown by the positive slope in the waveform 225, will undesirably cause a variation in the ion energy distribution (IED) and thus cause undesirable characteristics of the etched features to be formed in the substrate during the RIE process. Plasma sheath impedance varies with supplied voltage waveform voltages. The RF match 172 may use either or both of the synchronization signals and/or use its internal sensors to sample impedances in different processing phases. In some cases, a synchronization signal or characteristics determined by an input sensor or an output sensor may be used to trigger the RF match 172 to determine at least two different impendences at different processing stages. Then, the RF match 172 updates its matching point based on the at least two different impedances.

[0037] The waveforms 225 and 226 (and any voltage pulses or pulsed voltage (PV) waveforms described herein) may be considered and/or referred to as asymmetric PATENT

Attorney Docket No.: 44025357WO01 waveforms because the ion current stage of the waveforms 225 and 226 is different in time (e.g., has a different length in time or a different duration) than the sheath collapse stage. For example, and as illustrated in Figure 2, the ion current stage of each of the waveforms 225 and 226 may be longer in time than the sheath collapse stage. In addition, and in some cases, the waveforms 225 and 226 (and any voltage or PV waveforms described herein) may be considered and/or referred to as non-sinusoidal waveforms (e.g., waveforms that do not follow the shape of a sine wave).

Power Delivery Circuit Examples

[0038] Figures 3A-3I are block diagrams of example power delivery assemblies 300A, 300B, 300C, 300D, 300E, 300F, 300G, 300H, and 3001 that may be included in the plasma processing assembly 10 of Figure 1 , in accordance with certain aspects of the present disclosure. The power delivery assembly 300A may include a power delivery circuit 180A (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and the damping circuit 182 (not shown in Figure 3A) that may be disposed at node D1 or at node D2. The power delivery assembly 300A may also include the radio frequency (RF) generator 171 , the RF match 172, the high voltage direct current (DC) supply 173, and the pulsed voltage (PV) waveform generator 175. In certain aspects, the location of the damping circuit 182 may be optimized based on the circuit design and configuration as well as load characteristics. In some cases, the damping circuit 182 (and any included resistive element(s)) may be placed close to the PV waveform generator 175. The damping circuit 182 may also be optimized to minimize power dissipation in the power delivery assembly 300A.

[0039] In certain aspects, the damping circuit 182 may be implemented with one or more damping resistive elements, whereas in other aspects, the damping circuit 182 may be implemented with one or more damping resistive elements coupled in series and/or in parallel with one or more inductive elements. The one or more damping resistive elements may be implemented by one or more resistors, each with a resistance between, for example, 0 ohms and 1 ,100 ohms. In some cases, the one or more damping resistive elements may be implemented by one or more resistors each with a resistance between 0 ohms and 100 ohms. For example, the one or more damping resistive elements may be implemented by a singular 5-ohm damping PATENT

Attorney Docket No.: 44025357WO01 resistor. The damping circuit 182 may be configured to eliminate (or at least reduce) PV waveform ringing, PV waveform distortion, and/or PV waveform overshoot in PV provided by the PV waveform generator 175 during plasma processing.

[0040] The power delivery circuit 180A may also include an output 210 (e.g., a pulsed voltage technology (PVT), labeled “DC”), an output 220 (e.g., an RF output labeled “RF”), a filter assembly 230 (labeled “RF FILTER 1”), a filter assembly 240 (labeled “RF FILTER 2”), one or more capacitive elements 250 (labeled “BLOCKING CAP 1”), one or more capacitive elements 260 (labeled “BLOCKING CAP 2”), a bias compensation circuit 270 (e.g., which may be implemented in a bias compensation module, labeled “BCM”), and a filter assembly 280 (labeled “PVT FILTER”). The output 210 may be coupled to an electrode (e.g., the electrode 138 in Figure 1 ), such that the PVT output (e.g., from the PV waveform generator 175) may be provided to the electrode. The second output 220 may be coupled to a plate (e.g., the RF plate 137 in Figure 1 ), such that RF power (e.g., from the RF generator 171 ) may be provided to the plate. As illustrated in the configuration of the power delivery assembly 300A, the output 210 may be coupled to the filter assembly 230 and the one or more capacitive elements 260, and the second output 220 may be coupled to the filter assembly 240 and the filter assembly 280. The one or more capacitive elements 260 may be coupled between the filter assembly 230 and the filter assembly 240. The bias compensation circuit 270 may be coupled between the filter assembly 230 and the high voltage DC supply 173, and the one or more capacitive elements 250 may be coupled between the filter assembly 230, the bias compensation circuit 270, and the PV waveform generator 175. The filter assembly 280 may be coupled between the RF match 172 and the second output 220, and the RF match 172 may be coupled to the RF generator 171.

[0041] The filter assemblies 230, 240, and 280 may each be implemented by one or more capacitive elements and/or one or more inductors (e.g., coupled in series and/or in parallel), and the one or more capacitive elements 250 and the one or more capacitive elements 260 may each be implemented by one or more capacitors (e.g., coupled in series and/or in parallel). The bias compensation circuit 270 may be implemented by one or more diodes, one or more resistors, and/or one or more PATENT

Attorney Docket No.: 44025357WO01 capacitors. Example implementations of the filter assemblies 230, 240, and 280, the one or more capacitive elements 250 and 260, and the bias compensation circuit 270.

[0042] In certain aspects, the filter assembly 230 may be configured to filter and (substantially) block RF signals generated by the RF generator 171 , the filter assembly 240 may be configured to filter and (substantially) block RF signals generated by the RF generator 171 to protect the high voltage DC supply 173 and/or the PV waveform generator 175, and the filter assembly 280 may be configured to substantially prevent the current generated by the output of the high voltage DC supply 173 and/or the PV signals generated by the PV waveform generator 175 from damaging the RF generator 171 during plasma processing. In this manner, noise in the RF waveform and/or the PV may be reduced to help ensure clean signals are delivered to the output 210 and/or the output 220. The one or more capacitive elements 250 and the one or more capacitive elements 260 may be configured to allow alternating current (AC) signals to pass through to the output 210 and/or the output 220 while blocking the flow of DC. Specifically, the one or more capacitive elements 250 may be configured to protect the PV waveform generator 175 from the output of the high voltage DC supply 173, which thus drops across the one or more capacitive elements 250 and does not impact the output of the PV waveform generator 175. The one or more capacitive elements 260 may be configured to protect the RF generator 171 from the output of the high voltage DC supply 173, which thus drops across the one or more capacitive elements 260 and does not impact the output of the RF generator 171 . The bias compensation circuit 270 may be configured to be a current suppressing/filtering circuit for the PV from the PV waveform generator 175, such that the PV from the PV waveform generator 175 does not induce current through high voltage DC supply 173. In the configuration of the power delivery assembly 300A, PV may be provided by the PV waveform generator 175 to both the output 210 and the output 220, and the damping circuit 182 may be coupled in series with the PV waveform generator 175.

[0043] As illustrated in Figure 3A, the damping circuit 182 may be disposed at node D1 or at node D2 (or any other location in the power delivery assembly 300A or the power delivery circuit 180A), such that the damping circuit 182 may coupled in series between the PV waveform generator 175 and the one or more capacitive elements PATENT

Attorney Docket No.: 44025357WO01

250 or may be coupled in series between the filter assembly 230, the bias compensating circuit 270, and the one or more capacitive elements 250. The PV waveform generator 175 may be configured to deliver PV to at least one of the output 210 or the output 220, the RF generator 171 may be configured to deliver RF signals to at least one of the output 210 or the output 220, and the high voltage DC supply 173 may be configured to deliver DC bias to the output 210.

[0044] Referring to Figure 3B, the power delivery assembly 300B may include a power delivery circuit 180B (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and may be similar to the power delivery assembly 300A, and may thus include the output 210, the output 220, the filter assembly 230, the filter assembly 240, the one or more capacitive elements 250, the bias compensation circuit 270, the filter assembly 280, the high voltage DC supply 173, the PV waveform generator 175, the RF match 172, and the RF generator 171. The damping circuit 182 (not shown in Figure 3B) may be disposed at node D1 , at node D2, or at node D3 (or any other location in the power delivery assembly 300B or the power delivery circuit 180B). As illustrated in the configuration of the power delivery assembly 300B, the output 210 may be coupled to the filter assembly 230, and the second output 220 may be coupled to the filter assembly 240 and the filter assembly 280. The one or more capacitive elements 250 may be coupled between the filter assembly 230, the filter assembly 240, and the PV waveform generator 175. The bias compensation circuit 270 may be coupled between the filter assembly 230, the one or more capacitive elements 250, and the high voltage DC supply 173. The filter assembly 280 may be coupled between the RF match 172 and the second output 220. In the configuration of the power delivery assembly 300B, PV is provided by the PV waveform generator 175 to both the output 210 and the output 220, and the damping circuit 182 may be coupled in series with the PV waveform generator 175. In some cases, the damping circuit 182 may also be included in the PV waveform generator 175.

[0045] Referring to Figure 3C, the power delivery assembly 300C may include a power delivery circuit 180C (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and may be similar to the power delivery assembly 300A, and may thus include the output 210, the output 220, the filter assembly 230, the one or more PATENT

Attorney Docket No.: 44025357WO01 capacitive elements 250, the one or more capacitive elements 260, the bias compensation circuit 270, the filter assembly 280, the high voltage DC supply 173, the PV waveform generator 175, the RF match 172, and the RF generator 171. The damping circuit 182 (not shown in Figure 3C) may be disposed at node D1 , at node D2, or at node D3 (or any other location in the power delivery assembly 300C or the power delivery circuit 180C). As illustrated in the configuration of the power delivery assembly 300C, the output 210 may be coupled to the filter assembly 230 and the one or more capacitive elements 260, and the second output 220 may be coupled to the one or more capacitive elements 260 and the filter assembly 280. The filter assembly 230 may be coupled between the one or more capacitive elements 250, the bias compensation circuit, and the one or more capacitive elements 260. The bias compensation circuit 270 may be coupled between the filter assembly 230, the one or more capacitive elements 250, and the high voltage DC supply 173. The one or more capacitive elements 250 may be coupled between the filter assembly 230, the bias compensation circuit 270, and the PV waveform generator 175. The filter assembly 280 may be coupled between the RF match 172, the one or more capacitive elements 260, and the second output 220.

[0046] Referring to Figure 3D, the power delivery assembly 300D may include a power delivery circuit 180D (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and may be similar to the power delivery assembly 300A, and may thus include the output 210, the output 220, the filter assembly 230, the filter assembly 240, the one or more capacitive elements 250, the bias compensation circuit 270, the filter assembly 280, the high voltage DC supply 173, the PV waveform generator 175, the RF match 172, and the RF generator 171. The damping circuit 182 (not shown in Figure 3D) may be disposed at node D1 , at node D2, or at node D3 (or any other location in the power delivery assembly 300D or the power delivery circuit 180D). As illustrated in the configuration of the power delivery assembly 300D, the output 210 may be coupled to the filter assembly 230 and the filter assembly 240, and the second output 220 may be coupled to the filter assembly 240 and the filter assembly 280. The filter assembly 230 may be coupled to the bias compensation circuit 270 and the one or more capacitive elements 250. The bias compensation circuit 270 may be coupled between the filter assembly 230, the one or more capacitive elements 250, and the PATENT

Attorney Docket No.: 44025357WO01 high voltage DC supply 173. The one or more capacitive elements 250 may be coupled between the filter assembly 230, the bias compensation circuit 270, and the PV waveform generator 175. The filter assembly 280 may be coupled between the RF match 172 and the second output 220.

[0047] Referring to Figure 3E, the power delivery assembly 300E may include a power delivery circuit 180E (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and may be similar to the power delivery assembly 300A, and may thus include the output 210, the output 220, the filter assembly 230, the filter assembly 240, the one or more capacitive elements 250, the bias compensation circuit 270, the filter assembly 280, the high voltage DC supply 173, the PV waveform generator 175, the RF match 172, and the RF generator 171. The damping circuit 182 (not shown in Figure 3E) may be disposed at node D1 , at node D2, or at node D3 (or any other location in the power delivery assembly 300E or the power delivery circuit 180E). As illustrated in the configuration of the power delivery assembly 300E, the output 210 may be coupled to the filter assembly 230 and the filter assembly 240, and the second output 220 may be coupled to the filter assembly 240 and the filter assembly 280. The filter assembly 230 may be coupled to the bias compensation circuit 270 and the one or more capacitive elements 250. The filter assembly 240 may be coupled to the one or more capacitive elements 250 and the filter assembly 280. The bias compensation circuit 270 may be coupled between the filter assembly 230, the one or more capacitive elements 250, and the high voltage DC supply 173. The one or more capacitive elements 250 may be coupled between the filter assembly 230, the filter assembly 240, the bias compensation circuit 270, and the PV waveform generator 175. The filter assembly 280 may be coupled between the RF match 172 and the second output 220.

[0048] Referring to Figure 3F, the power delivery assembly 300F may include a power delivery circuit 180F (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and may be similar to the power delivery assembly 300A, and may thus include the output 210, the output 220, the filter assembly 230, the filter assembly 240, the one or more capacitive elements 250, the one or more capacitive elements 260, the bias compensation circuit 270, the filter assembly 280, the high voltage DC supply PATENT

Attorney Docket No.: 44025357WO01

173, the PV waveform generator 175, the RF match 172, and the RF generator 171. The damping circuit 182 (not shown in Figure 3F) may be disposed at node D1 (or any other location in the power delivery assembly 300F or the power delivery circuit 180F). As illustrated in the configuration of the power delivery assembly 300F, the output 210 may be coupled to the filter assembly 230, and the second output 220 may be coupled to the one or more capacitive elements 260 and the filter assembly 280. The filter assembly 230 may be coupled to the bias compensation circuit 270 and the one or more capacitive elements 250. The filter assembly 240 may be coupled between the one or more capacitive elements 260, the one or more capacitive elements 250, and the PV waveform generator 175. The bias compensation circuit 270 may be coupled between the filter assembly 230, the one or more capacitive elements 250, and the high voltage DC supply 173. The one or more capacitive elements 250 may be coupled between the filter assembly 230, the filter assembly 240, the bias compensation circuit 270, and the PV waveform generator 175. The filter assembly 280 may be coupled between the RF match 172 and the second output 220.

[0049] Referring to Figure 3G, the power delivery assembly 300G may include a power delivery circuit 180G (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and may be similar to the power delivery assembly 300A, and may thus include the output 210, the output 220, the filter assembly 230, the one or more capacitive elements 250, the bias compensation circuit 270, the filter assembly 280, the high voltage DC supply 173, the PV waveform generator 175, the RF match 172, and the RF generator 171. The damping circuit 182 (not shown in Figure 3G) may be disposed at node D1 (or any other location in the power delivery assembly 300G or the power delivery circuit 180G). As illustrated in the configuration of the power delivery assembly 300F, the output 210 may be coupled to the filter assembly 230, and the second output 220 may be coupled to the filter assembly 280. The filter assembly 230 may be coupled to the bias compensation circuit 270 and the one or more capacitive elements 250. The bias compensation circuit 270 may be coupled between the filter assembly 230, the one or more capacitive elements 250, and the high voltage DC supply 173. The one or more capacitive elements 250 may be coupled between the filter assembly 230, the filter assembly 240, the bias compensation circuit 270, and the PV waveform generator 175. The filter assembly PATENT

Attorney Docket No.: 44025357WO01

280 may be coupled between the RF match 172 and the second output 220. In some cases, and as shown in the configuration of the power delivery assembly 300F, PV is delivered, using the PV waveform generator 175, to the output 210, but not to the output 220. In these cases, the plasma processing assembly that includes the power delivery assembly 300F may utilize an inductively coupled plasma (ICP) source (e.g., using the RF generator 194, the RF match 192, and the electromagnetic coils 190, as described above).

[0050] Referring to Figure 3H, the power delivery assembly 300H may include a power delivery circuit 180H (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and may be similar to the power delivery assembly 300A, and may thus include the output 210, the output 220, the one or more capacitive elements 250, the bias compensation circuit 270, the high voltage DC supply 173, and the PV waveform generator 175. The power delivery circuit 180H may optionally include the one or more capacitive elements 260. The damping circuit 182 (not shown in Figure 3H) may be disposed at node D1 or at node D2 (or any other location in the power delivery assembly 300H or the power delivery circuit 180H). As illustrated in the configuration of the power delivery assembly 300H, the output 210 may be coupled to the bias compensation circuit 270 and the one or more capacitive elements 250, and the second output 220 may be coupled to the one or more capacitive elements 250. In some cases, the one or more capacitive elements 260 may be included and coupled between the one or more capacitive elements 250 and the output 220. The one or more capacitive elements 250 may be coupled between the output 210, the bias compensation circuit 270, and the PV waveform generator 175. The bias compensation circuit 270 may be coupled between the output 210, the one or more capacitive element 250, and the high voltage DC supply 173. In some cases, and as shown in the configuration of the power delivery assembly 300H, the RF generator 171 and the RF match 172 may not be included. In these cases, PV may be delivered, using the PV waveform generator 175, to both the output 210 and the output 220. In addition, in these cases, the plasma processing assembly that includes the power delivery assembly 300H may include the RF generator 194, the RF match 192, and the electromagnetic coils 190 (e.g., and utilize ICP source-based plasma processing, as described above). PATENT

Attorney Docket No.: 44025357WO01

[0051] Referring to Figure 3I, the power delivery assembly 300I may include a power delivery circuit 1801 (e.g., which may implement the power delivery circuit 180 of Figure 1 ) and may be similar to the power delivery assembly 300A, and may include the output 210, the one or more capacitive elements 250, the bias compensation circuit 270, the high voltage DC supply 173, and the PV waveform generator 175. The power delivery circuit 1801 may optionally include a filter assembly 310. The filter assembly 310 may be implemented by one or more capacitive elements and/or one or more inductors (e.g., coupled in series and/or in parallel). The damping circuit 182 (not shown in Figure 3I) may be disposed at node D1 (or any other location in the power delivery assembly 300I or the power delivery circuit 1801). As illustrated in the configuration of the power delivery assembly 300H, the output 210 may be coupled to the bias compensation circuit 270 and the one or more capacitive elements 250. In some cases, the filter assembly 310 may be included and coupled between the one or more capacitive elements 250 and the output 210. The one or more capacitive elements 250 may be coupled to the output 210, the bias compensation circuit 270, and the PV waveform generator 175. The bias compensation circuit 270 may be coupled between the output 210, the one or more capacitive element 250, and the high voltage DC supply 173. In some cases, and as shown in the configuration of the power delivery assembly 300H, the RF generator 171 and the RF match 172 are not included. In these cases, PV may be delivered, using the PV waveform generator 175, to the output 210. In addition, in these cases, a plasma processing assembly that includes the power delivery assembly 300I may include the RF generator 194, the RF match 192, and the electromagnetic coils 190 (e.g., and utilize ICP source-based plasma processing, as described above).

[0052] Figure 4 is a schematic diagram of an example power delivery circuit 400 that may be included in the plasma processing assembly 10 of Figure 1 , in accordance with certain aspects of the present disclosure. The power delivery circuit 400 may be an example circuit implementation of a power delivery assembly, and may include the output 210, the output 220, the filter assembly 230, the filter assembly 240, the one or more capacitive elements 250, the one or more capacitive elements 260, the bias compensation circuit 270, the filter assembly 280, the high voltage DC supply 173, the PV waveform generator 175, the RF match 172, and the RF generator 171. The power PATENT

Attorney Docket No.: 44025357WO01 delivery circuit 400 may also include the system controller 126, a voltage monitor 410, a current monitor 420, and a resistor-capacitor network 430. The damping circuit 182 may be disposed between the filter assembly 230, the bias compensating circuit 270, and the resistor-capacitor network 430. It is to be understood that the implementations of the various blocks of the power delivery assemblies described above in Figure 4 are merely examples, and that each of the blocks of the power delivery assemblies described herein may be implemented in any suitable manner.

[0053] In the power delivery circuit 400, the output 210 may be coupled to the one or more capacitive elements 260 (implemented by a capacitor C6) and the filter assembly 230 (implemented by a capacitor C6 coupled in parallel with an inductor L2). The filter assembly 230 may be coupled to the one or more capacitive elements 250 (implemented by a capacitor C5), which may in turn be coupled to the damping circuit 182 (labeled “R” in Figure 4). The damping circuit 182 may also be coupled to a first terminal of a resistive element R5, and the second terminal of the resistive element R5 may be coupled to a reference potential node 440 (e.g., electrical ground) of the power delivery circuit 400. The damping circuit 182 may also be coupled to the current monitor 420, which may be coupled to the PV waveform generator 175 (labeled “PVT SOURCE” in Figure 4). The one or capacitive elements 260 may be coupled to the filter assembly 240 (which may be implemented by, one or more capacitive elements and/or one or more inductive elements). The output 220 may be coupled to the filter assembly 240 and the filter assembly 280 (implemented by a capacitor C1 coupled in series with an inductor L1 ). The filter assembly 280 may be coupled to the RF match 172 (labeled “MATCH” in Figure 4), and the RF match 172 may be coupled to the RF generator 171 (labeled “RF SOURCE” in Figure 4). The RF generator 171 may also be coupled to the reference potential node 440. The filter assembly 230 may also be coupled to the bias compensation circuit 270 (implemented with a resistor R1 coupled in parallel with a diode D1 , a shunt capacitive element C2 coupled to the reference potential node 440, and a resistive element R2 coupled in series with the high voltage DC supply 173 (labeled “HVM”)) and the resistor-capacitor network 430 (implemented with resistors R3 and R4 and capacitors C3 and C4). Referring to the resistorcapacitor network 430, resistors R3 and R4 may be coupled in series, capacitors C3 and C4 may be coupled in series, and the set of resistors R3 and R4 may be coupled PATENT

Attorney Docket No.: 44025357WO01 in parallel with the set of capacitors C3 and C4. The resistor-capacitor network 430 may be coupled to the voltage monitor 410, and the bias compensation circuit 270 may be coupled to the high voltage DC supply 173.

[0054] The controller 126 may be electrically connected to (e.g., in communication with) the current monitor 420 and the voltage monitor 410, and may monitor the voltage provided by the high voltage DC supply 173 and the PV provided by the PV waveform generator 175 and control (e.g., adjust) the high voltage DC supply 173 and PV waveform generator 175 during plasma processing based on the desired process recipe and/or in response to conditions in the processing chamber of the plasma processing assembly.

[0055] Figures 5A-5C illustrate graphs of example PV waveforms 500A, 500B, and 500C, in accordance with certain aspects of the present disclosure. The PV waveform 500A represents an example PV waveform provided at the DC output (e.g., output 210) and/or the RF output (e.g., output 220) of a power delivery assembly of a plasma processing assembly using a PV waveform generator when the power delivery assembly does not include an RF filter assembly. The PV waveform 500B represents an example PV waveform provided at the DC output and/or the RF output of the power delivery assembly of a plasma processing assembly using a PV waveform generator when a power delivery assembly includes an RF filter assembly (e.g., RF filter assembly 230 and/or 240). As illustrated, the PV waveform 500B may include more PV waveform ringing, PV waveform distortion, and/or PV waveform overshoot compared to the PV waveform 500A as a result of the inclusion of the RF filter assembly (or assemblies).

[0056] Aspects herein may provide a power delivery circuit that incorporates a damping circuit designed to operate alongside a PV waveform generator within a plasma processing assembly. The inclusion of the damping circuit helps reduce PV waveform ringing, distortion, and/or overshoot during plasma processing. The power delivery circuit facilitates the transfer of PV signals from the waveform generator to an electrode or a plate in a processing chamber of the plasma processing assembly, and the inclusion of the damping circuit may also contribute to temperature regulation by dissipating excess energy. In certain aspects, the damping circuit may include one or PATENT

Attorney Docket No.: 44025357WO01 more resistors with values ranging from approximately 0.1 ohms to 1 ,100 ohms. The damping effect created by the one or more resistors is particularly beneficial for stabilizing PV waveforms when the PV waveform generator outputs relatively high voltage PV signals. When lower resistance values (e.g., 5 ohms) are used, the damping circuit minimizes the impact of the resistance of the damping circuit on low- voltage PV signals, thereby maintaining performance across a range of operating conditions. Conversely, higher resistance values (e.g., 100 ohms) further enhance the suppression of PV waveform ringing, distortion, and/or overshoot but may suffer from slightly decreased performance when the PV waveform generator outputs relatively low voltage PV signals. The PV waveform 500C represents an example PV waveform provided at the output 210 and/or the output 220 of the power delivery assembly of a plasma processing assembly using the PV waveform generator 175 when the power delivery assembly includes an RF filter assembly (e.g., RF filter assembly 230 and/or 240) and a damping circuit. As illustrated, the PV waveform ringing, PV waveform distortion, and/or PV waveform overshoot in the PV waveform 500C may be significantly reduced compared to the PV waveform 500B as a result of the inclusion of the damping circuit.

Operations for Delivering Power

[0057] Figure 6 is a flow diagram illustrating example operations 600 for delivering power to a plasma processing assembly (e.g., plasma processing assembly 10) using a power delivery circuit (e.g., power delivery circuit 180, which may be implemented by power delivery circuit 180A-180I), in accordance with certain aspects of the present disclosure. The operations 600 may be performed by control circuitry (e.g., system controller 126) included in the plasma processing system.

[0058] The operations 600 may include, at block 610, delivering, using a pulsed voltage (PV) waveform generator (e.g., a PV waveform generator 175), a pulsed voltage waveform (e.g., waveform 225, 230, 500A, 500B, or 500C) to at least one of an electrode (e.g., electrode 138) via a first output (e.g., output 210, which may be a pulsed voltage technology (PVT) or DC output to the processing chamber 100 of the plasma processing assembly 10) or a plate (e.g., RF baseplate 137) via a second output (e.g., second output 220, which may be a radio frequency (RF) output to the PATENT

Attorney Docket No.: 44025357WO01 processing chamber 100 of the plasma processing assembly 10). The PV waveform generator may be coupled to one or more capacitive elements (e.g., one or more capacitive elements 250 or 260).

[0059] At block 620, the operations 600 may include providing, using a direct current (DC) power supply (e.g., a high voltage direct current (DC) supply 173), a chucking voltage to the electrode via the first output.

[0060] At block 630, the operations 600 may include damping, using a damping circuit (e.g., damping circuit 182) coupled to the PV waveform generator, the pulsed voltage waveform. In some cases, the damping circuit may include one or more resistive elements, whereas in other cases, the damping circuit may include one or more resistive elements coupled in series and/or in parallel with one or more inductive elements. In some cases, the one or more resistive elements may include one or more resistive elements (e.g., coupled in series or in parallel) with a resistance between 0 ohms and 1 ,100 ohms. For example, the one or more resistive elements may include one or more resistive elements with a resistance between 0.1 ohms and 100 ohms or a resistance between 0.1 ohms and 10 ohms, such as a resistance of 5 ohms.

[0061] According to certain aspects, the operations 600 may further include modifying, using a bias compensation circuit (e.g., bias compensation circuit 270) coupled to the DC power supply, the chucking voltage. For example, the bias compensation circuit may be configured to modify the chucking voltage output from the DC power supply to ensure that a relatively consistent chucking voltage may be supplied to the first output.

Additional Considerations

[0062] In the above description, details are set forth by way of example to facilitate an understanding of the disclosed subject matter. It should be apparent to a person of ordinary skill in the field, however, that the disclosed implementations are exemplary and not exhaustive of all possible implementations. Thus, it should be understood that reference to the described examples is not intended to limit the scope of the disclosure. PATENT

Attorney Docket No.: 44025357WO01

Any alterations and further modifications to the described devices, instruments, methods, and any further application of the principles of the present disclosure are fully contemplated as would normally occur to one skilled in the art to which the disclosure relates. In particular, it is fully contemplated that the features, components, and/or steps described with respect to one implementation may be combined with the features, components, and/or steps described with respect to other implementations of the present disclosure. As used herein, the term “about” may refer to a +/-10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.

[0063] As used herein, “a processor,” “at least one processor,” or “one or more processors” generally refers to a single processor configured to perform one or multiple operations or multiple processors configured to collectively perform one or more operations. In the case of multiple processors, performance of the one or more operations could be divided amongst different processors, though one processor may perform multiple operations, and multiple processors could collectively perform a single operation. Similarly, “a memory,” “at least one memory” or “one or more memories” generally refers to a single memory configured to store data and/or instructions, multiple memories configured to collectively store data and/or instructions.

[0064] As used herein, a phrase referring to “at least one of” or “one or more of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0065] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims. PATENT

Attorney Docket No.: 44025357WO01

[0066] The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, then objects A and C may still be considered coupled to one another — even if objects A and C do not directly physically touch each other. For instance, a first object may be coupled to a second object even though the first object is never directly physically in contact with the second object.

[0067] While the foregoing is directed to aspects of the present disclosure, other and further aspects of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

PATENT Attorney Docket No.: 44025357WO01 CLAIMS: What is claimed is:

1 . A power delivery circuit comprising: one or more first capacitive elements coupled to a first node that is configured to be coupled to a pulsed voltage (PV) waveform generator configured to deliver a non-sinusoidal PV waveform to at least one of an electrode via a first output or a plate via a second output; a bias compensation circuit coupled to a second node that is configured to be coupled to a direct current (DC) power supply; and a damping circuit coupled to the first node, wherein the damping circuit includes one or more first resistive elements.

2. The power delivery circuit of claim 1 , wherein the one or more first resistive elements comprise a resistive element with a resistance between 0.1 ohms and 100 ohms.

3. The power delivery circuit of claim 1 , wherein the one or more first resistive elements comprise a resistor with a resistance between 0.1 ohms and 10 ohms.

4. The power delivery circuit of claim 1 , wherein the damping circuit is coupled between the first node and the one or more first capacitive elements.

5. The power delivery circuit of claim 1 , further comprising one or more second capacitive elements coupled between the one or more first capacitive elements and the second output.

6. The power delivery circuit of claim 1 , further comprising one or more second capacitive elements coupled between the one or more first capacitive elements and the second output, wherein the damping circuit is coupled between the one or more first capacitive elements and the one or more second capacitive elements. PATENT

Attorney Docket No.: 44025357WO01

7. The power delivery circuit of claim 1 , wherein the damping circuit further comprises one or more inductive elements coupled in parallel with the one or more first resistive elements.

8 The power delivery circuit of claim 1 , further comprising a filter assembly coupled between the second output, the one or more first capacitive elements, and the bias compensation circuit.

9. The power delivery circuit of claim 1 , further comprising a first filter assembly coupled to a third node configured to be coupled to a radio frequency (RF) generator, wherein the RF generator is configured to deliver RF power to the at least one of the electrode via the first output and the plate via the second output.

10. The power delivery circuit of claim 9, further comprising: a second filter assembly coupled between the first output, the bias compensation circuit, and the one or more first capacitive elements; and one or more second capacitive elements coupled between the second filter assembly and a third filter assembly, the third filter assembly being coupled to the second output and the first filter assembly.

11 . The power delivery circuit of claim 1 , wherein the bias compensation circuit comprises: one or more resistive elements; one or more diodes coupled to the one or more resistive elements; and one or more shunt capacitive elements coupled to the one or more diodes and the one or more resistive elements.

12. A plasma processing assembly comprising: a pulsed voltage (PV) waveform generator configured to deliver PV to at least one of an electrode via a first output or a plate via a second output; one or more first capacitive elements coupled to the PV waveform generator; a direct current (DC) power supply; PATENT

Attorney Docket No.: 44025357WO01 a bias compensation circuit coupled to the DC power supply; and a damping circuit coupled to the PV waveform generator, wherein the damping circuit includes one or more first resistive elements.

13. The plasma processing assembly of claim 12, wherein the one or more first resistive elements comprise a resistive element with a resistance between 0.1 ohms and 10 ohms.

14. The plasma processing assembly of claim 12, wherein the damping circuit is coupled between the PV waveform generator and the one or more first capacitive elements.

15. The plasma processing assembly of claim 12, further comprising one or more second capacitive elements coupled between the one or more first capacitive elements and the second output.

16. The plasma processing assembly of claim 12, further comprising one or more second capacitive elements coupled between the one or more first capacitive elements and the second output, wherein the damping circuit is coupled between the one or more first capacitive elements and the one or more second capacitive elements.

17. The plasma processing assembly of claim 12, wherein the bias compensation circuit comprises: one or more second resistive elements; one or more diodes coupled to the one or more second resistive elements; and one or more shunt capacitive elements coupled to the one or more diodes and the one or more second resistive elements.

18. A method for delivering power in a plasma processing assembly, the method comprising: PATENT

Attorney Docket No.: 44025357WO01 delivering, using a pulsed voltage (PV) waveform generator, a pulsed voltage waveform to at least one of an electrode via a first output or a plate via a second output, wherein the PV waveform generator is coupled to one or more first capacitive elements; providing, using a direct current (DC) power supply, a chucking voltage to the electrode via the first output; and damping, using a damping circuit coupled to the PV waveform generator, the PV waveform, wherein the damping circuit includes one or more resistive elements.

19. The method of claim 18, further comprising modifying, using a bias compensation circuit coupled to the DC power supply, the chucking voltage.

20. The method of claim 18, wherein the one or more resistive elements comprise a resistive element with a resistance between 0.1 ohms and 10 ohms.