WO2026016757A1 - 太阳能电池片、太阳能电池片的制备方法及光伏组件 - Google Patents

太阳能电池片、太阳能电池片的制备方法及光伏组件

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Publication number
WO2026016757A1
WO2026016757A1 PCT/CN2025/103452 CN2025103452W WO2026016757A1 WO 2026016757 A1 WO2026016757 A1 WO 2026016757A1 CN 2025103452 W CN2025103452 W CN 2025103452W WO 2026016757 A1 WO2026016757 A1 WO 2026016757A1
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WIPO (PCT)
Prior art keywords
layer
doped
region
doped layer
solar cell
Prior art date
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Pending
Application number
PCT/CN2025/103452
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English (en)
French (fr)
Inventor
李振国
童洪波
靳玉鹏
陈晨
陈瑶
马娜
陈石
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Longi Green Energy Technology Co Ltd
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Longi Green Energy Technology Co Ltd
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Application filed by Longi Green Energy Technology Co Ltd filed Critical Longi Green Energy Technology Co Ltd
Publication of WO2026016757A1 publication Critical patent/WO2026016757A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/93—Interconnections
    • H10F77/933—Interconnections for devices having potential barriers
    • H10F77/935—Interconnections for devices having potential barriers for photovoltaic devices or modules

Definitions

  • This application relates to the field of photovoltaic technology, specifically to a solar cell, a method for preparing a solar cell, and a photovoltaic module.
  • Solar cells can convert solar energy into electrical energy.
  • Back-contact solar cells a type of solar cell, have their electrodes located on the back of the cell to prevent them from blocking the front, thus improving the photoelectric conversion efficiency.
  • Existing back-contact solar cells typically include a substrate with a front and a back side.
  • the back side has a first region, a second region, and a third region disposed between the first and second regions.
  • a first doped layer is stacked in the first region
  • a second doped layer is stacked in the second region
  • a dielectric layer is stacked in the third region. The dielectric layer blocks the first and second doped layers, preventing leakage current and improving the photoelectric conversion efficiency of the solar cell.
  • This application discloses a solar cell, a method for preparing the solar cell, and a photovoltaic module, to solve or at least partially solve the problem of hot spots easily occurring in back-contact solar cells in the prior art.
  • this application discloses a solar cell, the solar cell comprising: a substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals and a third region located between the first region and the second region; a first doped layer and a second doped layer, the first doped layer being disposed on the surface of the first region or at least partially embedded in the surface of the first region, the second doped layer being disposed on the surface of the second region or at least partially embedded in the surface of the second region, the second doped layer having opposite polarity to the first doped layer; a dielectric layer and a conductive path layer, wherein the dielectric layer and the conductive path layer are sequentially stacked in the third region along a direction away from the substrate, the dielectric layer blocking the first doped layer and the second doped layer, and the conductive path layer connecting a portion of the first doped layer and a portion of the second doped layer.
  • the thickness of the dielectric layer is greater than the thickness of the conductive path layer.
  • the thickness of the conductive path layer is greater than the thickness of the dielectric layer.
  • the base materials of the dielectric layer and the conductive path layer are the same; or, the base materials of the dielectric layer and the conductive path layer are different.
  • the conductive path layer includes a layer doped with one element; and/or, the conductive path layer includes a layer doped with two elements of opposite polarity.
  • the conductive path layer includes a single-doped path layer and a co-doped path layer, wherein the single-doped path layer is stacked on the side of the dielectric layer away from the substrate, and the co-doped path layer is stacked on the side of the single-doped path layer away from the dielectric layer; the single-doped path layer is doped with one element, and the co-doped path layer is doped with two elements of opposite polarity.
  • the single-doped path layer and the co-doped path layer have the same conductivity type.
  • the surface element doping concentration of the conductive path layer is greater than or equal to the surface element doping concentration of the first doped layer; and/or, the surface element doping concentration of the conductive path layer is greater than or equal to the surface element doping concentration of the second doped layer.
  • the thickness of the conductive path layer is d1 , satisfying 10nm ⁇ d1 ⁇ 120nm ; and/or, the element doping concentration of the conductive path layer is greater than 1E18cm ⁇ 3 and less than 5E22cm ⁇ 3 .
  • the elemental doping concentration of the dielectric layer is less than 1E13cm ⁇ 3 ; and/or, along the thickness direction of the solar cell, the thickness of the dielectric layer is d2 , satisfying 20nm ⁇ d2 ⁇ 490nm .
  • the substrate corresponding to the third region has a third doped region, wherein the elemental doping concentration of the third doped region is less than 1E13cm ⁇ 3 .
  • the substrate corresponding to the first region has a first doped region, the elemental doping concentration of the first doped region being greater than 1E13cm ⁇ 3 ; and/or, the substrate corresponding to the second region has a second doped region, the elemental doping concentration of the second doped region being greater than 1E13cm ⁇ 3 .
  • the first doped layer includes a first mono-doped layer and a first co-doped layer.
  • the first mono-doped layer is doped with one element, and the first co-doped layer is doped with two elements of opposite polarity.
  • the first mono-doped layer is stacked on the surface of the first region or at least partially embedded in the surface of the first region.
  • the first co-doped layer is stacked on the side of the first mono-doped layer away from the substrate.
  • the first co-doped layer has an opposite conductivity type to the first mono-doped layer.
  • the solar cell further includes a first electrode coupled to a first region of the substrate.
  • the first co-doped layer is provided with a through-groove.
  • the first electrode is embedded in the through-groove and connected to the first mono-doped layer or the first region of the substrate. There is a gap between the first electrode and the inner wall of the through-groove.
  • the uniformity of element doping concentration in the first single-doped layer is better than the uniformity of element doping concentration in the first co-doped layer.
  • the second doped layer includes a second mono-doped layer and a second co-doped layer.
  • the second mono-doped layer is doped with one element, and the second co-doped layer is doped with two elements of opposite polarity.
  • the second mono-doped layer is stacked on the surface of the second region or at least partially embedded in the surface of the second region, and the second co-doped layer is stacked on the side of the second mono-doped layer away from the substrate.
  • the second co-doped layer has the same conductivity type as the second mono-doped layer.
  • the thickness of the second co-doped layer is greater than the thickness of the first co-doped layer of the first doped layer, and the thickness of the first co-doped layer is greater than or equal to the thickness of the co-doped path layer of the conductive path layer, wherein the first co-doped layer contains two elements with opposite polarities, and the co-doped path layer contains two elements with opposite polarities.
  • the first doped layer has a first concentration gradient co-doped region on the side near the conductive path layer; and/or, the second doped layer has a second concentration gradient co-doped region on the side near the conductive path layer.
  • the width of the first concentration-gradient co-doped region is greater than the width of the second concentration-gradient co-doped region.
  • the conductive path layer has a first depth-gradient co-doped region on the side near the first doped layer, and the conductive path layer has a second depth-gradient co-doped region on the side near the second doped layer.
  • this application also discloses a method for fabricating a solar cell, the method comprising: providing a substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals and a third region located between the first region and the second region; forming a first doped layer on the surface of the first region or within the surface of the first region, and forming a second doped layer on the surface of the second region or within the surface of the second region, the first doped layer and the second doped layer having opposite polarities; and sequentially stacking a dielectric layer and a conductive path layer in the third region along a direction away from the substrate, so as to block the first doped layer and the second doped layer through the dielectric layer, and to connect a portion of the first doped layer and a portion of the second doped layer through the conductive path layer.
  • forming a first doped layer on or within the surface of the first region, and forming a second doped layer on or within the surface of the second region includes: forming a semiconductor layer on the first surface of the substrate; forming a first doped source layer and a second doped source layer at positions on the semiconductor layer corresponding to the first region and the second region, respectively; heating and advancing the first doped source layer and the second doped source layer so that the portion of the semiconductor layer corresponding to the first region forms the first doped layer, and the portion of the semiconductor layer corresponding to the second region forms the second doped layer, wherein the polarities of the first doped layer and the second doped layer are opposite.
  • the step of sequentially stacking the dielectric layer and the conductive path layer in the third region along a direction away from the substrate includes: forming a semiconductor layer on a first surface of the substrate, forming a third doped source layer at a position of the semiconductor layer corresponding to the third region; and heating and advancing the third doped source layer so that the portion of the semiconductor layer corresponding to the third region sequentially forms the stacked dielectric layer and the conductive path layer along a direction away from the substrate.
  • forming a first doped layer on or within the surface of the first region includes: forming a semiconductor layer on a first surface of the substrate, forming a first doped source layer at a position of the semiconductor layer corresponding to the first region; heating and advancing the first doped source layer to form a first mono-doped layer at a portion of the semiconductor layer corresponding to the first region; forming a fourth doped source layer on the first mono-doped layer; heating and advancing the fourth doped source layer to form a first co-doped layer on a side of the first mono-doped layer away from the substrate, wherein the first mono-doped layer and the first co-doped layer constitute the first doped layer; the method further includes: forming a through-groove on the first co-doped layer, embedding a first electrode in the through-groove, and connecting it to the first mono-doped layer or a first region of the substrate, wherein there is a gap between the first electrode and the inner
  • this application also discloses a photovoltaic module comprising the solar cells described in the first aspect.
  • the solar cell includes a substrate having a first surface and a second surface disposed opposite to each other.
  • the first surface includes a first region and a second region spaced apart, and a third region located between the first region and the second region.
  • It also includes a first doped layer and a second doped layer, wherein the first doped layer is disposed on the surface of the first region or at least partially embedded within the surface of the first region, and the second doped layer is disposed on the surface of the second region or at least partially embedded within the surface of the second region, with the second doped layer having the opposite polarity to the first doped layer.
  • the dielectric layer blocks the first doped layer and the second doped layer
  • the conductive path layer connects a portion of the first doped layer and a portion of the second doped layer.
  • the solar cell disclosed in this application includes a substrate.
  • the first surface of the substrate includes a first region and a second region spaced apart, and a third region located between the first region and the second region.
  • a first doped layer is disposed on the surface of the first region or at least partially embedded in the surface of the first region, and a second doped layer is disposed on the surface of the second region or at least partially embedded in the surface of the second region.
  • the first doped layer and the second doped layer have opposite polarities to collect the current generated on the substrate through the first doped layer and the second doped layer.
  • the dielectric layer and the conductive path layer are sequentially stacked in the third region to block the first doped layer and the second doped layer through the dielectric layer.
  • the dielectric layer can also block the substrate and the conductive path layer, preventing short circuits in the solar cell, ensuring the normal operation of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.
  • the conductive path layer connects part of the first doped layer and part of the second doped layer.
  • This conductive path layer enables soft breakdown between the first and second doped layers, preventing hot spot effects when the solar cell is shaded. Moreover, while preventing hot spot effects, it also ensures the photoelectric conversion efficiency of the solar cell under normal operating conditions.
  • Figure 1 shows a cross-sectional view of the solar cell described in an embodiment of this application
  • Figure 2 shows a second cross-sectional view of the solar cell described in an embodiment of this application
  • FIG. 3 shows a cross-sectional view of the solar cell described in the embodiment of this application.
  • Figure 4 shows a cross-sectional view of the solar cell according to another embodiment of this application.
  • Figure 5 shows a second cross-sectional view of the solar cell described in another embodiment of this application.
  • Figure 6 shows a cross-sectional view three of the solar cell described in another embodiment of this application.
  • Figure 7 shows a cross-sectional view four of the solar cell described in another embodiment of this application.
  • Figure 8 shows a cross-sectional view of the solar cell described in yet another embodiment of this application.
  • Figure 9 shows a second cross-sectional view of the solar cell described in yet another embodiment of this application.
  • Figure 10 shows a third cross-sectional view of the solar cell described in yet another embodiment of this application.
  • Figure 11 shows a cross-sectional view four of the solar cell described in yet another embodiment of this application.
  • FIG. 12 shows a flowchart of the solar cell fabrication method described in the embodiments of this application.
  • FIG. 1 a cross-sectional view of the solar cell in an embodiment of this application is shown; referring to Figure 2, a cross-sectional view of the solar cell in an embodiment of this application is shown; referring to Figure 3, a cross-sectional view of the solar cell in an embodiment of this application is shown; referring to Figure 4, a cross-sectional view of the solar cell in another embodiment of this application is shown; referring to Figure 5, a cross-sectional view of the solar cell in another embodiment of this application is shown; referring to Figure 6, a cross-sectional view of the solar cell in another embodiment of this application is shown; referring to Figure 7, a cross-sectional view of the solar cell in another embodiment of this application is shown; referring to Figure 8, a cross-sectional view of the solar cell in yet another embodiment of this application is shown; referring to Figure 9, a cross-sectional view of the solar cell in yet another embodiment of this application is shown; referring to Figure 10, a cross-sectional view of the solar cell in yet another embodiment of this application is shown; referring to
  • this application discloses a solar cell, which includes a substrate 100.
  • the substrate 100 has a first surface and a second surface disposed opposite to each other.
  • the first surface includes a first region and a second region disposed at intervals, and a third region located between the first region and the second region.
  • a first doped layer 101 and a second doped layer 102 are also included.
  • the first doped layer 101 is disposed on the surface of the first region or at least partially embedded in the surface of the first region
  • the second doped layer 102 is disposed on the surface of the second region or at least partially embedded in the surface of the second region.
  • the polarity of the second doped layer 102 is opposite to that of the first doped layer 101.
  • a dielectric layer 1031 and a conductive path layer 1032 are also included. Along a direction away from the substrate 100, the dielectric layer 1031 and the conductive path layer 1032 are sequentially stacked in the third region. The dielectric layer 1031 blocks the first doped layer 101 and the second doped layer 102, and the conductive path layer 1032 connects a portion of the first doped layer 101 and a portion of the second doped layer 102.
  • Solar cells are the core component of photovoltaic modules, converting solar energy into electrical energy. As shown in Figures 1 to 11, embodiments of this application disclose a solar cell that can be used in photovoltaic modules to prevent hot spot effects from occurring on the solar cells when the photovoltaic module is shaded, thus affecting the photoelectric conversion efficiency of the photovoltaic module.
  • the solar cell disclosed in this application includes a substrate 100.
  • the substrate 100 is the core component of the solar cell, which converts solar energy into electrical energy.
  • the substrate 100 can be a P-type substrate, an N-type substrate, or an intrinsically conductive silicon wafer.
  • the crystal type can be monocrystalline or polycrystalline, etc.
  • the substrate 100 can also be other types of substrates.
  • no specific restrictions are placed on the specific type of substrate 100. In practical applications, those skilled in the art can select appropriate materials as the substrate 100 as needed.
  • the substrate 100 in this embodiment has a first surface and a second surface disposed opposite to each other, wherein the first surface is the back side of the solar cell and the second surface is the front side of the solar cell.
  • the solar cell disclosed in this embodiment is a back-contact solar cell.
  • the first surface of the substrate 100 includes a first region and a second region spaced apart, and a third region located between the first region and the second region.
  • a first doped layer 101 is disposed on the surface of the first region or at least partially embedded in the surface of the first region
  • a second doped layer 102 is disposed on the surface of the second region or at least partially embedded in the surface of the second region.
  • the polarity of the second doped layer 102 is opposite to that of the first doped layer 101, so as to collect the current generated by the substrate 100 through the first doped layer 101 and the second doped layer 102.
  • the first doped layer 101 and the second doped layer 102 can be one or more of polycrystalline silicon, amorphous silicon, microcrystalline silicon, and monocrystalline silicon.
  • the second doped layer 102 is an N-type doped layer.
  • the first doped layer 101 is an N-type doped layer
  • the second doped layer 102 is a P-type doped layer.
  • P-type layers are generally doped with Group IIIA elements
  • N-type layers are generally doped with Group VA elements.
  • the dielectric layer 1031 and the conductive path layer 1032 are sequentially stacked in the third region.
  • the dielectric layer 1031 blocks the first doped layer 101 and the second doped layer 102, and also blocks the substrate 100 and the conductive path layer 1032, thus preventing short circuits in the solar cell, ensuring normal operation of the solar cell, and improving the photoelectric conversion efficiency of the solar cell.
  • the dielectric layer 1031 in this embodiment includes a semiconductor layer and/or an insulating layer.
  • the insulating layer and the semiconductor layer are sequentially stacked on the surface of the third region along the direction away from the substrate 100.
  • the conductive path layer 1032 is stacked on the side of the semiconductor layer away from the insulating layer.
  • the semiconductor layer includes an intrinsic semiconductor layer and an electrically neutral co-doped semiconductor layer, wherein the intrinsic semiconductor layer includes at least one of intrinsic amorphous silicon, intrinsic polycrystalline silicon, intrinsic monocrystalline silicon, etc.
  • the electrically neutral co-doped semiconductor layer refers to a co-doped semiconductor layer with an element doping concentration not exceeding 1E18 cm ⁇ 3 , exhibiting absolute electrical neutrality, a weak positive charge, or a weak negative charge.
  • the electrically neutral co-doped semiconductor layer is a polycrystalline silicon layer simultaneously doped with phosphorus and boron.
  • a conductive path layer 1032 is stacked on the side of the dielectric layer 1031 away from the substrate 100.
  • the conductive path layer 1032 connects a portion of the first doped layer 101 and a portion of the second doped layer 102, thus conducting the first doped layer 101 and the second doped layer 102.
  • the conductive path layer 1032 enables soft breakdown of the first doped layer 101 and the second doped layer 102, preventing hot spot effects when the solar cell is shaded. Furthermore, this arrangement, while addressing the hot spot effect, also ensures the photoelectric conversion efficiency of the solar cell under normal operating conditions.
  • the thickness of the dielectric layer 1031 is greater than the thickness of the conductive path layer 1032.
  • the thickness of the dielectric layer 1031 is set to be greater than the thickness of the conductive path layer 1032 along the thickness direction of the solar cell. This setting results in a thicker dielectric layer 1031, which ensures electrical isolation between the first doped layer 101 and the second doped layer 102, as well as electrical isolation between the substrate 100 and the conductive path layer 1032. This leads to higher photoelectric conversion efficiency of the solar cell under normal operating conditions.
  • the conductive path layer 1032 is thinner than the dielectric layer 1031, and soft breakdown between the first doped layer 101 and the second doped layer 102 is achieved through the conductive path layer 1032.
  • the conductive path layer 1032 can prevent hot spots, thus avoiding the hot spot effect on the solar cell.
  • the above configuration allows for the placement of a dielectric layer 1031 between the first doped layer 101 and the second doped layer 102 across the entire area of the solar cell, achieving heat spot prevention across the entire area. This eliminates the need for other spatial spacing grooves, simplifying the fabrication process of the solar cell and reducing its production cost.
  • the thickness of the conductive path layer 1032 is greater than the thickness of the dielectric layer 1031.
  • the thickness of the conductive path layer 1032 is set to be greater than the thickness of the dielectric layer 1031 along the thickness direction of the battery cell to increase the conductive path. Only a small number of anti-hot spot structures are needed across the entire battery cell area to achieve the anti-hot spot effect of the entire battery cell.
  • the dielectric layer 1031 and the conductive path layer 1032 can be sequentially stacked over the entire area of at least one third region on the first surface of the substrate 100, or the dielectric layer 1031 and the conductive path layer 1032 can be sequentially stacked over at least a portion of the area of at least one third region on the first surface of the substrate 100.
  • positions of the different conductive path layers 1032 located on the multiple third regions of the first surface of the substrate 100 can correspond to each other or be staggered. This application does not impose specific limitations on this. In practical applications, those skilled in the art can configure them as needed.
  • the base material of the dielectric layer 1031 and the conductive path layer 1032 is the same.
  • the dielectric layer 1031 and the conductive path layer 1032 are made of the same base material.
  • both the dielectric layer 1031 and the conductive path layer 1032 comprise polysilicon; the conductive path layer 1032 is formed by doped polysilicon, and the dielectric layer 1031 is formed by undoped polysilicon.
  • the undoped polysilicon can also be referred to as intrinsic polysilicon.
  • the above specific embodiments are merely individual examples of this application and are not intended to limit the application. In practical applications, those skilled in the art can set the base materials of the dielectric layer 1031 and the conductive path layer 1032 as needed.
  • the base materials of the dielectric layer 1031 and the conductive path layer 1032 in this embodiment are the same as the base materials of the first doped layer 101 and the second doped layer 102.
  • This configuration simplifies the cell fabrication process, enabling the patterning of the cell. By depositing semiconductor films in a single step and performing different degrees of doping, the aforementioned structure can be formed.
  • the base materials of the dielectric layer 1031 and the conductive path layer 1032 are different.
  • the base materials of the dielectric layer 1031 and the conductive path layer 1032 in this embodiment can also be different.
  • the dielectric layer 1031 can also be an insulating layer.
  • the dielectric layer 1031 can be at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, silicon carbide, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and intrinsic monocrystalline silicon.
  • the conductive path layer 1032 can be at least one of doped amorphous silicon, doped polycrystalline silicon, and doped monocrystalline silicon.
  • the conductive path layer 1032 includes a layer doped with one element; and/or, the conductive path layer 1032 includes a layer doped with two elements of opposite polarity.
  • the conductive path layer 1032 may be doped with an element to improve its conductivity, achieving soft breakdown of the first doped layer 101 and the second doped layer 102, and preventing hot spot effects when the solar cell is shaded.
  • the conductive path layer 1032 may be doped with only boron, or only phosphorus.
  • the conductive path layer 1032 can also be doped with two elements of opposite polarity to simplify the cell fabrication process, facilitate cell fabrication, and reduce cell fabrication costs.
  • the conductive path layer 1032 is doped with both boron and phosphorus.
  • the concentration of the doped element decreases along the direction from the conductive path layer 1032 to the substrate 100.
  • the conductive path layer 1032 in this embodiment includes a single-doped path layer 1032a and a co-doped path layer 1032b, wherein the single-doped path layer 1032a is stacked on the side of the dielectric layer 1031 away from the substrate 100, and the co-doped path layer 1032b is stacked on the side of the single-doped path layer 1032a away from the dielectric layer 1031; the single-doped path layer 1032a is doped with one element, and the co-doped path layer 1032b is doped with two elements of opposite polarity.
  • the conductive path layer 1032 is configured as two layers.
  • One layer is a single-doped path layer 1032a, which is stacked on the side of the dielectric layer 1031 away from the substrate 100.
  • the single-doped path layer 1032a is doped with one element.
  • the other layer is a co-doped path layer 1032b, which is stacked on the side of the single-doped path layer 1032a away from the dielectric layer 1031.
  • the co-doped path layer 1032b is doped with two elements of opposite polarity. One of these two elements is the same as the doping element in the single-doped path layer 1032a.
  • the above-described design reduces the manufacturing complexity of solar cells, simplifies the cell fabrication process, and lowers production costs. Furthermore, this design also prevents hot spot effects when the cells are shaded. Moreover, while preventing hot spot effects, it also ensures the photoelectric conversion efficiency of the cells under normal operating conditions.
  • the single-doped path layer 1032a and the co-doped path layer 1032b have the same conductivity type.
  • the conductivity type of the single-doped path layer 1032a is set to be the same as that of the co-doped path layer 1032b, so that the soft breakdown interface between the first doped layer 101 and the second doped layer 102 is more uniform and the hot spot prevention effect is better.
  • the surface element doping concentration of the conductive path layer 1032 is greater than or equal to the surface element doping concentration of the first doped layer 101; and/or, the surface element doping concentration of the conductive path layer 1032 is greater than or equal to the surface element doping concentration of the second doped layer 102.
  • the surface element doping concentration of the conductive path layer 1032 is set to be greater than or equal to the surface element doping concentration of the first doped layer 101; and/or, the surface element doping concentration of the conductive path layer 1032 is set to be greater than or equal to the surface element doping concentration of the second doped layer 102.
  • the surface element doping concentration of the conductive path layer 1032 can be controlled, making the conductive path layer 1032 thinner, thereby improving the heat spot prevention effect of the solar cell and ensuring the photoelectric conversion efficiency of the solar cell.
  • the thickness of the conductive path layer 1032 is d1 , satisfying 10nm ⁇ d1 ⁇ 120nm ; and/or, the element doping concentration of the conductive path layer 1032 is greater than 1E18cm -3 and less than 5E22cm -3 .
  • the thickness of the conductive path layer 1032 is set to d1 along the thickness direction of the solar cell.
  • d1 is greater than or equal to 10 nm and less than or equal to 120 nm.
  • the thickness of the conductive path layer 1032 along the thickness direction of the battery cell can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, etc.
  • the doping concentration of the elements in the conductive path layer 1032 is greater than or equal to 1E18cm ⁇ 3 and less than 5E22cm ⁇ 3 .
  • the doping concentration of the elements in the conductive path layer 1032 can conduct electricity, achieving a soft breakdown effect in the solar cell.
  • the element doping concentration in the conductive path layer 1032 can be 1E18cm -3 , 1E20cm - 3 , 2E18cm-3, 3E18cm -3 , 4E18cm -3 , 5E18cm -3 , 5E22cm -3 , etc.
  • the element doping concentration of the dielectric layer 1031 is less than 1E13cm ⁇ 3 ; and/or, along the thickness direction of the cell, the thickness of the dielectric layer 1031 is d2 , satisfying 20nm ⁇ d2 ⁇ 490nm .
  • the doping concentration of the elements in the dielectric layer 1031 is set to be less than 1E13cm ⁇ 3 , so that the dielectric layer 1031 has insulating properties.
  • the dielectric layer 1031 can block the first doped layer 101 and the second doped layer 102, as well as the substrate 100 and the conductive path layer 1032, thereby achieving electrical isolation between the first doped layer 101 and the second doped layer 102, and between the substrate 100 and the conductive path layer 1032.
  • the doping concentration of elements in the dielectric layer 1031 can be 1E12cm -3 , 1E11cm -3 , 1E10cm -3 , 1E9cm -3 , etc.
  • the thickness of the dielectric layer 1031 is set to d2 along the thickness direction of the battery cell, wherein d2 is greater than or equal to 20nm and less than or equal to 490nm, so as to block the first doped layer 101 and the second doped layer 102, as well as the substrate 100 and the conductive path layer 1032 through the dielectric layer 1031, thereby achieving electrical isolation between the first doped layer 101 and the second doped layer 102, and electrical isolation between the substrate 100 and the conductive path layer 1032.
  • the thickness of the dielectric layer 1031 can be 20nm, 50nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 490nm, etc.
  • the substrate 100 corresponding to the third region has a third doped region, and the element doping concentration of the third doped region is less than 1E13cm ⁇ 3 .
  • the substrate 100 has a third doped region corresponding to the third region, and the doping concentration of the elements in the third doped region is set to be less than 1E13cm ⁇ 3 .
  • a dielectric layer 1031 is disposed between the conductive path layer 1032 and the third doped region of the substrate 100. The dielectric layer 1031 can block the conductive path layer 1032 and the third doped region of the substrate 100, preventing the doped elements in the conductive path layer 1032 from diffusing into the third doped region of the substrate 100, so as to ensure that the solar cell has a higher photoelectric conversion efficiency under normal operating conditions.
  • the doping concentration of the elements in the third doped region of the substrate 100 can be 1E12cm -3 , 1E11cm -3 , 1E10cm -3 , 1E9cm -3 , 1E8cm -3 , etc.
  • the substrate 100 corresponding to the first region has a first doped region, the element doping concentration of the first doped region being greater than 1E13cm ⁇ 3 ; and/or, the substrate 100 corresponding to the second region has a second doped region, the element doping concentration of the second doped region being greater than 1E13cm ⁇ 3 .
  • the substrate 100 has a first doped region at the position corresponding to the first region, a second doped region at the position corresponding to the second region, and a third doped region located between the first doped region and the second doped region.
  • the doping concentration of the element in the first doping region is set to be greater than 1E13 cm ⁇ 3
  • the doping concentration of the element in the second doping region is also set to be greater than 1E13 cm ⁇ 3 .
  • the first and second doping regions have different depths within the substrate 100. Through these settings, the solid solubility of different doping elements is matched, enabling effective doping of the first doped layer 101 and the second doped layer 102, and achieving sufficient separation of charge carriers.
  • the boron dopant has a deeper diffusion depth in the substrate 100, while the phosphorus dopant has a relatively shallower diffusion depth in the substrate 100.
  • the boron diffusion depth is capped at E17 cm ⁇ 3
  • the phosphorus diffusion depth is capped at E18 cm ⁇ 3 .
  • the first doped layer 101 in this embodiment includes a first mono-doped layer 1011 and a first co-doped layer 1012.
  • the first co-doped layer 1012 is doped with two elements of opposite polarity.
  • the first mono-doped layer 1011 is stacked on the surface of the first region or at least partially embedded in the surface of the first region.
  • the first co-doped layer 1012 is stacked on the side of the first mono-doped layer 1011 away from the substrate 100.
  • the first co-doped layer 1012 has an opposite conductivity type to the first mono-doped layer 1011.
  • the solar cell also includes a first electrode 106, which is coupled to the first region of the substrate 100.
  • the first co-doped layer 1012 is provided with a through groove 1012a.
  • the first electrode 106 is embedded in the through groove 1012a and connected to the first mono-doped layer 1011 or the first region of the substrate 100. There is a gap between the first electrode 106 and the inner wall of the through groove 1012a.
  • the first doped layer 101 is configured as two layers: a first mono-doped layer 1011 and a first co-doped layer 1012.
  • the first mono-doped layer 1011 and the first co-doped layer 1012 have opposite conductivity types.
  • the first mono-doped layer 1011 is doped with one element and is stacked on the surface of the first region or at least partially embedded in the surface of the first region.
  • the first co-doped layer 1012 is doped with two elements of opposite polarity and is stacked on the side of the first mono-doped layer 1011 away from the substrate 100. This configuration reduces the manufacturing difficulty of the solar cell, simplifies the process flow, and lowers the manufacturing cost.
  • the battery cell disclosed in this embodiment further includes a first electrode 106, which is coupled to a first region of the substrate 100 to collect charge carriers generated in the first region of the substrate 100.
  • the first electrode 106 can be embedded in a surface passivation layer or antireflection layer 105 and connected to a first co-doped layer 1012.
  • the first electrode 106 can also be embedded in the surface passivation layer or antireflection layer 105 and the first co-doped layer 1012, with one end of the first electrode 106 connected to the position of the first mono-doped layer 1011 corresponding to the first region.
  • the first electrode 106 can also be embedded in the surface passivation layer or antireflection layer 105, the first co-doped layer 1012, and the first mono-doped layer 1011, with one end of the first electrode 106 connected to the surface of the tunneling passivation layer or the first region of the substrate 100.
  • the first electrode 106 can collect charge carriers generated in the first region of the substrate 100.
  • a through-groove 1012a can also be provided on the first co-doped layer 1012, and one end of the first electrode 106 can be connected to the position corresponding to the first mono-doped layer 1011 and the first region through the through-groove 1012a, or one end of the first electrode 106 can be directly connected to the surface of the first region of the tunneling passivation layer or the substrate 100.
  • the configuration of the second electrode 107 in this embodiment is similar to that of the first electrode 106, and will not be described again here.
  • the uniformity of element doping concentration in the first single-doped layer 1011 is better than the uniformity of element doping concentration in the first co-doped layer 1012.
  • the first single-doped layer 1011 is used as the first conductivity type, and the first co-doped layer 1012 is used as the second conductivity type for explanation. It can be understood that the first single-doped layer 1011 is doped with only one type of element, while the first co-doped layer 1012 is doped with both one type of element and two types of elements.
  • the type of element can be a group IIIA element, such as boron, aluminum, gallium, etc.
  • the type of element can be a group VA element, such as phosphorus, antimony, arsenic, etc.
  • the thickness of the first single-doped layer 1011 is greater than or equal to 20 nm and less than or equal to 490 nm, and the thickness of the first co-doped layer 1012 is greater than or equal to 10 nm and less than or equal to 480 nm.
  • the doping concentration distribution of one type of element is basically on the same order of magnitude, and the concentration uniformity is less than 50%.
  • the doping concentration of one type of element is almost uniformly distributed, and the concentration uniformity is less than 20%.
  • the doping concentrations of one type of element in the first co-doped layer 1012 and the first mono-doped layer 1011 are basically on the same order of magnitude.
  • the doping concentration of one type of element ranges from 1E16 cm ⁇ 3 to 1E21 cm ⁇ 3 .
  • the doping concentration of one type of element ranges from 1E16 cm ⁇ 3 to 1E21 cm ⁇ 3
  • the doping concentration of two types of element ranges from 1E17 cm ⁇ 3 to 1E22 cm ⁇ 3 .
  • the boron doping concentration at different depths in the first mono-doped layer 1011 was tested.
  • the boron doping concentration was 6E19cm ⁇ 3 near the substrate 100 and 7E19cm ⁇ 3 away from the substrate 100.
  • the concentration was 7.7%, which is less than 20%.
  • the boron doping concentration at different depths in the first co-doped layer 1012 was tested.
  • the boron doping concentration was 7E19cm ⁇ 3 near the substrate 100 and 3E19cm ⁇ 3 away from the substrate 100.
  • the uniformity of elemental doping concentration within the first mono-doped layer 1011 is set to be better than the uniformity of elemental doping concentration within the first co-doped layer 1012. This setting ensures the carrier separation efficiency within the first mono-doped layer 1011. Furthermore, this setting also ensures that the first mono-doped layer 1011 does not affect the passivation effect of the substrate 100.
  • the second doped layer 102 in this embodiment includes a second mono-doped layer 1021 and a second co-doped layer 1022.
  • the second co-doped layer 1022 is doped with two elements of opposite polarity.
  • the second mono-doped layer 1021 is stacked on the surface of the second region or at least partially embedded in the surface of the second region.
  • the second co-doped layer 1022 is stacked on the side of the second mono-doped layer 1021 away from the substrate 100.
  • the second co-doped layer 1022 and the second mono-doped layer 1021 have the same conductivity type.
  • the second doped layer 102 in this embodiment includes two layers: a second mono-doped layer 1021, in which one element is doped; and a second co-doped layer 1022, in which two elements with opposite polarities are doped.
  • the second mono-doped layer 1021 and the second co-doped layer 1022 have the same conductivity type.
  • the second mono-doped layer 1021 is stacked on the surface of the second region or at least partially embedded in the surface of the second region, and the second co-doped layer 1022 is stacked on the side of the second mono-doped layer 1021 away from the substrate 100.
  • This configuration reduces the manufacturing difficulty of the solar cell, simplifies the process flow, and lowers the manufacturing cost.
  • the second electrode 107 can contact the second mono-doped layer 1021 alone or the second co-doped layer 1022 alone.
  • the second electrode 107 can also contact the second mono-doped layer 1021 and the second co-doped layer 1022 simultaneously.
  • the contact formed is better, and the reliability of the solar cell is higher.
  • the thickness of the second co-doped layer 1022 is greater than the thickness of the first co-doped layer 1012, and the thickness of the first co-doped layer 1012 is greater than or equal to the thickness of the co-doped path layer 1032b.
  • the thickness of the co-doped path layer 1032b cannot be too thick to ensure the effectiveness of the solar cell in preventing hot spots and maintaining its photoelectric conversion efficiency.
  • the second co-doped layer 1022 does not affect the conductivity type of the second doped layer 102; therefore, the thickness of the second co-doped layer 1022 can be relatively thick.
  • the thickness of the first co-doped layer 1012 cannot be too thick, as an excessively thick first co-doped layer 1012 will affect the carrier collection efficiency in the first region.
  • the thickness of the first co-doped layer 1012 also cannot be too thin.
  • An excessively thin first co-doped layer 1012 will increase the number of processing steps required for the solar cell, necessitating separate processing to form the co-doped path layer 1032b, thus increasing the manufacturing cost of the solar cell.
  • the thickness of the second co-doped layer 1022 is set to be greater than the thickness of the first co-doped layer 1012, and the thickness of the first co-doped layer 1012 is set to be greater than or equal to the thickness of the co-doped path layer 1032b.
  • the first doped layer 101 has a first concentration gradient co-doped region (not shown in the figure) on the side near the conductive path layer 1032; and/or, the second doped layer 102 has a second concentration gradient co-doped region 108 on the side near the conductive path layer 1032.
  • the region of the first doped layer 101 near the first electrode 106 has a higher element doping concentration to facilitate carrier collection, as well as current transmission and collection.
  • the element doping concentration is even higher in the first doped layer 101 below the first electrode 106 to effectively reduce the metal-semiconductor contact resistance.
  • the element doping concentration is lower, which is conducive to Auger recombination, thereby improving the photoelectric conversion efficiency of the solar cell.
  • a first concentration gradient co-doped region is provided on the side of the first doped layer 101 near the conductive path layer 1032, and/or a second concentration gradient co-doped region 108 is provided on the side of the second doped layer 102 near the conductive path layer 1032, so as to improve the current collection efficiency of the solar cell and improve the photoelectric conversion efficiency of the solar cell.
  • the width of the first concentration-gradient co-doped region is greater than the width of the second concentration-gradient co-doped region 108.
  • the width of the first concentration gradient co-doped region is greater than the width of the second concentration gradient co-doped region 108.
  • the above settings can improve carrier transport efficiency, current transport and collection efficiency, and reduce metal-semiconductor contact without increasing process complexity.
  • the above-described method of setting the first doped layer 101 as a P-type doped layer and the second doped layer 102 as an N-type doped layer is merely a specific example of this application and is not intended to limit the scope of this application. In practical applications, those skilled in the art can set the specific doping types of the first doped layer 101 and the second doped layer 102 as needed.
  • the conductive path layer 1032 has a first depth-gradient co-doped region 1032c on the side near the first doped layer 101, and a second depth-gradient co-doped region (not shown in the figure) on the side near the second doped layer 102.
  • a first depth-gradient co-doped region 1032c is formed on the side of the conductive path layer 1032 near the first doped layer 101
  • a second depth-gradient co-doped region is formed on the side of the conductive path layer 1032 near the second doped layer 102.
  • the heat dissipation test standard was as follows: a reverse bias voltage of 15V was applied for 100ms, and the temperature difference of the cell before and after the application was measured. The temperature at the point of highest temperature change after applying current was used as the standard ⁇ T/°C.
  • the heat dissipation test results are shown in Table 1 below.
  • the solar cell only separates the first doped layer 101 and the second doped layer 102 by spatial spacing, without providing a conductive path layer 1032 and a dielectric layer 1031.
  • the first doped layer 101 and the second doped layer 102 of the solar cell are connected by the dielectric layer 1031 and the conductive path layer 1032.
  • the first doped layer 101 and the second doped layer 102 of the solar cell are connected by the dielectric layer 1031 and the conductive path layer 1032.
  • the first doped layer 101 includes a first single-doped layer 1011 and a first co-doped layer 1012.
  • the first doped layer 101 and the second doped layer 102 of the solar cell are connected by the dielectric layer 1031 and the conductive path layer 1032.
  • the first doped layer 101 includes a first mono-doped layer 1011 and a first co-doped layer 1012
  • the second doped layer 102 includes a second mono-doped layer 1021 and a second co-doped layer 1022.
  • the solar cells disclosed in Examples 1, 2, and 3 of this application have lower hot spot test temperatures, a lower proportion of cells exceeding 3°C, and better protection against hot spot effects.
  • the photoelectric conversion efficiency of the solar cells with co-doped layers disclosed in Examples 2 and 3 is slightly improved.
  • an embodiment of this application discloses a method for preparing a battery cell, the method comprising:
  • a substrate having a first surface and a second surface disposed opposite to each other, the first surface including a first region and a second region disposed at intervals and a third region located between the first region and the second region.
  • the substrate serves as the core component of the solar cell, converting solar energy into electrical energy.
  • the substrate can be a P-type substrate, an N-type substrate, or an intrinsically conductive silicon wafer.
  • the crystal type can be monocrystalline or polycrystalline, etc.
  • the substrate can also be other types.
  • no specific restrictions are placed on the type of substrate; in practical applications, those skilled in the art can select appropriate materials as the substrate according to their needs.
  • the substrate needs to undergo surface treatment before being provided.
  • Surface treatment includes steps such as removing damage, removing stains, polishing, and texturing.
  • the substrate in this embodiment of the application has a first surface and a second surface disposed opposite to each other, wherein the first surface is the back side of the battery cell, and the second surface is the front side of the battery cell.
  • the solar cell disclosed in this application is a back-contact solar cell.
  • the first surface of the substrate has a first region and a second region spaced apart, and a third region located between the first region and the second region.
  • a first doped layer is formed on or within the surface of the first region, and a second doped layer is formed on or within the surface of the second region, wherein the polarities of the first doped layer and the second doped layer are opposite.
  • the first doped layer 101 and the second doped layer 102 can both be one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon.
  • the second doped layer 102 is an N-type doped layer.
  • the first doped layer 101 is an N-type doped layer
  • the second doped layer 102 is a P-type doped layer.
  • P-type layers are generally doped with Group IIIA elements
  • N-type layers are generally doped with Group VA elements.
  • first doped layer 101 and the second doped layer 102 there is no specific restriction on the formation order of the first doped layer 101 and the second doped layer 102.
  • the first doped layer 101 can be formed first, followed by the second doped layer 102.
  • the second doped layer 102 can be formed first, followed by the first doped layer 101. In practical applications, those skilled in the art can choose according to their needs.
  • forming a first doped layer on or within the surface of the first region, and forming a second doped layer on or within the surface of the second region includes: forming a semiconductor layer on a first surface of the substrate, and forming a first doped source layer and a second doped source layer at positions of the semiconductor layer corresponding to the first and second regions, respectively. Heating is used to advance the first and second doped source layers, such that the portion of the semiconductor layer corresponding to the first region forms the first doped layer, and the portion of the semiconductor layer corresponding to the second region forms the second doped layer, with the first and second doped layers having opposite polarities.
  • laser heating can be used to propel elements within the first and second doped source layers to form the first and second doped layers.
  • the above-described laser heating propulsion method is merely a specific example of the embodiments of this application and is not intended to limit the scope of this application. In practical applications, those skilled in the art can select appropriate doping methods as needed.
  • the first doped source layer can be formed first, then heated and advanced, followed by the formation of the second doped source layer, and then heated and advanced again.
  • the second doped source layer can be formed first, followed by the formation of the first doped source layer, and then the heating and advancing of the first and second doped source layers sequentially.
  • an interface passivation layer 104 can be formed on the first surface of the substrate to protect the substrate.
  • the interface passivation layer 104 in this embodiment can be a single-layer structure or a multi-layer structure.
  • the interface passivation layer 104 includes one or more of the following: silicon nitride layer, silicon oxide layer, silicon oxynitride layer, aluminum oxide layer, silicon carbide layer, and amorphous silicon layer.
  • forming a first doped layer on or within the surface of the first region includes:
  • a semiconductor layer is formed on a first surface of a substrate, and a first doped source layer is formed at a location corresponding to a first region of the semiconductor layer.
  • the first doped source layer is then heated and advanced to form a first mono-doped layer at a portion of the semiconductor layer corresponding to the first region.
  • a fourth doped source layer is formed on the first mono-doped layer.
  • the fourth doped source layer is then heated and advanced to form a first co-doped layer on the side of the first mono-doped layer away from the substrate.
  • the first mono-doped layer and the first co-doped layer constitute the first doped layer.
  • the fourth doped source layer and the second doped source layer can be the same layer.
  • the preparation of the first doped layer by the above method which includes a first mono-doped layer and a first co-doped layer, can reduce the process difficulty of solar cells, simplify the process flow of solar cells, and reduce the manufacturing cost of solar cells.
  • the method further includes:
  • a through-groove is provided on the first co-doped layer, and a first electrode is embedded in the through-groove and connected to the first region of the first mono-doped layer or the substrate. There is a gap between the first electrode and the inner wall of the through-groove.
  • a through-groove is provided in the first co-doped layer, a first electrode is embedded in the through-groove, and one end of the first electrode is connected to the first mono-doped layer or the first region of the substrate, so as to collect the charge carriers generated in the first region of the substrate through the first electrode.
  • a dielectric layer and a conductive path layer are sequentially stacked in the third region to block the first doped layer and the second doped layer through the dielectric layer, and to connect a portion of the first doped layer and a portion of the second doped layer through the conductive path layer.
  • the solar cell fabrication method disclosed in the embodiments of this application is used to fabricate a solar cell.
  • a dielectric layer and a conductive path layer are sequentially stacked in the third region.
  • the dielectric layer blocks the first doped layer and the second doped layer.
  • the dielectric layer can also block the substrate and the conductive path layer, avoid short circuits in the solar cell, ensure normal operation of the solar cell, and improve the photoelectric conversion efficiency of the solar cell.
  • the conductive path layer can achieve soft breakdown between the first doped layer and the second doped layer, avoiding the hot spot effect when the solar cell is shaded. In addition, while taking into account the hot spot effect, it can also ensure the photoelectric conversion efficiency of the cell under normal operation.
  • the dielectric layer and the conductive path layer are sequentially stacked, including:
  • a semiconductor layer is formed on the first surface of the substrate, and a third doped source layer is formed at the position of the semiconductor layer corresponding to the third region.
  • the third doped source layer is heated and advanced so that a dielectric layer and a conductive path layer are sequentially formed in the part of the semiconductor layer corresponding to the third region in a direction away from the substrate.
  • the method for fabricating a battery cell disclosed in this application after forming a first doped layer, a second doped layer, a dielectric layer, and a conductive path layer, further includes:
  • the process involves removing residual dopant sources from the surface of the solar cells and cleaning them. Further surface modification steps, such as etching, are then required. Etching modifies the surface dopant in different areas, removing surfaces with excessively high or low doping concentrations. Surfaces with excessively high doping concentrations can lead to Auger recombination regions, while surfaces with excessively low doping concentrations are detrimental to subsequent contact between the surface metal and electrodes. These processes result in improved solar cell performance.
  • the method further includes:
  • a surface passivation layer is formed on the side of the first doped layer, the second doped layer, and the conductive path layer away from the substrate.
  • a first electrode and a second electrode are formed within the surface passivation layer. The first electrode is electrically connected to the first doped layer, and the second electrode is electrically connected to the second doped layer. The first electrode collects charge carriers in the first doped layer and transmits the current collected in the first doped layer, while the second electrode collects charge carriers in the second doped layer and transmits the current collected in the second doped layer.
  • a surface passivation layer or antireflection layer can be formed simultaneously on the side of the first doped layer away from the substrate, the side of the second doped layer away from the substrate, and the side of the conductive path layer away from the substrate. This ensures that the structure of the surface passivation layer or antireflection layer corresponding to the first region, the second region, and the third region is completely identical.
  • the surface passivation layer or antireflection layer in the embodiments of this application can be a single-layer structure or a multi-layer structure.
  • the surface passivation layer or antireflection layer includes one or more of the following: silicon nitride layer, silicon oxide layer, silicon oxynitride layer, aluminum oxide layer, silicon carbide layer, amorphous silicon layer, and transparent conductive oxide (TCO).
  • atomic layer deposition ALD
  • chemical vapor deposition CVD
  • PECVD plasma enhanced chemical vapor deposition
  • APCVD atmospheric pressure chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • MOCVD metal-organic chemical vapor deposition
  • PEVD physical vapor deposition
  • an aluminum oxide passivation layer can be prepared first by atomic layer deposition (ALD), and then one or more silicon nitride layers can be formed on the aluminum oxide passivation layer by plasma enhanced chemical vapor deposition (PECVD).
  • ALD atomic layer deposition
  • PECVD plasma enhanced chemical vapor deposition
  • the first and second electrodes in this embodiment can be made of metals such as Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, etc., or metal nitrides such as TiN, metal carbides such as TiC, etc., or metal sulfides.
  • metals such as Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, etc.
  • metal nitrides such as TiN, metal carbides such as TiC, etc., or metal sulfides.
  • no specific limitations are placed on the materials used for the first and second electrodes. In practical applications, those skilled in the art can select appropriate materials as needed.
  • This application also discloses a photovoltaic module, which includes the solar cells described in the above embodiments.
  • the photovoltaic module includes solar cells with the same structure as the solar cells described in the above embodiments, and their beneficial effects are similar, so they will not be repeated here.

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Abstract

本申请公开了一种太阳能电池片、太阳能电池片的制备方法及光伏组件，属于光伏技术领域。太阳能电池片包括基底，基底具有相对设置的第一表面和第二表面，第一表面包括间隔设置的第一区域和第二区域以及位于第一区域和第二区域之间的第三区域；第一掺杂层和第二掺杂层，第一掺杂层设置于第一区域的表面上或者至少部分嵌设于第一区域的表面内，第二掺杂层设置于第二区域的表面上或者至少部分嵌设于第二区域的表面内，第二掺杂层与第一掺杂层的极性相反；介质层和导电路径层，沿远离基底的方向，介质层和导电路径层依次叠置于第三区域，介质层阻隔第一掺杂层和第二掺杂层，导电路径层连接部分第一掺杂层和部分第二掺杂层。

Description

太阳能电池片、太阳能电池片的制备方法及光伏组件 技术领域
本申请涉及光伏技术领域，具体涉及一种太阳能电池片、太阳能电池片的制备方法及光伏组件。
背景技术
太阳能电池片可以将太阳能转化为电能。而背接触式太阳能电池片作为太阳能电池片中的一种，背接触式太阳能电池片的电极均设置于电池片的背面，以避免电极遮挡电池片的正面，从而提升电池片的光电转化效率。
现有的背接触式太阳能电池片通常包括基底，基底具有正面和背面，背面具有第一区域、第二区域以及设置于第一区域和第二区域之间的第三区域，第一掺杂层叠置于第一区域，第二掺杂层叠置于第二区域，介质层叠置于第三区域。通过介质层阻隔第一掺杂层和第二掺杂层，以防止电池片漏电，提升电池片的光电转化效率。
然而，现有的背接触式太阳能电池片很容易出现热斑问题。
发明内容
本申请公开了一种太阳能电池片、太阳能电池片的制备方法及光伏组件，以解决或者至少部分解决现有技术中存在的背接触式太阳能电池片容易出现热斑的问题。
为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请公开了一种太阳能电池片，所述太阳能电池片包括：基底，所述基底具有相对设置的第一表面和第二表面，所述第一表面包括间隔设置的第一区域和第二区域以及位于所述第一区域和所述第二区域之间的第三区域；第一掺杂层和第二掺杂层，所述第一掺杂层设置于所述第一区域的表面上或者至少部分嵌设于所述第一区域的表面内，所述第二掺杂层设置于所述第二区域的表面上或者至少部分嵌设于所述第二区域的表面内，所述第二掺杂层与所述第一掺杂层的极性相反；介质层和导电路径层，沿远离所述基底的方向，所述介质层和所述导电路径层依次叠置于所述第三区域，所述介质层阻隔所述第一掺杂层和所述第二掺杂层，所述导电路径层连接部分所述第一掺杂层和部分所述第二掺杂层。
可选地，沿所述电池片的厚度方向，所述介质层的厚度大于所述导电路径层的厚度。
可选地，沿所述电池片的厚度方向，所述导电路径层的厚度大于所述介质层的厚度。
可选地，所述介质层和所述导电路径层的基础材料相同；或者，所述介质层和所述导电路径层的基础材料不同。
可选地，所述导电路径层包括掺杂一种元素的层；和/或，所述导电路径层包括掺杂极性相反的两种元素的层。
可选地，所述导电路径层包括单一掺杂路径层和共掺杂路径层，其中，所述单一掺杂路径层叠置于所述介质层远离所述基底的一侧，所述共掺杂路径层叠置于所述单一掺杂路径层远离所述介质层的一侧；所述单一掺杂路径层内掺杂一种元素，所述共掺杂路径层内掺杂极性相反的两种元素。
可选地，所述单一掺杂路径层与所述共掺杂路径层的导电类型相同。
可选地，所述导电路径层的表面元素掺杂浓度大于或者等于所述第一掺杂层的表面元素掺杂浓度；和/或，所述导电路径层的表面元素掺杂浓度大于或者等于所述第二掺杂层的表面元素掺杂浓度。
可选地，沿所述电池片的厚度方向，所述导电路径层的厚度为d1，满足10nm≤d1≤120nm；和/或，所述导电路径层的元素掺杂浓度大于1E18cm-3且小于5E22cm-3。
可选地，所述介质层的元素掺杂浓度小于1E13cm-3；和/或，沿所述电池片的厚度方向，所述介质层的厚度为d2，满足20nm≤d2≤490nm。
可选地，与所述第三区域对应的所述基底内具有第三掺杂区域，所述第三掺杂区域的元素掺杂浓度小于1E13cm-3。
可选地，与所述第一区域对应的所述基底内具有第一掺杂区域，所述第一掺杂区域的元素掺杂浓度大于1E13cm-3；和/或，与所述第二区域对应的所述基底内具有第二掺杂区域，所述第二掺杂区域的元素掺杂浓度大于1E13cm-3。
可选地，所述第一掺杂层包括第一单掺层和第一共掺层，所述第一单掺层内掺杂一种元素，所述第一共掺层内掺杂极性相反的两种元素，其中，所述第一单掺层叠置于所述第一区域的表面上或者至少部分嵌入所述第一区域的表面内，所述第一共掺层叠置于所述第一单掺层远离所述基底的一侧，所述第一共掺层与所述第一单掺层的导电类型相反；所述太阳能电池片还包括第一电极，所述第一电极与所述基底的第一区域耦合，所述第一共掺层设置有贯穿槽，所述第一电极嵌设于所述贯穿槽内，且连接于所述第一单掺层或者所述基底的第一区域，所述第一电极与所述贯穿槽的内壁之间具有间隔。
可选地，所述第一单掺层内的元素掺杂浓度的均匀性优于所述第一共掺层内的元素掺杂浓度的均匀性。
可选地，所述第二掺杂层包括第二单掺层和第二共掺层，所述第二单掺层内掺杂一种元素，所述第二共掺层内掺杂极性相反的两种元素，其中，所述第二单掺层叠置于所述第二区域的表面上或者至少部分嵌设于所述第二区域的表面内，所述第二共掺层叠置于所述第二单掺层远离所述基底的一侧，所述第二共掺层与所述第二单掺层的导电类型相同。
可选地，沿所述电池片的厚度方向，所述第二共掺层的厚度大于所述第一掺杂层的第一共掺层的厚度，且所述第一共掺层的厚度大于或者等于所述导电路径层的共掺杂路径层的厚度，其中所述第一共掺层内掺杂极性相反的两种元素，并且所述共掺杂路径层内掺杂极性相反的两种元素。
可选地，所述第一掺杂层靠近所述导电路径层的一侧具有第一浓度渐变共掺区；和/或，所述第二掺杂层靠近所述导电路径层的一侧具有第二浓度渐变共掺区。
可选地，在所述第一掺杂层为P型掺杂层，所述第二掺杂层为N型掺杂层的情况下，所述第一浓度渐变共掺区的宽度大于所述第二浓度渐变共掺区的宽度。
可选地，所述导电路径层靠近所述第一掺杂层的一侧具有第一深度渐变共掺区，所述导电路径层靠近所述第二掺杂层的一侧具有第二深度渐变共掺区。
第二方面，本申请还公开了一种太阳能电池片的制备方法，所述方法包括：提供基底，所述基底具有相对设置的第一表面和第二表面，所述第一表面包括间隔设置的第一区域和第二区域以及位于所述第一区域和所述第二区域之间的第三区域；在所述第一区域的表面上或者所述第一区域的表面内形成第一掺杂层，在所述第二区域的表面上或者所述第二区域的表面内形成第二掺杂层，所述第一掺杂层与所述第二掺杂层的极性相反；沿远离所述基底的方向，在所述第三区域依次叠置介质层和导电路径层，以通过所述介质层阻隔所述第一掺杂层和所述第二掺杂层，通过所述导电路径层连接部分所述第一掺杂层和部分所述第二掺杂层。
可选地，所述在所述第一区域的表面上或者所述第一区域的表面内形成第一掺杂层，在所述第二区域的表面上或者所述第二区域的表面内形成第二掺杂层包括：在所述基底的第一表面上形成半导体层，在所述半导体层对应所述第一区域和所述第二区域的位置分别形成第一掺杂源层和第二掺杂源层；加热推进所述第一掺杂源层和所述第二掺杂源层，以使所述半导体层对应所述第一区域的部分形成所述第一掺杂层，所述半导体层对应所述第二区域的部分形成所述第二掺杂层，所述第一掺杂层和所述第二掺杂层的极性相反。
可选地，所述沿远离所述基底的方向，在所述第三区域依次叠置介质层和导电路径层包括：在所述基底的第一表面上形成半导体层，在所述半导体层对应所述第三区域的位置形成第三掺杂源层；加热推进所述第三掺杂源层，以使所述半导体层对应所述第三区域的部分沿远离所述基底的方向，依次形成叠置的所述介质层和所述导电路径层。
可选地，所述在所述第一区域的表面上或者所述第一区域的表面内形成第一掺杂层包括：在所述基底的第一表面上形成半导体层，在所述半导体层对应所述第一区域的位置形成第一掺杂源层；加热推进所述第一掺杂源层，以使所述半导体层对应所述第一区域的部分形成第一单掺层；在所述第一单掺层上形成第四掺杂源层；加热推进所述第四掺杂源层，以使所述第一单掺层在远离所述基底的一侧形成第一共掺层，所述第一单掺层和所述第一共掺层构成所述第一掺杂层；所述方法还包括：在所述第一共掺层上设置贯穿槽，将第一电极嵌设于所述贯穿槽内，并连接于所述第一单掺层或者所述基底的第一区域，所述第一电极与所述贯穿槽的内壁之间具有间隔。
第三方面，本申请还公开了一种光伏组件，该光伏组件包括第一方面所述的太阳能电池片。
本申请公开了一种太阳能电池片、太阳能电池片的制备方法及光伏组件，该太阳能电池片包括基底，所述基底具有相对设置的第一表面和第二表面，所述第一表面包括间隔设置的第一区域和第二区域以及位于所述第一区域和所述第二区域之间的第三区域；第一掺杂层和第二掺杂层，所述第一掺杂层设置于所述第一区域的表面上或者至少部分嵌设于所述第一区域的表面内，所述第二掺杂层设置于所述第二区域的表面上或者至少部分嵌设于所述第二区域的表面内，所述第二掺杂层与所述第一掺杂层的极性相反；介质层和导电路径层，沿远离所述基底的方向，所述介质层和所述导电路径层依次叠置于所述第三区域，所述介质层阻隔所述第一掺杂层和所述第二掺杂层，所述导电路径层连接部分所述第一掺杂层和部分所述第二掺杂层。
本申请中公开的太阳能电池片包括基底，基底的第一表面包括间隔设置的第一区域和第二区域以及位于第一区域和第二区域之间的第三区域。第一掺杂层设置于第一区域的表面上或者至少部分嵌设于第一区域的表面内，第二掺杂层设置于第二区域的表面上或者至少部分嵌设于第二区域的表面内，且第一掺杂层和第二掺杂层的极性相反，以通过第一掺杂层和第二掺杂层对基底产生的电流进行收集。
进一步地，沿远离基底的方向，将介质层和导电路径层依次叠置于第三区域，以通过介质层阻隔第一掺杂层和第二掺杂层，介质层还可以阻隔基底和导电路径层，避免太阳能电池片出现短路，保证太阳能电池片正常工作，提升太阳能电池片的光电转化效率。
另外，导电路径层连接部分第一掺杂层和部分第二掺杂层，导电路径层的设置可以实现第一掺杂层和第二掺杂层之间的软击穿，避免太阳能电池片被遮挡时出现热斑效应。并且，兼顾防热斑效应的同时，还可以保证太阳能电池片正常工作下的光电转化效率。
附图说明
图1表示本申请实施例中所述太阳能电池片的剖视图一；
图2表示本申请实施例中所述太阳能电池片的剖视图二；
图3表示本申请实施例中所述太阳能电池片的剖视图三；
图4表示本申请另一实施例中所述太阳能电池片的剖视图一；
图5表示本申请另一实施例中所述太阳能电池片的剖视图二；
图6表示本申请另一实施例中所述太阳能电池片的剖视图三；
图7表示本申请另一实施例中所述太阳能电池片的剖视图四；
图8表示本申请又一实施例中所述太阳能电池片的剖视图一；
图9表示本申请又一实施例中所述太阳能电池片的剖视图二；
图10表示本申请又一实施例中所述太阳能电池片的剖视图三；
图11表示本申请又一实施例中所述太阳能电池片的剖视图四；
图12表示本申请实施例中所述太阳能电池片制备方法的流程图。
附图标记：
100：基底；
101：第一掺杂层；1011：第一单掺层；1012：第一共掺层；1012a：贯穿槽；
102：第二掺杂层；1021：第二单掺层；1022：第二共掺层；
1031：介质层；1032：导电路径层；1032a：单一掺杂路径层；1032b：共掺杂路径层；
1032c：第一深度渐变共掺区；
104：界面钝化层；
105：表面钝化层或减反射层；
106：第一电极；
107：第二电极；
108：第二浓度渐变共掺区。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请的范围。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。
参照图1，示出了本申请实施例中所述太阳能电池片的剖视图一；参照图2，示出了本申请实施例中所述太阳能电池片的剖视图二；参照图3，示出了本申请实施例中所述太阳能电池片的剖视图三；参照图4，示出了本申请另一实施例中所述太阳能电池片的剖视图一；参照图5，示出了本申请另一实施例中所述太阳能电池片的剖视图二；参照图6，示出了本申请另一实施例中所述太阳能电池片的剖视图三；参照图7，示出了本申请另一实施例中所述太阳能电池片的剖视图四；参照图8，示出了本申请又一实施例中所述太阳能电池片的剖视图一；参照图9，示出了本申请又一实施例中所述太阳能电池片的剖视图二；参照图10，示出了本申请又一实施例中所述太阳能电池片的剖视图三；参照图11，本申请又一实施例中所述太阳能电池片的剖视图四。
如图1至图11所示，本申请实施例公开了一种太阳能电池片，该太阳能电池片包括基底100，基底100具有相对设置的第一表面和第二表面，第一表面包括间隔设置的第一区域和第二区域以及位于第一区域和第二区域之间的第三区域；第一掺杂层101和第二掺杂层102，第一掺杂层101设置于第一区域的表面上或者至少部分嵌设于第一区域的表面内，第二掺杂层102设置于第二区域的表面上或者至少部分嵌设于第二区域的表面内，第二掺杂层102与第一掺杂层101的极性相反；介质层1031和导电路径层1032，沿远离基底100的方向，介质层1031和导电路径层1032依次叠置于第三区域，介质层1031阻隔第一掺杂层101和第二掺杂层102，导电路径层1032连接部分第一掺杂层101和部分第二掺杂层102。
太阳能电池片是光伏组件的核心部件，其可以将太阳能转化为电能。如图1至图11所示，本申请实施例公开了一种太阳能电池片，该太阳能电池片可以用于光伏组件中，以避免光伏组件被遮挡时，太阳能电池片出现热斑效应，影响光伏组件的光电转化效率。
如图1至图11所示，本申请实施例中公开的太阳能电池片包括基底100，基底100作为太阳能电池片的核心部件，其可以将太阳能转化为电能。示例性地，基底100可以为P型基底、N型基底或者本征导电类型的硅片。晶体类型可以是单晶，也可以是多晶等。当然，基底100也可以为其他类型的基底100。在此，对于基底100的具体类型不做过多的限制，在实际的应用中，技术人员可以根据需要选择合适的材质，作为基底100。
本申请实施例中的基底100具有相对设置的第一表面和第二表面，其中，第一表面为电池片的背面，第二表面为电池片的正面。也就是说，本申请实施例公开的太阳能电池片为背接触式太阳能电池片。
如图1至图11所示，基底100的第一表面包括间隔设置的第一区域和第二区域以及位于第一区域和第二区域之间的第三区域。第一掺杂层101设置于第一区域的表面上或者至少部分嵌设于第一区域的表面内，第二掺杂层102设置于第二区域的表面上或者至少部分嵌设于第二区域的表面内，第二掺杂层102与第一掺杂层101的极性相反，以通过第一掺杂层101和第二掺杂层102对基底100产生的电流进行收集。
需要说明的是，第一掺杂层101和第二掺杂层102均可以为多晶硅、非晶硅、微晶硅、单晶硅中的一种或者多种。在第一掺杂层101为P型掺杂层的情况下，第二掺杂层102为N型掺杂层。在第一掺杂层101为N型掺杂层的情况下，第二掺杂层102为P型掺杂层。其中，P型一般掺杂有IIIA族元素，N型一般掺杂有VA族元素。
如图1至图11所示，沿远离基底100的方向，介质层1031和导电路径层1032依次叠置于第三区域。通过介质层1031阻隔第一掺杂层101和第二掺杂层102，介质层1031还可以阻隔基底100和导电路径层1032，以避免太阳能电池片出现短路现象，保证太阳能电池片正常工作，提升太阳能电池片的光电转化效率。
需要说明的是，本申请实施例中的介质层1031包括半导体层和/或绝缘层。当介质层1031包括半导体层和绝缘层时，沿远离基底100的方向，绝缘层和半导体层依次叠置于第三区域的表面上。导电路径层1032叠置于半导体层远离绝缘层的一侧。半导体层包括本征半导体层和呈电中性的共掺半导体层，其中，本征半导体层包括本征非晶硅、本征多晶硅、本征单晶硅等中的至少一种。呈电中性的共掺半导体层是指元素掺杂浓度不超过1E18cm-3，表现出绝对的电中性、呈微弱的正电或者呈微弱的负电的共掺半导体层，示例性地，呈电中性的共掺半导体层为同时掺杂磷元素和硼元素的多晶硅层。
如图1至图11所示，本申请实施例中，在介质层1031远离基底100的一侧叠置导电路径层1032，导电路径层1032连接部分第一掺杂层101和部分第二掺杂层102，通过导电路径层1032导通第一掺杂层101和第二掺杂层102。导电路径层1032的设置，可以实现第一掺杂层101和第二掺杂层102的软击穿，避免太阳能电池片被遮挡时出现热斑效应。并且，上述设置，在兼顾热斑效应的同时，还可以保证太阳能电池片正常工作下的光电转化效率。
可选地，沿电池片的厚度方向，介质层1031的厚度大于导电路径层1032的厚度。
本申请实施例中，沿太阳能电池片的厚度方向，将介质层1031的厚度设置为大于导电路径层1032的厚度。通过上述设置，使得介质层1031的厚度较厚，介质层1031能够保证第一掺杂层101和第二掺杂层102之间的电隔离，以及基底100和导电路径层1032之间的电隔离，使得太阳能电池片正常工作状态下，光电转化效率更高。
本申请实施例中的导电路径层1032相较于介质层1031更薄，通过导电路径层1032实现第一掺杂层101和第二掺杂层102之间的软击穿。当太阳能电池片被遮挡时，导电路径层1032可以起到防热斑的作用，避免太阳能电池片出现热斑效应。
并且，上述设置，可以在太阳能电池片的整个面积上的第一掺杂层101和第二掺杂层102之间设置介质层1031，实现整个面积上的防热斑，从而省去制备其他空间间隔槽的步骤和工艺，使太阳能电池片的制备工艺更为简单，降低太阳能电池片的生产成本。
可选地，沿电池片的厚度方向，导电路径层1032的厚度大于介质层1031的厚度。
本申请实施例中，沿电池片的厚度方向，将导电路径层1032的厚度设置为大于介质层1031的厚度，以增加导电通路，在整个电池片面积上仅需要较少的防热斑结构，就可以实现整个电池片的防热斑效果。
具体地，可以在基底100第一表面的至少一个第三区域的整个面积上依次叠置介质层1031和导电路径层1032，也可以在基底100第一表面的至少一个第三区域的至少部分面积上依次叠置介质层1031和导电路径层1032。
需要说明的是，位于基底100第一表面的多个第三区域上的不同的导电路径层1032的位置可以相互对应，也可以相互交错。对此，本申请不做具体的限定。在实际的应用中，技术人员可以根据需要进行设置。
可选地，介质层1031和导电路径层1032的基础材料相同。
本申请实施例中的介质层1031和导电路径层1032的基础材料相同。示例性地，介质层1031和导电路径层1032均包括多晶硅，经过掺杂的多晶硅形成导电路径层1032，未经掺杂的多晶硅形成介质层1031。其中，未经掺杂的多晶硅也可以称之为本征多晶硅。当然，上述具体实施例仅为本申请的个别举例，不作为本申请的限制，在实际的应用中，技术人员可以根据需要设置介质层1031和导电路径层1032的基础材料。
需要说明的是，本申请实施例中的介质层1031和导电路径层1032的基础材料与第一掺杂层101和第二掺杂层102的基础材料也相同。通过上述设置，可以简化电池片的制备流程，也即电池片图形化的流程，通过一次沉积半导体膜层，分别进行不同程度的掺杂，即可形成上述结构。
可选地，介质层1031和导电路径层1032的基础材料不同。
本申请实施例中的介质层1031和导电路径层1032的基础材料也可以不同。介质层1031也可以为绝缘层，示例性地，介质层1031可以为氧化硅层、氮化硅层、氮氧化硅层、氧化铝层、碳化硅层、本征非晶硅层、本征多晶硅层、本征单晶硅层等中的至少一种。导电路径层1032可以为掺杂非晶硅层、掺杂多晶硅层、掺杂单晶硅层等中的至少一种。
可选地，导电路径层1032包括掺杂一种元素的层；和/或，导电路径层1032包括掺杂极性相反的两种元素的层。
本申请实施例中的导电路径层1032内可以掺杂一种元素，以提升导电路径层1032的导电效果，实现第一掺杂层101和第二掺杂层102的软击穿，避免太阳能电池片被遮挡时出现热斑效应。示例性地，导电路径层1032内仅掺杂硼元素，或者，导电路径层1032内仅掺杂磷元素。
当然，导电路径层1032内也可以掺杂极性相反的两种元素，以简化电池片的制备流程，便于电池片的制备，降低电池片的制备成本。示例性地，导电路径层1032内既掺杂硼元素，也掺杂磷元素。
需要说明的是，在导电路径层1032内掺杂一种元素的情况下，沿导电路径层1032至基底100的方向，导电路径层1032内掺杂元素的浓度递减。
可选地，如图2所示，本申请实施例中的导电路径层1032包括单一掺杂路径层1032a和共掺杂路径层1032b，其中，单一掺杂路径层1032a叠置于介质层1031远离基底100的一侧，共掺杂路径层1032b叠置于单一掺杂路径层1032a远离介质层1031的一侧；单一掺杂路径层1032a内掺杂一种元素，共掺杂路径层1032b内掺杂极性相反的两种元素。
如图2所示，本申请实施例中将导电路径层1032设置成两层，其中一层为单一掺杂路径层1032a，单一掺杂路径层1032a叠置于介质层1031远离基底100的一侧，单一掺杂路径层1032a内掺杂一种元素。其中另一层为共掺杂路径层1032b，共掺杂路径层1032b叠置于单一掺杂路径层1032a远离介质层1031的一侧，共掺杂路径层1032b内掺杂极性相反的两种元素。上述两种元素中的一种与单一掺杂路径层1032a内的掺杂元素相同。
通过上述设置，能够降低电池片的工艺难度，简化电池片的制备流程，降低电池片的生产成本。进一步地，上述设置，也可以避免电池片被遮挡时出现热斑效应。并且，在兼顾防热斑效应的同时，还可以保证电池片正常工作下的光电转化效率。
可选地，单一掺杂路径层1032a与共掺杂路径层1032b的导电类型相同。
本申请实施例中，将单一掺杂路径层1032a的导电类型设置为与共掺杂路径层1032b的导电类型相同，以使第一掺杂层101和第二掺杂层102之间的软击穿界面更统一，防热斑效果更好。
进一步地，将单一掺杂路径层1032a的导电类型设置为与共掺杂路径层1032b的导电类型相同，还可以防止软击穿层过厚，导致电池片的效率损失。
可选地，导电路径层1032的表面元素掺杂浓度大于或者等于第一掺杂层101的表面元素掺杂浓度；和/或，导电路径层1032的表面元素掺杂浓度大于或者等于第二掺杂层102的表面元素掺杂浓度。
本申请实施例中，将导电路径层1032的表面元素掺杂浓度设置为大于或者等于第一掺杂层101的表面元素的掺杂浓度；和/或，将导电路径层1032的表面元素掺杂浓度设置为大于或者等于第二掺杂层102的表面元素掺杂浓度。
通过上述设置，可以控制导电路径层1032的表面元素掺杂浓度，使导电路径层1032可以制作的更薄，从而提升电池片防热斑的效果，并且也可以保证电池片的光电转化效率。
可选地，沿电池片的厚度方向，导电路径层1032的厚度为d1，满足10nm≤d1≤120nm；和/或，导电路径层1032的元素掺杂浓度大于1E18cm-3且小于5E22cm-3。
本申请实施例中，沿电池片的厚度方向，将导电路径层1032的厚度设置为d1。其中，d1大于或者等于10nm且小于或者等于120nm。通过对导电路径层1032厚度的设置，使得导电路径层1032的厚度较薄，从而保证电池片软击穿的效果。
示例性地，沿电池片的厚度方向，导电路径层1032的厚度可以为10nm、20nm、30nm、40nm、50nm、60nm、70nm、80nm、90nm、100nm、110nm、120nm等。
本申请实施例中，导电路径层1032内元素的掺杂浓度大于或者等于1E18cm-3且小于5E22cm-3。通过将导电路径层1032内元素的掺杂浓度设置为大于或者等于1E18cm-3且小于5E22cm-3，以使导电路径层1032可以导电，达到电池片的软击穿效果。
示例性地，导电路径层1032内元素掺杂浓度可以为1E18cm-3、1E20cm-3、2E18cm-3、3E18cm-3、4E18cm-3、5E18cm-3、5E22cm-3等。
可选地，介质层1031的元素掺杂浓度小于1E13cm-3；和/或，沿电池片的厚度方向，介质层1031的厚度为d2，满足20nm≤d2≤490nm。
本申请实施例中，将介质层1031内元素的掺杂浓度设置为小于1E13cm-3，以使介质层1031具有绝缘性。通过介质层1031可以阻隔第一掺杂层101和第二掺杂层102，以及基底100和导电路径层1032，实现第一掺杂层101和第二掺杂层102之间的电隔离，以及基底100和导电路径层1032之间的电隔离。
示例性地，介质层1031内元素的掺杂浓度可以为1E12cm-3、1E11cm-3、1E10cm-3、1E9cm-3等。
本申请实施例中，沿电池片的厚度方向，将介质层1031的厚度设置为d2，其中，d2大于或者等于20nm且小于或者等于490nm，以通过介质层1031阻隔第一掺杂层101和第二掺杂层102，以及基底100和导电路径层1032，实现第一掺杂层101和第二掺杂层102之间的电隔离，以及基底100和导电路径层1032之间的电隔离。
示例性地，沿电池片的厚度方向，介质层1031的厚度可以为20nm、50nm、100nm、150nm、200nm、250nm、300nm、350nm、400nm、450nm、490nm等。
可选地，与第三区域对应的基底100内具有第三掺杂区域，第三掺杂区域的元素掺杂浓度小于1E13cm-3。
本申请实施例中的基底100与第三区域对应的位置具有第三掺杂区域，将第三掺杂区域内元素的掺杂浓度设置为小于1E13cm-3。导电路径层1032与基底100的第三掺杂区域之间设置有介质层1031，介质层1031可以阻隔导电路径层1032和基底100的第三掺杂区域，避免导电路径层1032内的掺杂元素扩散至基底100的第三掺杂区域内，以保证电池片正常工作状态下，具有更高的光电转化效率。
示例性地，基底100的第三掺杂区域内元素的掺杂浓度可以为1E12cm-3、1E11cm-3、1E10cm-3、1E9cm-3、1E8cm-3等。
可选地，与第一区域对应的基底100内具有第一掺杂区域，第一掺杂区域的元素掺杂浓度大于1E13cm-3；和/或，与第二区域对应的基底100内具有第二掺杂区域，第二掺杂区域的元素掺杂浓度大于1E13cm-3。
本申请实施例中的基底100与第一区域对应的位置具有第一掺杂区域，与第二区域对应的位置具有第二掺杂区域，而第三掺杂区域位于第一掺杂区域和第二掺杂区域之间。
本申请实施例中，将第一掺杂区域内元素的掺杂浓度设置为大于1E13cm-3，和/或，将第二掺杂区域内元素的掺杂浓度也设置为大于1E13cm-3。并且，第一掺杂区域和第二掺杂区域在基底100中的内扩深度不同。通过上述设置，以匹配不同掺杂元素的固溶度，使第一掺杂层101和第二掺杂层102实现有效掺杂，实现载流子的充分分离。
示例性地，以掺杂元素为硼元素和磷元素为例，硼元素在基底100中的内扩深度更深，而磷元素在基底100中的内扩深度相对较浅。本申请中，硼内扩深度是以E17cm-3截止，磷内扩深度是以E18cm-3截止。
可选地，如图6、图7、图9至图11所示，本申请实施例中的第一掺杂层101包括第一单掺层1011和第一共掺层1012，第一共掺层1012内掺杂极性相反的两种元素，其中，第一单掺层1011叠置于第一区域的表面上或者至少部分嵌入第一区域的表面内，第一共掺层1012叠置于第一单掺层1011远离基底100的一侧，第一共掺层1012与第一单掺层1011的导电类型相反；太阳能电池片还包括第一电极106，第一电极106与基底100的第一区域耦合，第一共掺层1012设置有贯穿槽1012a，第一电极106嵌设于贯穿槽1012a内，且连接于第一单掺层1011或者基底100的第一区域，第一电极106与贯穿槽1012a的内壁之间具有间隔。
如图6、图7、图9至图11所示，本申请实施例中，将第一掺杂层101设置成两层，其中一层为第一单掺层1011，另一层为第一共掺层1012，第一单掺层1011和第一共掺层1012的导电类型相反。第一单掺层1011内掺杂一种元素，第一单掺层1011叠置于第一区域的表面上或者至少部分嵌设于第一区域的表面内。第一共掺层1012内掺杂有极性相反的两种元素，第一共掺层1012叠置于第一单掺层1011远离基底100的一侧。通过上述设置，可以降低电池片的工艺难度，简化电池片的工艺流程，降低电池片的制造成本。
本申请实施例中公开的电池片还包括第一电极106，第一电极106与基底100的第一区域耦合，以对基底100第一区域产生的载流子进行收集。具体地，如图4所示，第一电极106可以嵌设于表面钝化层或减反射层105内，并连接于第一共掺层1012。如图5所示，第一电极106也可以嵌设于表面钝化层或减反射层105和第一共掺层1012内，并将第一电极106的一端连接于第一单掺层1011与第一区域对应的位置。如图6所示，也可以将第一电极106嵌设于表面钝化层或减反射层105、第一共掺层1012和第一单掺层1011内，并将第一电极106的一端连接于隧穿钝化层或基底100的第一区域表面。通过上述设置，使得第一电极106可以对基底100第一区域产生的载流子进行收集。
如图9至图11所示，在本申请实施例中，还可以在第一共掺层1012上设置贯穿槽1012a，将第一电极106的一端穿过贯穿槽1012a连接于第一单掺层1011与第一区域对应的位置或者将第一电极106的一端直接连接于隧穿钝化层或基底100的第一区域表面，第一电极106的侧壁与贯穿槽1012a的内壁之间具有间隔，以降低电池片漏电的风险，提升电池片的光电转化效率。
需要说明的是，本申请实施例中第二电极107的设置，与第一电极106的设置类似，在此，不再赘述。
可选地，第一单掺层1011内元素掺杂浓度的均匀性优于第一共掺层1012内元素掺杂浓度的均匀性。
在本申请实施例中，以第一单掺层1011为第一导电类型，第一共掺层1012为第二导电类型为例，进行相关的说明。可以理解，第一单掺层1011内仅掺杂一类元素，而第一共掺层1012内既掺杂一类元素，还掺杂二类元素。其中，一类元素可以为IIIA组元素，例如硼元素、铝元素、镓元素等。二类元素可以为VA组元素，例如磷元素、锑元素、砷元素等。第一单掺层1011的厚度大于或者等于20nm且小于或者等于490nm，第一共掺层1012的厚度大于或者等于10nm且小于或者等于480nm。
第一共掺层1012中，沿远离基底100的方向，一类元素的掺杂浓度分布基本在同一个数量级，浓度的均匀度小于50％。第一单掺层1011中，沿远离基底100的方向，一类元素的掺杂浓度几乎呈均匀分布，浓度均匀度小于20％。第一共掺层1012和第一单掺层1011中一类元素的掺杂浓度基本在同一个数量级。
需要说明的是，本申请实施例中的浓度的均匀度＝(浓度最大值-浓度最小值)/(浓度最大值+浓度最小值)。
示例性地，本申请实施例中，第一单掺层1011中，一类元素的掺杂浓度范围为1E16cm-3至1E21cm-3。第一共掺层1012中，一类元素的掺杂浓度范围为1E16cm-3至1E21cm-3，二类元素的掺杂浓度范围为1E17cm-3至1E22cm-3。
在同一区域中，测试第一单掺层1011中不同深度硼元素的掺杂浓度，第一单掺层1011中，靠近基底100的位置，硼元素的掺杂浓度为6E19cm-3，远离基底100的位置，硼元素的掺杂浓度为7E19cm-3，浓度均为度＝(7-6)/(7+6)＝7.7％，小于20％。
在同一区域中，测试第一共掺层1012中不同深度硼元素的掺杂浓度，第一共掺层1012中，靠近基底100的位置，硼元素的掺杂浓度为7E19cm-3，远离基底100的位置，硼元素的掺杂浓度为3E19cm-3，浓度均为度＝(7-3)/(7+3)＝40％，小于50％。
在本申请实施例中，将第一单掺层1011内元素掺杂浓度的均匀性设置为优于第一共掺层1012内元素掺杂浓度的均匀性。通过上述设置，可以保证第一单掺层1011内载流子的分离效率。进一步地，通过上述设置，还可以保证第一单掺层1011不会影响基底100的钝化效果。
可选地，如图8至图11所示，本申请实施例中的第二掺杂层102包括第二单掺层1021和第二共掺层1022，第二共掺层1022内掺杂极性相反的两种元素，第二单掺层1021叠置于第二区域的表面上或者至少部分嵌设于第二区域的表面内，第二共掺层1022叠置于第二单掺层1021远离基底100的一侧，第二共掺层1022与第二单掺层1021的导电类型相同。
如图8至图11所示，本申请实施例中的第二掺杂层102包括两层，其中一层为第二单掺层1021，第二单掺层1021内掺杂一种元素。其中另一层为第二共掺层1022，第二共掺层1022内掺杂极性相反的两种元素。其中，第二单掺层1021和第二共掺层1022的导电类型相同。
如图8至图11所示，第二单掺层1021叠置于第二区域的表面上或者至少部分嵌设于第二区域的表面内，第二共掺层1022叠置于第二单掺层1021远离基底100的一侧。通过上述设置，可以降低电池片的工艺难度，简化电池片的工艺流程，降低电池片的制造成本。
需要说明的是，本申请实施例中，无论第二单掺层1021和第二共掺层1022的导电类型相同还是导电类型不同。第二电极107可以单独和第二单掺层1021接触，也可以单独和第二共掺层1022接触，当然，第二电极107也可以和第二单掺层1021和第二共掺层1022同时接触，当第二电极107与第二单掺层1021和第二共掺层1022同时接触时，形成的接触更好，太阳能电池片的可靠性更高。
可选地，沿电池片的厚度方向，第二共掺层1022的厚度大于第一共掺层1012的厚度，且第一共掺层1012的厚度大于或者等于共掺杂路径层1032b的厚度。
沿电池片的厚度方向，共掺杂路径层1032b的厚度不能太厚，以保证电池片防热斑的效果，以及电池片的光电转化效率。第二共掺层1022不会影响第二掺杂层102的导电类型，因此，第二共掺层1022的厚度可以较厚，而第一共掺层1012的厚度不能太厚，第一共掺层1012的厚度过厚，会影响第一区域载流子的收集效率。当然，第一共掺层1012的厚度也不能太薄，第一共掺层1012的厚度过薄，会增加电池片的工艺步骤，需要单独处理以形成共掺杂路径层1032b，增加电池片的制造成本。
基于上述，本申请实施例中，沿电池片的厚度方向，将第二共掺层1022的厚度设置为大于第一共掺层1012的厚度，并将第一共掺层1012的厚度设置为大于或者等于共掺杂路径层1032b的厚度。
可选地，如图3所示，本申请实施例中第一掺杂层101靠近导电路径层1032的一侧具有第一浓度渐变共掺区(图中未示出)；和/或，第二掺杂层102靠近导电路径层1032的一侧具有第二浓度渐变共掺区108。
如图3所示，第一掺杂层101内靠近第一电极106的区域元素掺杂浓度较高，以利于载流子的收集，以及电流的传输和收集。尤其是，第一掺杂层101内位于第一电极106下方的元素掺杂浓度更高，以有效降低金属半导体接触电阻，而第一掺杂层101靠近导电路径层1032的一侧，元素掺杂浓度较低，有利于俄歇复合，从而提升电池片的光电转化效率。
基于上述，本申请实施例中，在第一掺杂层101靠近导电路径层1032的一侧设置第一浓度渐变共掺区，和/或，在第二掺杂层102靠近导电路径层1032的一侧设置第二浓度渐变共掺区108，以提升电池片电流收集效率，提升电池片的光电转化效率。
可选地，在第一掺杂层101为P型掺杂层，第二掺杂层102为N型掺杂层的情况下，第一浓度渐变共掺区的宽度大于第二浓度渐变共掺区108的宽度。
在第一掺杂层101为P型掺杂层，也即第一掺杂层101内掺杂硼元素，第二掺杂层102为N型掺杂层，也即第二掺杂层102内掺杂磷元素的情况下，第一浓度渐变共掺区的宽度大于第二浓度渐变共掺区108的宽度。
通过上述设置，可以在不增加工艺难度的情况下，提高载流子传输效率，以及电流的传输和收集效率，并且，降低金属半导体接触。
当然，以上将第一掺杂层101设置为P型掺杂层，将第二掺杂层102设置为N型掺杂层的方式，仅为本申请的个别举例，不作为本申请的限制。在实际的应用中，技术人员可以根据需要设置第一掺杂层101和第二掺杂层102的具体掺杂类型。
可选地，导电路径层1032靠近第一掺杂层101的一侧具有第一深度渐变共掺区1032c，导电路径层1032靠近第二掺杂层102的一侧具有第二深度渐变共掺区(图中未示出)。
本申请实施例中，在导电路径层1032靠近第一掺杂层101的一侧设置第一深度渐变共掺区1032c，在导电路径层1032靠近第二掺杂层102的一侧设置第二深度渐变共掺区，以提高软击穿通路的作用深度，减少第一掺杂层101和第二掺杂层102发热电流区域的过分集中。进一步地，还可以降低单个或单点软击穿发热温度，减少安全风险。
对本申请实施例中公开的太阳能电池片进行发热测试。发热测试标准为：施加反向偏压15V，持续100ms时间，测试电池片的前后温差，使用加电流后温度变化高点的温度为标准△T/℃。发热测试结果如下表1所示。
需要说明的是，对比例中，太阳能电池仅通过空间间隔阻隔第一掺杂层101和第二掺杂层102，不设置导电路径层1032和介质层1031。实施例1，如图1至图3所示，太阳能电池包括的第一掺杂层101和第二掺杂层102通过介质层1031以及导电路径层1032连接。实施例2，如图4至图7所示，太阳能电池包括的第一掺杂层101、第二掺杂层102通过介质层1031以及导电路径层1032连接。其中，第一掺杂层101包括第一单掺层1011和第一共掺层1012。实施例3，如图8至图11所示，太阳能电池包括的第一掺杂层101、第二掺杂层102通过介质层1031以及导电路径层1032连接。其中，第一掺杂层101包括第一单掺层1011和第一共掺层1012，第二掺杂层102包括第二单掺层1021和第二共掺层1022。
表1太阳能电池片发热测试结果
由表1中测试结果可知，相较于对比例公开的太阳能电池片，本申请实施例1、实施例2和实施例3中公开的太阳能电池片热斑测试温度更低，超过3℃的电池片比例更低，防热斑效应更优。实施例2和实施例3中公开的具有共掺层的太阳能电池片的光电转换效率略有提升。
参照图12，示出了本申请实施例中所述电池片制备方法的流程图。
如图12所示，本申请实施例中公开了一种电池片的制备方法，该方法包括：
201，提供基底，基底具有相对设置的第一表面和第二表面，第一表面包括间隔设置的第一区域和第二区域以及位于第一区域和第二区域之间的第三区域。
本申请实施例中的基底作为太阳能电池片的核心部件，其可以将太阳能转化为电能。示例性地，基底可以为P型基底、N型基底或者本征导电类型的硅片。晶体类型可以是单晶，也可以是多晶等。当然，基底也可以为其他类型的基底，在此，对于基底的具体类型不做过多的限制，在实际的应用中，技术人员可以根据需要选择合适的材质，作为基底。
需要说明的是，本申请实施例中，在提供基底之前，需要对基底进行表面处理。表面处理包括去伤损、去污渍、抛光以及制绒处理等步骤。本申请实施例中的基底具有相对设置的第一表面和第二表面，其中，第一表面为电池片的背面，第二表面为电池片的正面。
也就是说，本申请实施例公开的太阳能电池片为背接触式太阳能电池片。其中，基底的第一表面具有间隔设置的第一区域和第二区域以及位于第一区域和第二区域之间的第三区域。
202，在第一区域的表面上或者第一区域的表面内形成第一掺杂层，在第二区域的表面上或者第二区域的表面内形成第二掺杂层，第一掺杂层与第二掺杂层的极性相反。
需要说明的是，第一掺杂层101和第二掺杂层102均可以为多晶硅、非晶硅、微晶硅中的一种或者多种。在第一掺杂层101为P型掺杂层的情况下，第二掺杂层102为N型掺杂层。在第一掺杂层101为N型掺杂层的情况下，第二掺杂层102为P型掺杂层。其中，P型一般掺杂有IIIA族元素，N型一般掺杂有VA族元素。
在本申请实施例中，对于第一掺杂层101和第二掺杂层102的形成顺序不做具体的限制。可以先形成第一掺杂层101，后形成第二掺杂层102。也可以先形成第二掺杂层102，后形成第一掺杂层101。在实际的应用中，技术人员可以根据需要进行选择。
具体地，所述在第一区域的表面上或者第一区域的表面内形成第一掺杂层，在第二区域的表面上或者第二区域的表面内形成第二掺杂层包括：在基底的第一表面上形成半导体层，在半导体层对应第一区域和第二区域的位置分别形成第一掺杂源层和第二掺杂源层。加热推进第一掺杂源层和第二掺杂源层，以使半导体层对应第一区域的部分形成第一掺杂层，半导体层对应第二区域的部分形成第二掺杂层，第一掺杂层和第二掺杂层的极性相反。
需要说明的是，本申请实施例中，可以采用激光加热推进的方式，在第一掺杂源层和第二掺杂源层内掺杂元素，以形成第一掺杂层和第二掺杂层。当然，以上采用激光加热推进的方式仅为本申请实施例的个别举例，不作为本申请的限制。在实际的应用中，技术人员可以根据需要选择合适的掺杂方式。
本申请实施例中，对于第一掺杂源层和第二掺杂源层的具体形成顺序以及第一掺杂源层和第二掺杂源层的加热推进顺序均不做具体的限制。示例性地，本申请实施例中，可以先形成第一掺杂源层，加热推进第一掺杂源层，再形成第二掺杂源层，然后，加热推进第二掺杂源层。也可以先形成第二掺杂源层，再形成第一掺杂源层，再依次加热推进第一掺杂源层和第二掺杂源层。
需要说明的是，本申请实施例中，在基底的第一表面上形成半导体层之前，可以在基底的第一表面先形成界面钝化层104，以保护基底。本申请实施例中的界面钝化层104可以是单层结构，也可以是多层结构。界面钝化层104包括氮化硅层、氧化硅层、氮氧化硅层、氧化铝层、碳化硅层、非晶硅层中的一种或多种。
具体地，在第一区域的表面上或者第一区域的表面内形成第一掺杂层包括：
在基底的第一表面上形成半导体层，在半导体层对应第一区域的位置形成第一掺杂源层；加热推进第一掺杂源层，以使半导体层对应第一区域的部分形成第一单掺层；在第一单掺层上形成第四掺杂源层；加热推进第四掺杂源层，以使第一单掺层在远离基底的一侧形成第一共掺层，第一单掺层和第一共掺层构成所述第一掺杂层。本申请中第四掺杂源层和第二掺杂源层可以是同一层。
通过上述方式制备第一掺杂层，第一掺杂层包括第一单掺层和第一共掺层，可以降低电池片的工艺难度，简化电池片的工艺流程，降低电池片的制造成本。
当然，也可以采用上述方式，在第二区域的表面上或者第二区域的表面内形成第二掺杂层。在此，不再赘述。
在加热推进第四掺杂源层，以使第一单掺层在远离基底的部分形成第一共掺层之后，所述方法还包括：
在第一共掺层上设置贯穿槽，将第一电极嵌设于贯穿槽内，并连接于第一单掺层或者基底的第一区域，第一电极与贯穿槽的内壁之间具有间隔。
本申请实施例中，在第一共掺层内设置贯穿槽，将第一电极嵌设于贯穿槽内，并将第一电极的一端连接于第一单掺层或者基底的第一区域，以通过第一电极对基底第一区域产生的载流子进行收集。
需要说明的是，在本申请实施例中，第一电极的侧壁与贯穿槽的内壁之间具有间隔，以降低电池片漏电的风险，提升电池片的光电转化效率。
203，沿远离基底的方向，在第三区域依次叠置介质层和导电路径层，以通过介质层阻隔第一掺杂层和第二掺杂层，通过导电路径层连接部分第一掺杂层和部分第二掺杂层。
采用本申请实施例公开的太阳能电池片的制备方法制备太阳能电池片，沿远离基底的方向，介质层和导电路径层依次叠置于第三区域，以通过介质层阻隔第一掺杂层和第二掺杂层，介质层还可以阻隔基底和导电路径层，避免太阳能电池片短路，保证太阳能电池片正常工作，提升太阳能电池片的光电转化效率。
进一步地，通过导电路径层连接部分第一掺杂层和部分第二掺杂层，导电路径层可以实现第一掺杂层和第二掺杂层之间的软击穿，避免太阳能电池片被遮挡时出现热斑效应，并且，兼顾防热斑效应的同时，还可以保证电池片正常工作下的光电转化效率。
具体地，沿远离基底的方向，在第三区域依次叠置介质层和导电路径层包括：
在基底的第一表面上形成半导体层，在半导体层对应第三区域的位置形成第三掺杂源层；加热推进第三掺杂源层，以使半导体层对应第三区域的部分沿远离基底的方向，依次形成叠置的介质层和导电路径层。
本申请实施例公开的电池片的制备方法，形成第一掺杂层、第二掺杂层、介质层和导电路径层之后，所述方法还包括：
去除电池片表面残余的各类掺杂源，对电池片进行清洗处理，以清洁电池片的表面。还需要对电池片表面进行刻蚀等修饰步骤。通过刻蚀修饰步骤，可以将各个区域表面掺杂元素进行修饰，去除掺杂浓度过高的表面或者掺杂浓度过低的表面。掺杂浓度过高的表面，会带来俄歇复合区，掺杂浓度过低的表面，不利于后续表面金属和电极的接触。通过上述处理，能够使电池片的性能更优。
沿远离基底的方向，在第三区域依次叠置介质层和导电路径层之后，所述方法还包括：
在第一掺杂层、第二掺杂层和导电路径层远离基底的一侧形成表面钝化层；在表面钝化层内形成第一电极和第二电极，第一电极电连接于第一掺杂层，第二电极电连接于第二掺杂层，以通过第一电极收集第一掺杂层内的载流子，并对第一掺杂层收集的电流进行传输，通过第二电极收集第二掺杂层内的载流子，并对第二掺杂层收集的电流进行传输。
作为一种优选地实施方式，在表面钝化的过程中，可以同时在第一掺杂层远离基底的一侧、第二掺杂层远离基底的一侧和导电路径层远离基底的一侧形成表面钝化层或减反射层。以使与第一区域、第二区域和第三区域对应的表面钝化层或减反射层的结构完全相同。
需要说明的是，本申请实施例中的表面钝化层或减反射层可以是单层结构，也可以是多层结构。表面钝化层或减反射层包括氮化硅层、氧化硅层、氮氧化硅层、氧化铝层、碳化硅层、非晶硅层、透明导电氧化层(TCO，Transparent Conductive Oxide)中的一种或多种。在制备表面钝化层或者减反射层的过程中，可以采用原子层沉积法(ALD，Atomic Layer Deposition)、化学气相沉积法，例如，等离子体增强化学气相沉积法(PECVD、Plasma Enhanced Chemical Vapor Deposition)、常压化学气相淀积法(APCVD，Atmospheric Pressure Chemical Vapor Deposition)、低压力化学气相沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)、金属有机化学气相沉积法(MOCVD，Metal-Organic Chemical Vapor Deposition)等、物理气相沉积法，例如，蒸发、溅射等方法制备表面钝化层或减反射层。
例如，在制备表面钝化层或减反射层的过程中，可以先通过原子层沉积法(ALD)制备一层氧化铝钝化层，再通过等离子体增强化学气相沉积法(PECVD)在氧化铝钝化层之上形成一层或者多层氮化硅层。
本申请实施例中的第一电极和第二电极可以使用金属制成，例如Ag、Cu、Al、Ni、Au、Zn、Sn、Pb等，可以使用金属氮化物制成，例如TiN等，可以使用金属碳化物制成，例如TiC等，也可以使用金属硫化物制成。在本申请实施例中，对于第一电极和第二电极的具体材质，不做过多的限制。在实际的应用中，技术人员可以根据需要选择合适的材质。
本申请实施例还公开了一种光伏组件，该光伏组件包括上述实施例中所述的太阳能电池片。
需要说明的是，在本申请实施例中，所述光伏组件包括的太阳能电池片与上述实施例中所述的太阳能电池片的结构相同，其有益效果也类似，在此不再赘述。
需要说明的是，本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
尽管已描述了本申请实施例的可选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例做出另外的变更和修改。所以，所附权利要求意欲解释为包括可选实施例以及落入本申请实施例范围的所有变更和修改。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体与另一个实体区分开来，而不一定要求或者暗示这些实体之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者终端设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者终端设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的物品或者终端设备中还存在另外的相同要素。
以上对本申请所提供的技术方案进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，同时，对于本领域的一般技术人员，依据本申请的原理及实现方式，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (24)

  1. 一种太阳能电池片，包括：
    基底，所述基底具有相对设置的第一表面和第二表面，所述第一表面包括间隔设置的第一区域和第二区域以及位于所述第一区域和所述第二区域之间的第三区域；
    第一掺杂层和第二掺杂层，所述第一掺杂层设置于所述第一区域的表面上或者至少部分嵌设于所述第一区域的表面内，所述第二掺杂层设置于所述第二区域的表面上或者至少部分嵌设于所述第二区域的表面内，所述第二掺杂层与所述第一掺杂层的极性相反；
    介质层和导电路径层，沿远离所述基底的方向，所述介质层和所述导电路径层依次叠置于所述第三区域，所述介质层阻隔所述第一掺杂层和所述第二掺杂层，所述导电路径层连接部分所述第一掺杂层和部分所述第二掺杂层。
  2. 根据权利要求1所述的太阳能电池片，其中，沿所述电池片的厚度方向，所述介质层的厚度大于所述导电路径层的厚度。
  3. 根据权利要求1所述的太阳能电池片，其中，沿所述电池片的厚度方向，所述导电路径层的厚度大于所述介质层的厚度。
  4. 根据权利要求1所述的太阳能电池片，其中，所述介质层和所述导电路径层的基础材料相同；
    或者，所述介质层和所述导电路径层的基础材料不同。
  5. 根据权利要求1所述的太阳能电池片，其中，所述导电路径层包括掺杂一种元素的层；
    和/或，所述导电路径层包括掺杂极性相反的两种元素的层。
  6. 根据权利要求1所述的太阳能电池片，其中，所述导电路径层包括单一掺杂路径层和共掺杂路径层，其中，
    所述单一掺杂路径层叠置于所述介质层远离所述基底的一侧，所述共掺杂路径层叠置于所述单一掺杂路径层远离所述介质层的一侧；
    所述单一掺杂路径层内掺杂一种元素，所述共掺杂路径层内掺杂极性相反的两种元素。
  7. 根据权利要求6所述的太阳能电池片，其中，所述单一掺杂路径层与所述共掺杂路径层的导电类型相同。
  8. 根据权利要求1所述的太阳能电池片，其中，所述导电路径层的表面元素掺杂浓度大于或者等于所述第一掺杂层的表面元素掺杂浓度；
    和/或，所述导电路径层的表面元素掺杂浓度大于或者等于所述第二掺杂层的表面元素掺杂浓度。
  9. 根据权利要求1所述的太阳能电池片，其中，沿所述电池片的厚度方向，所述导电路径层的厚度为d1，满足10nm≤d1≤120nm；
    和/或，
    所述导电路径层的元素掺杂浓度大于1E18cm-3且小于5E22cm-3。
  10. 根据权利要求1所述的太阳能电池片，其中，所述介质层的元素掺杂浓度小于1E13cm-3；
    和/或，沿所述电池片的厚度方向，所述介质层的厚度为d2，满足20nm≤d2≤490nm。
  11. 根据权利要求1所述的太阳能电池片，其中，与所述第三区域对应的所述基底内具有第三掺杂区域，所述第三掺杂区域的元素掺杂浓度小于1E13cm-3。
  12. 根据权利要求1所述的太阳能电池片，其中，与所述第一区域对应的所述基底内具有第一掺杂区域，所述第一掺杂区域的元素掺杂浓度大于1E13cm-3；
    和/或，与所述第二区域对应的所述基底内具有第二掺杂区域，所述第二掺杂区域的元素掺杂浓度大于1E13cm-3。
  13. 根据权利要求1-12中任一项所述的太阳能电池片，其中，所述第一掺杂层包括第一单掺层和第一共掺层，所述第一单掺层内掺杂一种元素，所述第一共掺层内掺杂极性相反的两种元素，其中，
    所述第一单掺层叠置于所述第一区域的表面上或者至少部分嵌入所述第一区域的表面内，所述第一共掺层叠置于所述第一单掺层远离所述基底的一侧，所述第一共掺层与所述第一单掺层的导电类型相反；
    所述太阳能电池片还包括第一电极，所述第一电极与所述基底的第一区域耦合，所述第一共掺层设置有贯穿槽，所述第一电极嵌设于所述贯穿槽内，且连接于所述第一单掺层或者所述基底的第一区域，所述第一电极与所述贯穿槽的内壁之间具有间隔。
  14. 根据权利要求13所述的太阳能电池片，其中，所述第一单掺层内的元素掺杂浓度的均匀性优于所述第一共掺层内的元素掺杂浓度的均匀性。
  15. 根据权利要求1-12中任一项所述的太阳能电池片，其中，所述第二掺杂层包括第二单掺层和第二共掺层，所述第二单掺层内掺杂一种元素，所述第二共掺层内掺杂极性相反的两种元素，其中，
    所述第二单掺层叠置于所述第二区域的表面上或者至少部分嵌设于所述第二区域的表面内，所述第二共掺层叠置于所述第二单掺层远离所述基底的一侧，所述第二共掺层与所述第二单掺层的导电类型相同。
  16. 根据权利要求15所述的太阳能电池片，其中，沿所述电池片的厚度方向，所述第二共掺层的厚度大于所述第一掺杂层的第一共掺层的厚度，且所述第一共掺层的厚度大于或者等于所述导电路径层的共掺杂路径层的厚度，其中所述第一共掺层内掺杂极性相反的两种元素，并且所述共掺杂路径层内掺杂极性相反的两种元素。
  17. 根据权利要求1所述的太阳能电池片，其中，所述第一掺杂层靠近所述导电路径层的一侧具有第一浓度渐变共掺区；
    所述第二掺杂层靠近所述导电路径层的一侧具有第二浓度渐变共掺区。
  18. 根据权利要求17所述的太阳能电池片，其中，在所述第一掺杂层为P型掺杂层，所述第二掺杂层为N型掺杂层的情况下，所述第一浓度渐变共掺区的宽度大于所述第二浓度渐变共掺区的宽度。
  19. 根据权利要求1所述的太阳能电池片，其中，所述导电路径层靠近所述第一掺杂层的一侧具有第一深度渐变共掺区，所述导电路径层靠近所述第二掺杂层的一侧具有第二深度渐变共掺区。
  20. 一种太阳能电池片的制备方法，所述方法包括：
    提供基底，所述基底具有相对设置的第一表面和第二表面，所述第一表面包括间隔设置的第一区域和第二区域以及位于所述第一区域和所述第二区域之间的第三区域；
    在所述第一区域的表面上或者所述第一区域的表面内形成第一掺杂层，在所述第二区域的表面上或者所述第二区域的表面内形成第二掺杂层，所述第一掺杂层与所述第二掺杂层的极性相反；
    沿远离所述基底的方向，在所述第三区域依次叠置介质层和导电路径层，以通过所述介质层阻隔所述第一掺杂层和所述第二掺杂层，通过所述导电路径层连接部分所述第一掺杂层和部分所述第二掺杂层。
  21. 根据权利要求20所述的太阳能电池片的制备方法，其中，所述在所述第一区域的表面上或者所述第一区域的表面内形成第一掺杂层，在所述第二区域的表面上或者所述第二区域的表面内形成第二掺杂层包括：
    在所述基底的第一表面上形成半导体层，在所述半导体层对应所述第一区域和所述第二区域的位置分别形成第一掺杂源层和第二掺杂源层；
    加热推进所述第一掺杂源层和所述第二掺杂源层，以使所述半导体层对应所述第一区域的部分形成所述第一掺杂层，所述半导体层对应所述第二区域的部分形成所述第二掺杂层，所述第一掺杂层和所述第二掺杂层的极性相反。
  22. 根据权利要求20所述的太阳能电池片的制备方法，其中，所述沿远离所述基底的方向，在所述第三区域依次叠置介质层和导电路径层包括：
    在所述基底的第一表面上形成半导体层，在所述半导体层对应所述第三区域的位置形成第三掺杂源层；
    加热推进所述第三掺杂源层，以使所述半导体层对应所述第三区域的部分沿远离所述基底的方向，依次形成叠置的所述介质层和所述导电路径层。
  23. 根据权利要求20所述的太阳能电池片的制备方法，其中，所述在所述第一区域的表面上或者所述第一区域的表面内形成第一掺杂层包括：
    在所述基底的第一表面上形成半导体层，在所述半导体层对应所述第一区域的位置形成第一掺杂源层；
    加热推进所述第一掺杂源层，以使所述半导体层对应所述第一区域的部分形成第一单掺层；
    在所述第一单掺层上形成第四掺杂源层；
    加热推进所述第四掺杂源层，以使所述第一单掺层在远离所述基底的一侧形成第一共掺层，所述第一单掺层和所述第一共掺层构成所述第一掺杂层；
    所述方法还包括：
    在所述第一共掺层上设置贯穿槽，将第一电极嵌设于所述贯穿槽内，并连接于所述第一单掺层或者所述基底的第一区域，所述第一电极与所述贯穿槽的内壁之间具有间隔。
  24. 一种光伏组件，包括权利要求1-19中任一项所述的太阳能电池片。
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CN118099245A (zh) * 2024-04-22 2024-05-28 浙江晶科能源有限公司 背接触太阳能电池及其制备方法、光伏组件
CN118571966A (zh) * 2024-07-17 2024-08-30 隆基绿能科技股份有限公司 太阳能电池片、太阳能电池片的制备方法及光伏组件

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