WO2026006241A2

WO2026006241A2 - Differential column weighted imc architecture

Info

Publication number: WO2026006241A2
Application number: PCT/US2025/034940
Authority: WO
Inventors: Jinseok Lee; Naveen Verma
Original assignee: Princeton University
Current assignee: Princeton University
Priority date: 2024-06-25
Filing date: 2025-06-24
Publication date: 2026-01-02
Anticipated expiration: 2026-12-25
Also published as: WO2026006241A9

Abstract

Various embodiments comprise systems, methods, architectures, mechanisms, apparatus, and improvements thereof for a differential column-weighted in-memory computing architecture.

Description

DIFFERENTIAL COLUMN- WEIGHTED IMC ARCHITECTURE

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of US Provisional Patent Application Serial No. 63/663,916 filed June 25, 2024, which Application is incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

[0002] The present invention relates to the field of in-memory computing and, more particularly, to a differential column-weighted in-memory computing architecture.

BACKGROUND

[0003] This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention that are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

[0004] Charge-domain in-memory' computing (IMC) has recently emerged as a robust and scalable way of doing in-memory computing. Here, compute operations within memory bit-cells provide their results as charge, typically using voltage-to-charge conversion via a capacitor. Thus, bit-cell circuits involve appropriate switching of a local capacitor in a given bit-cell, where that local capacitor is also appropriately coupled to other bit-cell capacitors, to yield an aggregated compute result across the coupled bit-cells. In-memory computing is well suited to implementing matrix-vector multiplication, where matrix elements are stored in the memory array, and vector elements are broadcast in parallel fashion over the memory array.

[0005] Advantageously, rather than acquiring individual bits one-at-a-time as done in conventional memory', an IMC computing architecture acquires computational results over many bits stored in memory. This enhances system energy efficiency and speed by reducing the number of data acquisition cycles required. Often, a computational result is derived within a memory' column, where: parallel input data is provided to the rows, computation (e.g., multiplication) is performed by the memory' bit cells with data stored therein; and further computation (e g., accumulation) is performed on the column bit lines to provide reduction to a single output. The reduced output generally has increased dynamic range (i. e. , number of signal levels) that need to be resolved, relative to single-bit accessing. Further, analog operation is often employed for the column computation, both to fit computation within the constrained memory circuits (e.g., bit cells, bit lines) and to enable the increased dynamic range. This necessitates for each column an analog-to-digital converter (ADC), in order to convert the column’s analog output to a digital representation, suitable for further processing within an architecture.

SUMMARY

[0006] Various deficiencies in the prior art are addressed by systems, methods, architectures, mechanisms, apparatus, and improvements thereof for a differential column-weighted in-memory computing architecture or hardware.

[0007] An integrated in-memory computing (IMC) hardware according to an embodiment comprises an array of switched capacitor (SC) differential output multiplying bit-cells (MBCs) processing N bits per cycle, where N is an integer greater than one; each of a plurality of MBC columns within the MBC array has associated with it respective positive and negative compute lines configured to be coupled to a differential analog-to-digital converter (ADC) to provide thereby a respective data-representative analog output signal; each MBC within a column of MBCs having positive and negative compute line outputs configured to charge respective positive and negative compute line capacitors coupled to the positive and negative compute lines of the respective array column.

[0008] In various embodiments, each MBC column having a greater data weight than the data weight of an adjacent MBC column charges its respective positive and negative compute line capacitors at a greater voltage level than that of the adjacent MBC column.

[0009] Additional objects, advantages, and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention and, together with a general description of the invention given above, and the detailed description of the embodiments given below, serve to explain the principles of the present invention.

[0011] FIG. 1 depicts an in-memory-computing (IMC) macro according to an embodiment of the differential column-weighted architecture;

[0012] FIG. 2A depicts a circuit diagram showing an architecture connecting MBCs configured for providing differential CLP/CLN outputs across two columns of binary -weighted data;

[0013] FIG. 2B depicts a circuit diagram of a pair of MBCs configured in accordance wi th the architecture of FIG. 2A;

[0014] FIG. 2C depicts an exemplary integrated circuit physical layout of the MBC architecture of FIG. 2A;

[0015] FIG. 3 A depicts a circuit diagram showing an architecture connecting MBCs configured for providing non-differential CLp outputs across two columns of binary -weighted data;

[0016] FIG. 3B depicts a circuit diagram of a pair of MBCs configured in accordance with the architecture of FIG. 3 A;

[0017] FIG. 4A depicts a circuit diagram of an architecture enabled by properly configured MBCs for providing differential CLP/CLN outputs across up to four columns of binary -weighted data;

[0018] FIG. 4B tabulates three configuration modes associated with the architecture and MBC configuration of FIG. 4A;

[0019] FIG. 4C graphically illustrates ADC resolution overlayed on top of input-data distribution, where ADC resolution is designed to be highest where input distribution density is maximum around mid-range (zero);

[0020] FIGS. 5A-5E graphically illustrate measured accuracy useful in confirming the efficacy of various embodiments;

[0021] FIG. 6 graphically illustrates an energy and SNR comparison summary associated with the configuration modes discussed with respect to FIGS. 4A-4C; and [0022] FIGS. 7A-7B illustrate a neural network demonstration summary, and comparison table, showing state-of-the-art efficiency and accuracy achieved by the various embodiments; [0023] FIG. 8 illustrates a die photo and measurement summary of a prototype implemented in 28nm standard CMOS.

[0024] FIGS. 9A-9B depict an exemplary test and measurement setup, showing hardware and software components thereof;

[0025] FIG. 10 illustrates area breakdown of a macro according to various embodiments; and

[0026] FIGS. 11-13 depict circuit diagrams of a pair of MBCs configured in accordance with the architecture of FIG. 2A using alternate embodiment weighting mechanisms.

[0027] It should be understood that the appended drawings are not necessarily to scale, presenting a somewhat simplified representation of various features illustrative of the basic principles of the invention. The specific design features of the sequence of operations as disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes of various illustrated components, will be determined in part by the particular intended application and use environment. Certain features of the illustrated embodiments have been enlarged or distorted relative to others to facilitate visualization and clear understanding. In particular, thin features may be thickened, for example, for clarity or illustration.

DETAILED DESCRIPTION

[0028] The following description and drawings merely illustrate the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the invention and the concepts contributed by the inventor(s) to furthering the art and are to be construed as being without limitation to such specifically recited examples and conditions. Additionally, the term, "or," as used herein, refers to a non-exclusive or, unless otherwise indicated (e.g.. “or else” or “or in the alternative”). Also, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. [0029] The numerous innovative teachings of the present application will be described with particular reference to the presently preferred exemplary embodiments. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. Those skilled in the art and informed by the teachings herein will realize that the invention is also applicable to various other technical areas or embodiments.

[0030] Before the present invention is described in further detail, it is to be understood that the invention is not limited to the particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.

[0031] Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limit of that range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.

[0032] Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can also be used in the practice or testing of the present invention, a limited number of the exemplary' methods and materials are described herein. It must be noted that as used herein and in the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise.

[0033] The various embodiments will be discussed within the context of an IMC computing architecture or hardware acquiring computational results over many bits stored in memory, such as computational results derived within memory columns, where: parallel input data is provided to the rows, computation (e.g., multiplication) is performed by the memory bit cells with data stored therein; and further computation (e g., accumulation) is performed on the column bit lines to provide at each column bit line a respective analog output signal representing a computational result associated with the respective bit line, illustratively described herein as being provided as a charge level though in alternate embodiments the column analog output may comprise a current level or voltage level. [0034] Part of the innovation herein is the determination by the inventors that, while in memory computing (IMC) research has recently seen substantial progress, a critical factor for energy and throughput advantage remains the fundamental signal-to-noise (SNR) tradeoff, such as arises from the dynamic range required for in-memory data reduction during, for example, accumulation within matrix-vector multiplications (MVMs). Specifically, while analog IMC has the potential to maximize compute efficiency and density, it is limited by analog noise in the bit cells used to store data-representative charge, as well as analog noise and quantization in analog to digital converters (ADC) used to convert the stored charge into a representative digital output word or signal. Switched-capacitor (SC) analog IMC may be used to address bit-cell analog noise (e.g., temperature/process variations, nonlinearities, etc.), thereby enabling a very large accumulation dynamic range. However, ADC noise and quantization remains as a primary limiter of SC analog IMC.

[0035] Various embodiments provide a differential-signal or differential architecture for in-memory computing (IMC). This is significant because it doubles the dynamic range of the signal-processing architecture, which poses the primary limitation today to the achievable performance and efficiency of IMC. Furthermore, it enhances robustness to common-mode noise sources, such as stray-capacitive coupling noise and power-supply noise. The differential architecture has the potential to increase integrated circuit (IC) fabrication area, however various embodiments leverage specialized optimizations and layout and/or a column weighting approach to enable reduced area. Various embodiments utilize a signal weighting approach, which enables area/density advantage w hen operating on 2 or more operand bits, which is the most common scenario.

[0036] Various embodiments address ADC limitations, achieving the highest energy efficiency reported thus far for analog IMC, through various contributions, including in various embodiments features such as: (1) ADC sharing between (illustratively) two or four IMC columns to amortize power and area, while increasing ADC resolution to, illustratively. 10 bits (10b), thereby- surpassing the typical ADC resolution of up to 8b of previous analog IMCs;

(2) a fully differential IMC architecture configured to enable ADC input swing to be doubled within the supply -voltage limits, thereby improving the efficiency of keeping analog noise sources below a sub-LSB level at the increased ADC resolution;

(3) a non-uniform ADC quantization architecture configured to provide higher precision in a center portion of the ADC conversion range, where IMC output data tends to be concentrated;

(4) an architecture providing differential output multiplying bit-cell (MBC) columns wherein each MBC provides compute line negative and compute line positive outputs with respective MBC capacitors (i.e., differential MBC embodiments);

(5) an architecture providing paired MBC columns where adjacent column MBCs share the compute line negative and compute line positive outputs, MBCs of a first column drive their compute line negative and positive outputs through unit capacitance MBC capacitors, and MBCs of a second column drive their compute line negative and positive outputs through double unit capacitance MBC capacitors (i.e., binary- weighted or other weighted differential embodiments);

(6) an architecture providing groups of three or more MBC columns where MBCs of adjacent MBC columns drive their compute line negative and positive outputs through unit capacitance MBC capacitors (i.e., non-weighted differential group embodiments); and

(7) an architecture providing groups of three or more MBC columns where MBCs of adjacent MBC columns drive their compute line negative and positive outputs through unit capacitance MBC capacitors that are twice the capacitance of MBCs of adjacent lower order or weighted columns (i.e., binary weighted or other weighted differential group embodiments); and

(8) an architecture providing some or all of the features described above either alone or in any combination.

Other embodiments are also described herein, such as weighted MBC column pairs or groups using columnar weighting other than binary- weighting, the optional use of multi-level dynamic-range doubling (DRD) drivers, and so on as will be described in more detail below. [0037] FIG. 1 depicts an in-memory-computing (IMC) macro according to an embodiment. The IMC macro 100 of FIG. 1, which may be used to implement compute-in-memory array (CIMA) structures and the like, is configured for providing fully row/column-parallel matrix-vector multiplication (MVM), for exploiting precision analog computation based on metal (wire) capacitors, for extending binary input-vector elements to for example 4-bit (4b) input-vector elements, and for doing so with increased energy efficiency and accuracy. The architecture/hardware of the in-memory computing macro as depicted supports in-memory computation over 4b inputs and 2b weights within two adjacent columns with 10b output analog to digital converters (ADCs). Various modifications are also contemplated. Further, the input and weight resolutions can be increased by properly weighting and summing the depicted outputs in the digital domain, across different 4b inputs provided across serial operations and 2b weights stored in parallel columns.

[0038] The IMC macro 100 of FIG. 1 comprises, illustratively, a fully row-/ column-parallel (e.g., 256 column x 1152 row) array 110 of switched capacitor (SC) static random-access memory (SRAM) based 10T multiplying bit-cells (MBCs) 105i-i through 105256-1152, periphery for writing/ reading thereto (e.g., a bit line (BL) decoder 140 including 256 BL drivers, a word line (WL) or address decoder 150 operatively coupled to 1152 WL drivers 152-1 through 152-1152, an SRAM control block 145 for controlling the decoders 240/250); periphery for providing 4-bit input-vector elements thereto (e.g., 1152 Dynamic-Range Doubling (DRD) DACs 120-1 through 120-1152, and a corresponding controller 125); periphery for digitizing the compute result from each column (e.g., 128 10-bit differential SAR ADCs 160-1 through 160-128); and column reset mechanisms (not shown) configured to pull the output voltage levels of column compute lines CLs to a reset voltage VRST during a reset phase of operation and allow the voltage levels of column compute lines CLs to reflect their respective compute results during an evaluation phase of operation. It is noted that, as depicted in FIG. 1 and described herein, the 1152 rows of the array 110 are vertically oriented and numbered from left to right, and the 256 columns of the array 110 are horizontally oriented and numbered from bottom to top. Specifically, to align with the typically fabrication techniques of memory, the depicted memory has been rotated by 90 degrees such that columns run horizontally and rows run vertically.

[0039] The array 110 of 10T SRAM multiplying bit cells (MBCs) 105 of IMC macro 100 is configured for, illustratively, row-by-row writing/reading operations. MVM operations are ty pi cal 1 y performed by applying input-vector elements corresponding to neural-network input activations to all or several rows at once. Each DRD-DAC 220j, in response to a respective 4-bit input-vector element Xj [3 : 0] , generates a respective differential output signal (IAj/I Abj) which is subjected to a 1 -bit multiplication with the stored weights (Wij/Wbij) at each MBCj in the corresponding row of MBCs, and accumulation through charge-redistribution across MBC capacitors on the compute line (CL) to yield an inner product in each column, which is then digitized via the respective ADC 160 of each column. It is noted that the term '‘column’⁷ may refer to structure depicted in the various figures as having a horizontal presentation, while “row” may refer to structure depicted in the various figures as having a vertical presentation.

[0040] Specifically, and referring to FIG. 1. input activations (lA/IAb) are optionally driven by multi-level dynamic-range doubling (DRD) drivers 120, which enable per-cycle processing of 4b wide inputs by selecting from eight different activation voltage supply levels VACTI through VACTS during SC reset/evaluate phases, to yield 16 possible transitions. It is noted that this processing increases IMC energy efficiency and throughput by 4X compared to bit-serial processing of inputs, where the increased compute-line (CL) dynamic range is enabled by the precision of SC operation. However, with such a high CL dynamic range, the ADC energy and precision (quantization) thus limits IMC operation. It is noted that each of the various embodiments described herein may be implemented with or without the optional multi-level dynamic-range doubling (DRD) drivers 120.

[0041] To address ADC energy, the various embodiments share each ADC 1 0 across two columns via an architecture where two columns, storing 2b weight data, provide binary-weighted accumulation on a respective single set of differential compute-lines denoted as CLp and CLN. While binary -weighting across 2b weight data is depicted, it should be understood that such an approach can be extended to a different (higher) number of weight bits as well. Such binary⁷ -weighting across multiple weight bits increases the CLP/CLN dynamic range. This is managed by a high ADC resolution, e g., 10 bit resolution as shown. Inputs beyond 4b precision are processed serially, and weights beyond 2b precision are stored and processed in multiple sets of two columns, whereby the final outputs are obtained by binary-weighting and summing the serial/parallel ADC outputs in the digital domain. For example, as depicted in FIG. 1, a first row of MBCs 105 i-i through 105I-HS2 cooperate with a second row of MBCs 1052-1 through 1052-1152 to form a first pair of cooperating rows 107i, which provide therefrom (via compute line controller 130) a first set of differential compute-lines CLp,i and CLN,I. The compute line controller 130 also includes reset switches (not shown) which are operable to reset (e.g., discharge or ground) the output capacitors within the various MBCs.

[0042] Optionally, the compute line controller includes scaler circuitry 132 as will be described in more detail below. Briefly, the scaler circuitry 132 may be used to reduce or scale an input to a differential ADC associated with a particular column as appropriate so as to maintain a binary weighting (or other weighting) between adjacent columns, column pairs, and so on. The scaling circuitry may comprise capacitor or charge divider circuitry', voltage divider circuitry, current divider circuitry, and/or any other circuitry suitable for use in scaling ADC input signals.

[0043] Optionally, the ADCs 160 include scaler circuitry similar to that described herein with respect to scaler circuitry' 132 to provide binary' or other weighting, illustratively associated with sample and hold circuitry within the ADCs 160.

[0044] Optionally, the ADCs 160 are NOT differential ADCs. That is, in some embodiments the ADCs 160 comprise single-ended ADC and not differential ADCs. In these embodiments, the CLp compute-line for a column may be coupled to an input of a single- ended ADC used for that column, while the CLN compute-line for that column may be coupled to a reference of the single-ended ADC for that column. Alternatively, each of the differential compute-lines CLp and CLN for a column may be coupled to inputs of respective single-ended ADCs for that column.

[0045] At such high ADC resolution, even high-precision SAR ADCs begin to approach thermal/shot-noise (analog) limitations, in addition to quantization-noise limitations. Thus, we employ a differential IMC architecture, which provides increased robustness to coupling noise sources (supply, substrate, stray), but also doubles the full-range swing within the supply-voltage limits, thus increasing the ADC LSB voltage above the analog noise.

[0046] FIG. 2A depicts a circuit diagram of a MBC architecture configured for providing differential CLP/CLN outputs across two columns of binary -weighted data. Again, it should be understood that this can be extended to more than two columns, through corresponding binary' weighting. Referring to FIG. 2B, each MBC 105 includes, illustratively, a 6T cell for data storage (W/Wb) and four NMOS switches. Two NMOS switches are used to select between the differential input activations (lA/lAb), based on W/Wb data, in order to drive a capacitor (CNIBC) coupled to each of the differential compute lines (CLP/CLN). In this way, a positive or negative transition is charge coupled to the compute lines, performing multiplication, and charge across MBCs in the column is summed, performing accumulation. [0047] It is noted that the various transistors of FIG. 3B (e.g., Mi through Ms) are depicted as NMOS transistors. However, these and other transistors may comprise, NMOOS, CMOS, and/or other types of transistors. While SC MBCs typically employ CMOS rather than NMOS switches to ensure low-impedance capacitor driving with maximum swing, various embodiments may optionally use NMOS-only switches, since DRD only requires input transitions from O-VDD/2, exploiting signal-charge storage during both reset and evaluate phases of SC operation to generate full-swing output range. Using NMOS only switches (rather than both NMOS and PMOS) may impose a speed penalty. However, the inventors note that NMOS suitable for passing lower to midpoint voltages, as might be the case for lower dynamic range differential ADC processing as discussed herein. The NMOS device is a little slower as voltages approach the VDD/2 level, but this speed penalty may be compensated for in the cell design and in the timing of the switches such that sufficient time is allowed for higher voltages more slowly passing through the NMOS device to charge a capacitor. That said, the speed of the NMOS device may or may not be a limiting factor in terms of charging the capacitor.

[0048] MBCs from the two columns (bitl, bit 0) both couple to the same compute lines (CLP/CLN), but through binary -weighted capacitors (2CMBC, CNIBC), thus providing accumulation across 2b stored weights. For differential and binary-weighted operation, the two MBCs thus require a total of 6-unit capacitors (CNIBC), effectively corresponding to 3CMBC per MBC. Despite this, the cell area is reduced compared to previous SC MBC by 20% through the efficient layout shown in FIG. 2C. The coupling capacitors are laid out as shown, across four MBCs, i.e., two sets of adjacent binary-weighted MBCs. This enables the 6 unit-capacitor (CNIBC) structures in the metal-layer design rules, with excellent capacitor precision verified by measurements.

[0049] In various embodiments, for a pair of columns the capacitors in a most significant bit (MSB) column (bit 1) may be twice as big as caps in a MSB-1 or least significant bit (LSB) (bit 0) column. That is, for the MSB column CMSB=C, whereas for the MSB-1 column, where CMSB-I=C/2. This may be implemented using three capacitors: two in the MSB column and one in the MSB-1 column. Since differential processing is used, there may be a need for 6 capacitors. This can be laid out in a manner avoiding area density penalty . That is, combining the capacitors and laying them out in a manner optimizing across multiple columns provides a means to avoid area overhead penalty. Thus, scaling via capacitor selection may be used to cause bO column (MSB-1 or LSB column) to be scaled so as to be half the weight of a bl column (MSB column). Similarly, scaling via capacitor selection may be used in four column (4 bit), eight column (8-bit) and other embodiments where binaryscaling between columns is desired. Further, scaling via capacitor selection may also be used to provide non-binary scaling in various embodiments.

[0050] In various embodiments, rather than scaling signal via differences in capacitor size, optional scaling circuitry 132 may be provided via, illustratively, the compute line controller 130. The scaling circuitry may comprise capacitor or charge divider circuitry, voltage divider circuitry, current divider circuitry, and/or any other circuitry suitable for use in scaling ADC input signals. The scaler circuitry 132 may be used to reduce or scale an input to a differential ADC associated with a particular column as appropriate so as to maintain a binary weighting (or other weighting) between adjacent columns, column pairs, and so on. The optional scaling circuitry 132 may be used alone or with capacitor selection scaling.

[0051] Brief discussion of non-differential embodiments. FIG. 3A depicts a circuit diagram showing an architecture connecting MBCs configured for providing non-differential CLp outputs across two columns of binary-weighted data, while FIG. 3B depicts a circuit diagram of a pair of MBCs configured in accordance with the architecture of FIG. 3A. It is noted that the architecture/circuitry 300A/300B of FIGS. 3A-3B differ from the architecture/circuitry 200A/200B of FIGS. 2A-2B in that the MBCs of FIGS. 3A-3B are not differential, and therefore include only the circuitry associated with one compute line (CL), illustratively compute line CLp, rather than two compute lines CLP/CLN configured to form a differential compute line output. It can also be seen that transistors M3, M4, M7, and Ms of the circuitry 200B of FIG. 2B are not present in the circuitry 300B of FIG. 3B. Aside from the lack of differential operation, the architecture of FIGS. 3A-3B works similarly to the architecture of FIGS. 2A-2B. The architecture of FIGS. 3A-3B is provided to illustrate the use of scaling or weighting capacitors 2CMBC and 1CMBC,SUC1I as described herein with respect to binary (and other) weighted pairs or groups of columns in a MBC array. Thus, other than the differential compute line functionality, the discussion herein with respect to the various embodiments is also applicable to the non-differential embodiments illustrated in FIGS. 3A-3B.

[0052] FIG. 4A depicts a circuit diagram of a MBC architecture configured for providing differential compute line CLP/CLN outputs across four columns of binary -weighted data, as compared to the two columns of binary-weighted data discussed above with respect to FIGS. 2A-2C. That is, the depicted architecture contemplates three configuration modes: (1) each set of binary-weighted columns feeds one ADC; (2) two sets of binary -weighted columns feed one ADC (by shorting segment of second column); (3) two sets of binary-weighted columns feed two ADCs (by shorting segment of second column), where the first ADC’s conversion range and quantization step sizes are reduced around mid-range (or some other point within the full range).

[0053] Specifically, FIG. 4A depicts an embodiment configured to address a challenge with analog IMC; namely, the inefficient use of ADC dynamic range that can result from inputs having highest distribution density at mid-range (zero), due to large accumulation dimension across uncorrelated products, as illustrated in FIG. 4C. Specifically, the circuit 400A depicted in FIG. 4A provides for a complementary use of two cooperating weighted column pairs (e.g., first and second weighted column pairs forming a weighted column group), each pair comprising a respective pair of columns sharing an ADC 160, resulting in three configuration modes, as tabulated in FIG. 4B.

[0054] MBCs from a first pair of columns (bit3, bit2) couple to respective compute lines (CLP/CLN) of a first differential ADC through respective binary' -weighted capacitors (8CMBC, 4CMBC), thus providing accumulation across 2b stored weights, while MBCs from a second pair of columns (bitl, bitO) couple to respective compute lines (CLP/CLN) of a second differential ADC through respective binary-weighted capacitors (2CMBC, CMBC). Stated differently, for the MSB column CMSB=C, for the MSB-1 column CMSB-I=C/2, for the MSB-2 column CMSB-2=C/4, and for the MSB-3 (or LSB) column CMSB-3=C/8.

[0055] In Mode (1), each pair of differential columns feeds inputs of a separate ADC.

[0056] In Mode (2), tw o pairs of differential columns feeds inputs of one ADC, thereby amortizing its energy. As shown, switches are introduced across the compute lines (CLP/CLN) enabling separation into four segments. After the charge accumulation operation has settled, opening these results in segments with one-fourth the original capacitance, and thus one-fourth the charge. Shorting all CLP/CLN segments of one column pair (by keeping the switches closed) with one CLP/CL segment of an adjacent column pair (by opening the switches) thus results in binary’ weighted charge accumulation across 4 columns. Such shorting is achieved via additional switches preceding the ADCs. This operation increases the dynamic range. It is noted that weighting other than binary weighting may be used, and such weighting may be controlled by adapting the capacitance selection accordingly, such as discussed herein with respect to binary’ yveighting. For example, for weighting a first column lOx that of a second column, the capacitance associated with the first (i.e., lOx) column is 10 times larger than the capacitance associated with the second (i.e., lx) column.

[0057] In Mode (3), two pairs of differential columns feeds inputs of each of two ADCs, where the conversion range of one ADC is reduced by scaling the reference voltages (VREF,P/N). yielding higher density’ of quantization levels at mid-range, while preserving the full conversion range of the second ADC, w ith the original density of quantization levels. That is, non-uniform ADC quantization is employed to substantially mitigate ADC quantization noise, since ADC theory holds that quantization levels should optimally be distributed according to the input-data distribution density’. Higher density of quantization levels in the first ADC implies smaller LSB voltage, elevating its sensitivity to analog noise sources; how ever, by utilizing both ADC outputs via weighted averaging in the digital domain, the uncorrelated analog noise is effectively reduced, as shown in measurements (below). By exploiting non-uniform quantization optimized to the ADC input distribution, this method further improves the overall SNR for random MVMs.

[0058] It is noted that the differential ADC is depicted as being a 1 Obit differential ADC, which may be used instead of prior 8bit ADCs. In various embodiments, the first differential ADC comprises a full range differential ADC while the second differential ADC comprises a smaller or reduced range differential ADC (e.g., !4. A, or some other reduced range as compared to the larger or full range differential ADC). In this manner, the 1024 levels may be distributed so as to have reduced error in quantization steps in a portion of the output data stream (i.e., the portion associated with the second differential ADC) where the addition of uncorrelated variables across the columns will exhibit the most date, such as at the center of the range. That is, there is a concentration of data around a zero point. Preference is to concentrate the quantization levels yvhere the density of data is highest. In this manner, various embodiments provide a higher precision in the smaller but more important range (i.e., portion where data likely to exist) to thereby reduce quantization error where it matters most. [0059] Advantageously, overall signal to quantization noise (SQNR) is greatly improved using the two ADCs in this manner (i.e., full range, partial range).

[0060] In one embodiment, the smaller or reduced range ADC is configured to operate at a zero point (midpoint) of the range associated with the larger or full range ADC.

[0061] In one embodiment, the smaller or reduced range ADC is configured to operate at a programmable or selectable point, which may be a zero point (midpoint) of the range associated with the larger or full range ADC, or some other operating point above or below the zero point (midpoint) of the range associated with the larger or full range ADC. The zero or midpoint of the range associated with the smaller or reduced range ADC will typically be the point proximate that portion of the full range where most of the data will be present (i.e., the data is most dense). However, other points above or below the zero or midpoint of the range associated with the larger or full range ADC may be deemed to be proximate ranges where more data will be present, or where the data expected to be present is more important in some way than data expected to be at the zero or midpoint or other points within the range associated with the larger or full range ADC. In some embodiments this window may be configured to move in response to data-related detected/determined energy levels associated with at various points in the range associated with the larger or full range ADC. This window can also be swept back and forth in response to a known distribution of expected data.

[0062] If data distribution is non-uniform, such as being peaky or having multiple peaks or a non-uniform distribution, the smaller or reduced range differential ADC may be configured to have a useful window or range that captures the peaky or data rich portion of the expected data.

[0063] Optionally, the ADC operation may be repeated to scan multiple data regions of interest (e g., two side lobes of peaky data rather than a single peaky portion of the expected data).

[0064] FIGS. 5A-5B illustrate measured transfer-function linearity for 4 bit input sweep (providing 16 output values) and 2 bit weight sweep (providing four output values) operation, respectively. FIG. 5C illustrates measured output as a function of nominal output for a 4 bit input sweep and a 2 bit weight sweep over the full IMC computation range (4b inputs, 2b weights, and 1152 rows), which results in <+/-! LSB INL at 10b ADC level as illustrated in FIG. 5D. FIG. 5E shows measured noise of three configuration modes, showing sub-LSB noise and reduced noise of mode 3 in mid-range region. FIG. 6 shows measured energy breakdown, SNR (relative to computation with no ADC quantization), and random MVM results, exhibiting excellent match with ideal computation.

[0065] FIGS. 5A-5E graphically illustrate measured accuracy useful in confirming the efficacy of various embodiments. The column transfer funchon is fully characterized by separate sw eeps, of the 4b inputs, 2-bit weights, and full range (4b inputs, 2b w eights, 1152 rows). In all cases, high input-output linearity is observed with INL <+/-! LSB at the 10 b level. Further, the output noise is characterized for each of the modes, at a level of 0.41 and 0.47 LSBRMS for Modes (1) and (2), and at a level that reduces to 0.29 LSBRMS via ADC averaging at the mid-range for Mode (3), where the LSB voltage is reduced by ~2X. In all cases, we see the importance of the differential architecture in keeping the noise below the 0.5 LSB level, when increasing ADC resolution to 10b.

[0066] FIG. 6 graphically illustrates a comparison summary associated with the configuration modes discussed with respect to FIGS. 4A-4C. As depicted in FIG. 6, achieved energy efficiency is 6143 (Mode (1)), 6585 (Mode (3)), and 8161 (Mode (2)) TOPS/W/b and compute density of 112 TOPS/mm2/b. As shown at the top. the high accuracy of the chip (in Mode (2)) was used to demonstrate CIFAR-10 and ImageNet classification via ResNet-18, achieving accuracies of 92.34% and 69.88%, equivalent to floating-point computation. AS show, measured energy for config, modes 1. 2, 3, as well as random MVM computation results (chip measured show excellent match with ideal computation) and SNR (relative to MVM with no ADC quantization/truncation).

[0067] FIGS. 7A-7B illustrate a neural network demonstration summan' (mode 2), and comparison table, showing state-of-the-art efficiency and accuracy achieved by the various embodiments.

[0068] FIG. 8 illustrates a die photo and measurement summary of a prototype implemented in 28nm standard CMOS.

[0069] FIGS. 9A-9B depict an exemplary test and measurement setup, showing hardware and software components thereof. The exemplary hardware consists of prototype chip on custom PCB connected to FPGA board (via FMC), implementing chip-control FSM and Ethernet server to host processor. The exemplary software consists of Python interfaces Ethernet drivers, within host processor, connecting to embedded microcontroller code running on FPGA board. Host Python functions are implemented to read/write and perform MVM computations on chip, used to implement neural-network demonstrations. [0070] FIG. 10 illustrates area breakdown of a macro according to various embodiments, across major blocks. It is noted that the bit-cell (MBC) array occupies nearly 70% of the macro, yielding high array efficiency.

[0071] As discussed in more detail above with respect to FIG. 2B, each MBC 105 includes, illustratively, a 6T cell for data storage (W/Wb) and four NMOS switches. Two NMOS switches are used to select between the differential input activations (lA/IAb), based on W/Wb data, in order to drive a capacitor (CMBC) coupled to each of the differential compute lines (CLP/CLN). In this way, a positive or negative transition is charge coupled to the compute lines, performing multiplication, and charge across MBCs in the column is summed, performing accumulation. As noted above, the bitO and bitl 'columns" of FIG. 2B are depicted as having a horizontal presentation, while the differential signal lines (lA/IAb) and word line (WL) are depicted as having a vertical presentation.

[0072] Further, MBCs from the two columns (bitl, bit 0) both couple to the same compute lines (CLP/CLN), but through binary-weighted capacitors (2CMBC, CMBC), thus providing accumulation across 2b stored weights. For differential and binary-weighted operation, the two MBCs thus require a total of 6-unit capacitors (CMBC), effectively corresponding to 3 CMBC per MBC.

[0073] Thus, FIG. 2B depicts a circuit diagram of a pair of MBCs configured in accordance with the architecture of FIG. 2A wherein weighting the bitO and bitl columns is achieved using respective weighted capacitors CMBC (e.g., binary-weighted capacitors CMBC for bitO column and 2CMBC for bitl column).

[0074] FIGS. 11-13 depict circuit diagrams of a pair of MBCs configured in accordance with the architecture of FIG. 2A using alternate embodiment weighting mechanisms.

[0075] Referring to FIGS. 11-13, it can be seen by inspection that for each of the bitO and bitl columns, the capacitors (CMBC) coupled to each of the differential compute lines (CLP/CLN) is the same (i.e., 1C). In the embodiments of FIGS. 11-13, weighting of the bitO and bitl columns is achieved using different capacitor driving voltages such that capacitors C BC of a higher weighted column (e.g., bitl) are driven with a larger voltage swing than capacitors CMBC of a lower weighted column (e.g., bitO).

[0076] As shown in FIG. 11, each of the bitO and bitl columns is associated with respective differential input activations (lA/IAb). That is rather than each of the bitO and bitl columns being connected to the same differential signal lines (lA/IAb) such as depicted above with respect to FIG. 2B. in the embodiments of FIG. 11 the bitO column is connected to a first pair of differential signal lines (lAo/IAbo) and bitl column is connected to a second pair of differential signal lines (lAi/IAbi).

[0077] By selecting different voltage levels for the first (lAo/IAbo) and second (lAi/IAbi) pairs of differential signal lines, the corresponding weighting of the bitO and bitl columns may be selected. For example, to replicate the binary weighting of FIG. 2B ((e.g., binary -weighted capacitors CMBC for bitO column and 2CMBC for bitl column), the embodiments of FIG. 11 may select for the bitl column a voltage (lAi/IAbi) that is twice the voltage (lAo/IAbo) selected for bitO column. Other voltage levels (lAo/IAbo) and (lAi/IAbi) may be used to provide weighting between columns other than binary weighting.

[0078] The weighting mechanisms of FIG. 11 provide an architecture wherein each MBC column having a greater data weight than the data weight of an adjacent MBC column charges its respective positive and negative compute line capacitors at a greater voltage level than that of the adjacent MBC column.

[0079] As shown in FIG. 12, and unlike the embodiments of FIG. 11. each of the bitO and bitl columns is associated with the same differential input activation (lA/IAb). However, each of the bitO and bitl columns is associated w ith respective signal-gain (SG) circuitry configured to amplify or attenuate signal from the differential signal lines (lA/IAb) during respective sampling times (time slots) and hold the sampled signal during respective nonsampling or hold times (time slots) .

[0080] By connecting via respective SG circuitry the bit cells of each column (e.g., bitO and bitl) to the differential signal lines (lA/IAb) only during respective assigned time slots; namely, timeslot 0 for bitO, timeslot 1 for bitl, and so on. Specifically, in response to the control signal 00, the bitO SG circuits SG01 and SG02 amplify/attenuate the differential signal lines lA/IAb and provide differential signals IA<so/IAb<co. Similarly, in response to the control signal Ol, the bitl SG circuits SGI 1 and SG12 amplify/attenuate the differential signal lines lA/IAb and provide the sampled differential signals lAoi/IAboi. In this manner, by controlling the voltage levels of differential signal lines lA/IAb at each of the timeslots the voltage levels of the respective differential signals IA®o/IAb<so and lAoi/IAbon may be controlled.

[0081] For example, by causing the differential voltage to be at an appropriate weighting level for the connected column (e.g., ±V and ±2V) when connected, the weighting effect described above with respect to FIG. 11 may be achieved using commonly connected differential signal lines (lA/IAb).

[0082] Referring to FIG. 12, the SG circuitry for the bitO column is depicted as a pair of circuits SGOi and SGO2 responsive to a control signal <bo, and the SG circuitry for the bitl column is depicted as a pair of SG circuits SGI 1 and SGI2 responsive to a control signal <bi. The control signals 1 are used to connect, respectively the bitO column bit cells only during a bitO timeslot and the bitl column bit cells only during a bitl timeslot. The SG circuitry may be realized using any appropriate division or amplification circuitry. The purpose of the SG circuitry is to enable driving the positive and negative compute line capacitors CMBC of the column to an appropriate level during a respective timeslot and holding that appropriate level during the respective timeslots of other columns.

[0083] As shown in FIG. 13, and unlike the embodiments of FIG. 11, each of the bitO and bitl columns is associated with the same differential input activation (lA/IAb). However, the bit cells of the bitO column are configured to have a reduced voltage swing when compared to the bit cells of the bitl column. That is, the range of charging voltage applied to the positive and negative compute line capacitors is reduced by driving with a fixed voltage Vf, which for instance may be substantially ground (0V) or any other fixed voltage. It is noted that this “fixed’" voltage may be adjustable in various embodiments depending upon weighting, topology, and/or other considerations. For example, in some embodiments Vf may be set to 0V (GND), some other fixed voltage level, some voltage equating to a percentage of IA or lAb, and so on.

[0084] Referring to FIG. 13, it can be seen that for column bitO the transistor Ms couples the positive compute line capacitor to ground rather than differential signal line IA, and the transistor M7 couples the negative compute line capacitor to ground rather than differential signal line lAb. In this manner, the data stored in column bitO has the effect of allowing either no voltage swing on the capacitors or a voltage swing equal to lA/IAb on the capacitors coupled to the differential compute lines CLN/CLP, while the data stored in column bitl has the effect of allowing either a voltage swing of IA/I Ab or lAb/IA on the capacitors coupled to the differential compute lines CLN/CLP. Taking the signal on CLN/CLP as a differential signal, this makes the relative weight of the data stored in column bitO half that of the data stored in column bitl, in terms of its impact to the signal on CLN/CLP. [0085] The weighting mechanisms described above with respect to FIGS. 2B, 11, 12, and 13 may be used individually or in combination. For example, assuming eight binary weighted columns bitO-bit7, the mechanism of FIG. 2B would provide that the capacitors (CMBC) coupled to each of the differential compute lines (CLP/CLN) may be as follows: C (column bitO), 2C (column bitl), 4C (column bit2), ... 128C (column bit?).

[0086] If the bit cells of column bitO were provided as described in FIG. 13, then column bitO would be weighted at half of column bitl with the same capacitors (CMBC). That is, the capacitors (CMBC) coupled to each of the differential compute lines (CLP/CLN) may be as follows: C (column bitO), C (column bitl), 2C (column bit2), ... 64C (column bit?). This may comprise a sufficient savings in geometry depending upon application needs/requirements.

[0087] Generally speaking, the weighting mechanisms of FIGS. 11-13 provide architectures wherein each MBC column having a greater data weight than the data weight of an adjacent MBC column charges its respective positive and negative compute line capacitors at a greater voltage level than that of the adjacent MBC column.

[0088] The weighting mechanisms of FIG. 11 provide architectures wherein each MBC column is coupled to a respective differential signal line providing appropriate positive and negative compute line capacitor charging voltage levels.

[0089] The weighting mechanisms of FIG. 12 provide architectures wherein each MBC column is coupled to a common differential line via a respective SG circuitry during a respective time slot appropriate positive and negative compute line capacitor charging voltage levels.

[0090] The weighting mechanisms of FIG. 13 provide architectures wherein each MBC column having a lower data weight than the data weight of an adjacent MBC column charges its respective positive and negative compute line capacitors with a smaller voltage swing than that of the adj acent MBC column by reducing a range of charging voltage applied to the positive and negative compute line capacitors. That range of reduction may comprise limiting to substantially 0V the lower range of charging voltage applied to the positive compute line capacitors and the upper range of charging voltage applied to the negative compute line capacitors.

[0091] The above-described hardware/ architecture provides significant power savings, low latency, and tight architectural control wherein computation is performed directly in the various bit cells along with columnar scaling/weighting. [0092] Various modifications may be made to the systems, methods, apparatus, mechanisms, techniques and portions thereof described herein with respect to the various figures, such modifications being contemplated as being within the scope of the invention. For example, while a specific order of steps or arrangement of functional elements is presented in the various embodiments described herein, various other orders/arrangements of steps or functional elements may be utilized within the context of the various embodiments. Further, while modifications to embodiments may be discussed individually, various embodiments may use multiple modifications contemporaneously or in sequence, compound modifications and the like.

[0093] While specific systems, apparatus, methodologies, mechanisms and the like have been disclosed as discussed above, it should be apparent to those skilled in the art that many more modifications besides those already described are possible without departing from the inventive concepts herein. The inventive subject matter, therefore, is not to be restricted except in the spirit of the disclosure. Moreover, in interpreting the disclosure, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms "comprises" and "comprising" should be interpreted as referring to elements, components, or steps in a non-exclusive manner, indicating that the referenced elements, components, or steps may be present, or utilized, or combined with other elements, components, or steps that are not expressly referenced. In addition, the references listed herein are also part of the application and are incorporated by reference in their entirety as if fully set forth herein.

[0094] Although various embodiments which incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings. Thus, while the foregoing is directed to various embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof.

Claims

PRIN-97676 What is claimed is:

1. An integrated in-memory computing (IMC) hardware, comprising: an array of switched capacitor (SC) differential output multiplying bit-cells (MBCs) processing N bits per cycle, where N is a positive integer; each of a plurality of MBC columns within the MBC array has associated with it respective positive and negative compute lines to provide thereby a respective data-representative analog output signal based on a voltage difference between the respective positive and negative compute lines; each MBC within a column of MBCs having positive and negative compute line outputs configured to charge respective positive and negative compute line capacitors, the positive and negative compute line capacitors of the MBC being respectively coupled to the positive and negative compute lines of the respective MBC column.

2. The IMC hardware of claim 1, wherein the positive and negative compute lines are configured to be connected to a differential analog-to-digital converter (ADC).

3. The IMC hardware of claim 1. wherein the plurality of MBC columns within the MBC array comprises at least one group of two or more adjacent MBC columns, each MBC column being associated with a respective data weight to provide at least a most significant bit (MSB) column and a least significant bit (LSB) column.

4. The IMC hardware of claim 3, wherein each MBC column having a greater data weight than the data w eight of an adjacent MBC column comprises positive and negative compute line capacitors having a capacitance different than the capacitance of the positive and negative compute line capacitors of the adjacent MBC column.

5. The IMC hardware of claim 3, wherein each MBC column having a greater data weight than the data w eight of an adjacent MBC column charges its respective positive and negative compute line capacitors at a greater voltage level than that of the adjacent MBC column. PRIN-97676

6. The IMC hardware of claim 5, wherein each MBC column is coupled to respective differential signal lines providing appropriate positive and negative compute line capacitor charging voltage levels.

7. The IMC hardware of claim 5, wherein each MBC column is coupled to common differential signal lines via respective signal-gain circuitry during a respective time slot.

8. The IMC hardware of claim 5, wherein each MBC column having a lower data weight than the data weight of an adjacent MBC column charges its respective positive and negative compute line capacitors at a lower voltage level than that of the adjacent MBC column by reducing a range of charging voltage applied to the positive and negative compute line capacitors.

9. The IMC hardware of claim 8, wherein each MBC column having a lower data weight than the data weight of an adjacent MBC column uses its data to select between a fixed voltage for the charging voltage applied to the positive and negative compute line capacitors or the same charging voltages as its adjacent column for the charging voltage applied to the positive and negative compute line capacitors.

10. The IMC hardware of claim 3, wherein each MBC column having a greater data weight than an adjacent MBC column comprises positive and negative compute line capacitors of twice the capacitance of the positive and negative compute line capacitors of the adjacent MBC column.

11. The IMC hardware of claim 1 , wherein: the MBC array is configured as a differential MBC array having groups of two weighted column pairs cooperating to provide thereby respective groups of four cooperating binary weighted columns.

12. The IMC hardware of claim 1, wherein: the MBC array is configured as a differential MBC array having groups of four weighted column pairs cooperating to provide thereby respective groups of eight cooperating binary weighted columns. PRIN-97676

13. The IMC hardware of claim 11, wherein: each of the weighted columns of the second weighted column pairs includes switches therein configured to controllably exclude from the respective weighted column at least some of the plurality of coupled MBC outputs normally associated with the respected weighted column so as to reduce the data-representative analog output signals provided thereby.

14. The IMC hardware of claim 11, wherein at least the second of the two weighted column pairs are controllably coupled to respective inputs of respective differential ADCs via respective scaling circuits configured to reduce by half the data-representative analog output signals provided by the differential ADCs.

15. The IMC hardware of claim 11, wherein each weighted column group is connected to multiple differential ADCs, respective first weighted column pair differential ADC output data represents a full range input signal, and respective second weighted column pair differential ADC output data represents a partial range input signal.

16. The IMC hardware of claim 15, wherein each differential ADC operates over a different input range, and the ADC outputs can be used together to generate an appropriate digital representation of the analog output of a weighted column group.

17. The IMC hardware of claim 15, wherein the input ranges of the differential ADCs can be controllably varied.

18. The IMC hardware of claim 1, wherein each MBC comprises only NMOS-type switches.

19. An integrated in-memory computing (IMC) hardware, comprising: an array of switched capacitor (SC) output multiplying bit-cells (MBCs) processing N bits per cycle, where N is a positive integer; each of a plurality of MBC columns within the MBC array has associated with it respective compute lines configured to be coupled to an analog-to-digital converter (ADC) to provide thereby a respective data-representative analog output signal; PRIN-97676 each MBC within a column of MBCs having a compute line output configured to charge a respective compute line capacitor coupled to the compute line of the respective array column; wherein the plurality of MBC columns within the MBC array comprises at least one group of two or more adjacent MBC columns; each MBC column having a greater data weight than an adjacent MBC column comprising compute line capacitors of different capacitance of the compute line capacitors of the adjacent MBC column.

20. The IMC hardware of claim 19, wherein the positive and negative compute lines are configured to be connected to a differential analog-to-digital converter (ADC).

21. The IMC hardware of claim 19, wherein the plurality of MBC columns within the MBC array comprises at least one group of two or more adjacent MBC columns, each MBC column being associated with a respective data weight to provide at least a most significant bit (MSB) column and a least significant bit (LSB) column.

22. The IMC hardware of claim 21, wherein each MBC column having a greater data weight than the data w eight of an adjacent MBC column comprises positive and negative compute line capacitors having a capacitance different than the capacitance of the positive and negative compute line capacitors of the adjacent MBC column.

23. The IMC hardware of claim 21 , wherein each MBC column having a greater data weight than an adjacent MBC column comprises positive and negative compute line capacitors of twice the capacitance of the positive and negative compute line capacitors of the adjacent MBC column.

24. The IMC hardware of claim 19, wherein: the MBC array is configured as a differential MBC array having groups of at least two weighted column pairs cooperating to provide thereby respective groups of at least four cooperating binary weighted columns.

25. The IMC hardw are of claim 24, wherein: PRIN-97676 each of the weighted columns of the second weighted column pairs includes switches therein configured to controllably exclude from the respective weighted column at least some of the plurality of coupled MBC outputs normally associated with the respected weighted column so as to reduce the data-representative analog output signals provided thereby.