WO2025255872A1 - 一种氮化硅电荷俘获型忆阻器及其制备方法 - Google Patents

一种氮化硅电荷俘获型忆阻器及其制备方法

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Publication number
WO2025255872A1
WO2025255872A1 PCT/CN2024/102319 CN2024102319W WO2025255872A1 WO 2025255872 A1 WO2025255872 A1 WO 2025255872A1 CN 2024102319 W CN2024102319 W CN 2024102319W WO 2025255872 A1 WO2025255872 A1 WO 2025255872A1
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Prior art keywords
memristor
functional layer
trapping
traps
sin
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French (fr)
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程晓敏
冯少鹏
罗云皓
缪向水
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Huazhong University of Science and Technology
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/25—Multistable switching devices, e.g. memristors based on bulk electronic defects, e.g. trapping of electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/041—Modification of switching materials after formation, e.g. doping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides

Definitions

  • This application belongs to the field of microelectronic devices, and more specifically, relates to a silicon nitride charge-trapping memristor and its fabrication method.
  • conductive wire type memristors account for the majority. Their resistive switching principle is to form or melt conductive wires in resistive switching materials. When the conductive wire forms a path, the device becomes a low-resistance state, and when the conductive wire breaks, the device becomes a high-resistance state.
  • the main problems faced by this type of memristor are as follows: (1) The non-uniformity caused by the random growth of conductive wires in the device is the main obstacle to the large-scale manufacturing of memristors; (2) The device requires a high-voltage forming initialization process, which will cause the device to break down and fail, reducing the reliability of the memristor. This not only brings higher power consumption, but also increases the complexity of peripheral circuit design.
  • the purpose of this application is to provide a silicon nitride charge-trapping memristor and its fabrication method, aiming to solve the problems of poor consistency caused by the randomness of conductive wire growth and the need for high-voltage forming in traditional conductive wire memristors.
  • this application provides a silicon nitride charge-trapping memristor, which sequentially includes a substrate, a lower electrode, a functional layer and an upper electrode, wherein the functional layer is configured as three layers, wherein the upper and lower layers are SiO2 and the middle layer is SiNX ;
  • the memristor is processed using a low-temperature annealing process, which forms silicon dangling bonds in the SiNX functional layer. These silicon dangling bonds act as traps for trapping and releasing charges.
  • the memristor utilizes the trapping and releasing mechanism of charges within the SiNX traps to achieve changes in resistance.
  • an application is applied between the upper and lower electrodes... Under a positive voltage, charges flow from the lower electrode to the upper electrode under the influence of the electric field.
  • the charges flow through the SiNX functional layer they are gradually captured by the traps in the SiNX , and the resistance of the memristor gradually decreases. When the traps are filled, the resistance of the memristor drops to its lowest value.
  • the SiO2 is used to increase the potential barrier difference between the functional layer and the upper and lower electrodes, and to buffer the process of charge being captured and released by SiNX traps.
  • the thickness of SiN X is less than or equal to 20 nm, and the thickness of SiO 2 is less than or equal to 10 nm.
  • the material of the upper electrode and the upper electrode is Pt, Ti, W, Au, Ru, Al, Hf, Ta or TiN.
  • the memristor can obtain stable multi-value storage characteristics by applying different magnitudes of DC or pulse voltages between its upper and lower electrodes; the memristor can achieve pulsed collision characteristics of long-term enhancement and long-term suppression by continuously applying pulse voltages between its upper and lower electrodes.
  • this application provides a method for fabricating a silicon nitride charge-trapping memristor as described above, comprising the following steps:
  • step S50 the device prepared in step S40 is placed in an annealing furnace for low-temperature annealing process, so that SiN X in the functional layer forms silicon dangling bonds, which are traps for capturing and releasing charges.
  • the annealing temperature in the low-temperature annealing process is controlled at 200–500°C, and the annealing time is 500–2500 seconds.
  • the functional layer is prepared by chemical vapor deposition or physical vapor deposition.
  • both the upper electrode and the lower electrode are prepared by physical vapor deposition or chemical vapor deposition.
  • the upper electrode is patterned on the functional layer using photolithography.
  • the functional layer adopts a three-layer structure of SiO2 / SiNX / SiO2 .
  • the resistance change of the memristor is achieved by trapping and releasing the charge of the silicon dangling bonds formed by SiNX through a low-temperature annealing process.
  • This resistance change process does not have the randomness problem of conductive filament growth, so there is no large voltage forming process, which is conducive to reducing the power consumption of the memristor and the complexity of the peripheral circuit design, improving the reliability of the device, and having high consistency.
  • the memristor provided in this application can have multiple conduction states by applying DC or pulse voltages of different magnitudes to the electrodes, thus achieving stable multi-resistance value retention.
  • pulse collision characteristics such as long-term enhancement and long-term suppression can be achieved, which has the potential for in-memory computing integration applications.
  • Figure 1 is a schematic diagram of the silicon nitride charge-trapping memristor provided in this application;
  • Figure 2 is a flowchart of the fabrication method of the silicon nitride charge-trapping memristor provided in this application;
  • Figure 3 is a schematic diagram of the energy band structure of a silicon nitride charge-trapping memristor provided in a specific embodiment of this application;
  • Figure 4 is an IV curve of the silicon nitride charge-trapping memristor provided in a specific embodiment of this application after the first to 100 consecutive DC voltage scans.
  • Figure 5 is a multi-resistance retention performance diagram of the silicon nitride charge-trapping memristor provided in a specific embodiment of this application;
  • Figure 6 is a graph showing the change in conductivity of a silicon nitride charge-trapping memristor provided in a specific embodiment of this application when 104 pulse voltages are applied.
  • the term “several” means at least one, such as one, two, etc., unless otherwise expressly and specifically defined; the term “multiple” means two or more, unless otherwise expressly and specifically defined; the terms “first” and “second,” etc., are used to distinguish different objects, not to describe a specific order of objects; the term “and/or” includes any and all combinations of one or more of the related listed items.
  • references to “an embodiment”; “an embodiment,” “an example,” or similar language indicate that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this application. Therefore, the appearance of the phrase “in one embodiment;” throughout this specification, and similar language, may, but not necessarily, refer to the same embodiment.
  • FIG. 1 is a schematic diagram of the structure of the silicon nitride charge-trapping memristor provided in this application. As shown in Figure 1, the memristor sequentially includes a substrate 100, a lower electrode 101, a functional layer, and an upper electrode 105.
  • the substrate 100 can be made of materials commonly used in the art, such as Si or SiO2 , and this application does not impose any restrictions.
  • the upper electrode 101 and the lower electrode 105 can be made of conductive materials such as Pt, Ti, W, Au, Ru, Al, Hf, Ta or TiN, and this application does not impose any restrictions.
  • the functional layer has a three-layer structure: the upper layer 104 and the lower layer 102 are both SiO2 , and the middle layer 103 is SiNX .
  • SiNX is the core resistive switching material of the functional layer.
  • the above-mentioned memristor structure needs to be treated by a low-temperature annealing process to form silicon dangling bonds in the SiN X in the functional layer. These silicon dangling bonds are traps for capturing and releasing charges.
  • the memristor provided in this application utilizes the trapping and releasing mechanism of charge in SiN2X traps to achieve resistance changes. Specifically, when a positive voltage is applied between the upper and lower electrodes (i.e., a negative bias is applied to the lower electrode and the upper electrode is grounded), the charge flows from the lower electrode to the upper electrode under the influence of the electric field. As the charge flows through the SiN2X in the functional layer, it is gradually trapped by the traps in SiN2X , causing the resistance of the memristor to gradually decrease. When the traps in SiN2X are filled, the resistance of the memristor drops to its lowest value.
  • the addition of two SiO2 layers is used to increase the potential barrier difference between the functional layer and the upper and lower electrodes, buffering the process of charge being captured and released by SiNX traps. This buffering effect enables the memristor to perform analog resistance switching, thereby realizing the pulsed contact function.
  • the memristor provided in this application can change the amount of charge trapped in the functional layer by adjusting the voltage applied to the electrodes. Different amounts result in different resistance values of the device. Applying different magnitudes or numbers of DC or pulse voltages to the electrodes can achieve stable multi-resistance retention. By continuously applying pulse voltages to the electrodes, pulsed collision characteristics such as long-term enhancement and long-term suppression can be achieved. This characteristic is an important biological learning mechanism.
  • the SiN X layer thickness in the functional layer provided in this application is less than or equal to 20 nm, and the SiO 2 layer thickness is less than or equal to 10 nm.
  • the functional layer within this thickness range can achieve the effect of subsequent stable charge trapping. Beyond this range, it exhibits insulation and cannot resist switching.
  • this application also provides a method for fabricating the aforementioned silicon nitride charge-trapping memristor, as shown in Figure 2, including steps S10 to S50, detailed below:
  • the substrate may be made of Si/ SiO2 material.
  • the lower electrode can be prepared by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • the functional layer is set to three layers, of which the top and bottom layers are SiO2 and the middle layer is SiNX .
  • the functional layer can be prepared by chemical vapor deposition or physical vapor deposition.
  • the upper electrode can be fabricated using physical vapor deposition or chemical vapor deposition.
  • the upper electrode can be patterned on the functional layer using photolithography.
  • step S50 the device prepared in step S40 is placed in an annealing furnace for low-temperature annealing, so that SiN X in the functional layer forms silicon dangling bonds, which are traps for capturing and releasing charges.
  • the device prepared in step S40 can be annealed in an annealing furnace under an N2 atmosphere or in a vacuum environment, which is not limited in this application.
  • the annealing temperature in the low-temperature annealing process can be controlled between 200°C and 500°C, and the annealing time can be between 500 seconds and 2500 seconds.
  • the functional layer adopts a three-layer structure of SiO2 / SiNX / SiO2 .
  • the resistance change of the memristor is achieved by trapping and releasing the charge of the silicon dangling bonds formed by SiNX through a low-temperature annealing process.
  • This resistance change process does not have the randomness problem of conductive filament growth, so there is no large voltage forming process, which is conducive to reducing the power consumption of the memristor and the complexity of the peripheral circuit design, improving the reliability of the device, and having high consistency.
  • the memristor provided in this application can have multiple conduction states by applying DC or pulse voltages of different magnitudes to the electrodes, thus achieving stable multi-resistance value retention.
  • pulse collision characteristics such as long-term enhancement and long-term suppression can be achieved, which has the potential for in-memory computing integration applications.
  • the silicon nitride charge-trapping memristor and its fabrication method provided in this specific embodiment have a device structure of Ti/ SiO2 / SiNX / SiO2 /Pt, wherein the lower electrode is Pt, the functional layer is a three-layer stacked structure of SiO2 / SiNX / SiO2 , and the upper electrode is Ti.
  • the specific fabrication process is as follows (substrate cleaning process is not described):
  • (2) DC magnetron sputtering was performed on the substrate with a power of 100W, an argon flow rate of 60sccm, and a gas pressure of 0.5Pa.
  • the target material was metallic Ti, and a Ti electrode with a thickness of 5-10nm was deposited as an adhesion layer.
  • the power was set to 40-60W
  • the gas pressure was 0.5Pa
  • the argon flow rate was 60sccm
  • the target material was Pt
  • a Pt electrode with a thickness of 50-120nm was deposited.
  • a 2 nm SiO2 thin film was deposited on the Pt electrode using plasma-enhanced chemical vapor deposition (PECVD) at a deposition temperature of 300 °C and a reaction pressure of 850 mTorr.
  • the reaction gas source was 5% SiH4 / N2 , N2 , and N2O .
  • a 6 nm SiNX thin film was deposited on the SiO2 thin film using PECVD at a deposition temperature of 300 °C and a reaction pressure of 1000 mTorr.
  • the reaction gas source was 5% SiH4 / N2 , NH3 , and N2 .
  • a 3 nm SiO2 thin film was deposited on the SiNX thin film using PECVD at a deposition temperature of 300 °C and a reaction pressure of 850 mTorr.
  • the reaction gas source was 5% SiH4 / N2 , N2 , and N2O .
  • the upper electrode pattern is lithographically patterned on the functional layer using ultraviolet lithography and prepared through six processes: homogenization, pre-baking, pre-exposure, post-baking, post-exposure, and development.
  • DC magnetron sputtering power 100W, argon flow rate 60sccm, gas pressure maintained at 0.5Pa
  • target material is metallic Ti
  • the upper electrode is square, with dimensions of 50 ⁇ m ⁇ 50 ⁇ m, 100 ⁇ m ⁇ 100 ⁇ m, 200 ⁇ m ⁇ 200 ⁇ m, 300 ⁇ m ⁇ 300 ⁇ m respectively;
  • step (7) Place the device prepared in step (6) into an annealing furnace and anneal it in a nitrogen atmosphere at a temperature of 350°C for 1200 seconds.
  • a Ti/3nm SiO2 /6nm SiNX /2nm SiO2 /Pt memristor is fabricated.
  • a negative bias is applied to the lower Pt electrode and the upper electrode is grounded, charges pass through the SiO2 layer from the Pt electrode into the SiNX layer under the influence of the electric field, and are subsequently trapped in the traps within the SiNX layer .
  • the memristor gradually transitions to a low-resistance state.
  • a positive bias is applied to the lower Pt electrode and the upper electrode is grounded, charges are released from the traps under the influence of the electric field and flow from the SiNX layer through the SiO2 layer to the Pt electrode.
  • the memristor gradually transitions to a high-resistance state.
  • Figure 3 is a schematic diagram of the energy band of the Ti/ SiO2 / SiNX / SiO2 /Pt memristor provided in this specific embodiment.
  • the potential barrier differences between the Ti and Pt electrodes and SiNX are 2.5 eV and 3.8 eV, respectively, and the potential barrier differences between the Ti and Pt electrodes and SiO2 are 3.35 eV and 4.65 eV, respectively.
  • the addition of two layers of SiO2 increases the potential barrier difference between the functional layer and the upper and lower electrodes, hindering the process of charge being trapped and released by SiNx traps. This buffering effect causes the device resistance to gradually change.
  • Figure 4 is the IV curve of the Ti/ SiO2 / SiNX / SiO2 /Pt memristor provided in this specific embodiment after the 1st to 100th continuous DC voltage scans.
  • the voltage scan range is controlled between -2 and 3V. It can be seen that the memristor has no forming process and the operating voltage is low. According to statistics, the coefficient of variation of the SET voltage is 4.8% and the coefficient of variation of the RESET voltage is 2.1%. The low coefficient of variation proves that the memristor has high consistency.
  • Figure 5 shows the multi-value retention performance of the Ti/ SiO2 / SiNX / SiO2 /Pt memristor provided in this specific embodiment at a high temperature of 85°C.
  • the memristor can stably maintain 12 resistive states, which is of great significance for improving the storage capacity of the memristor.
  • Figure 6 shows the conductance changes of the Ti/ SiO2 / SiNX / SiO2 /Pt memristor provided in this specific embodiment after applying 104 pulse voltages.
  • the continuous long-term enhancement and suppression characteristics are almost unchanged compared to the initial state, demonstrating a very stable and reliable neural synaptic function, indicating that the memristor has the potential for in-memory computing applications.

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Abstract

本申请公开了一种氮化硅电荷俘获型忆阻器及其制备方法，其中，该忆阻器中的功能层设置为三层，上下两层为SiO2，中间层为SiNX；忆阻器通过低温退火工艺处理，使得功能层中的SiNX形成硅悬挂键，硅悬挂键为俘获和释放电荷的陷阱；忆阻器利用电荷在SiNX陷阱中的俘获和释放机制实现电阻的变化。本申请提供的忆阻器没有导电丝随机性生长带来的一致性问题，且不需要大电压Forming过程，具有较高的一致性和应用前景；并且该忆阻器可实现可靠的多值存储和脉冲突触特性；另外，采用氮化硅作为核心阻变材料，具有成本低、易获取、与CMOS工艺更加兼容的优点。

Description

一种氮化硅电荷俘获型忆阻器及其制备方法 技术领域
本申请属于微电子器件领域，更具体地，涉及一种氮化硅电荷俘获型忆阻器及其制备方法。
背景技术
在当前的研究中，导电丝型忆阻器占大多数，其阻变原理是在阻变材料中形成或熔断导电丝，导电丝形成通路时器件变为低阻态，导电丝断裂时器件变为高阻态，然而此类型的忆阻器面临的主要问题如下：(1)器件中导电丝随机性生长带来的非一致性是忆阻器大规模制造的主要障碍；(2)器件需要大电压Forming初始化过程，会造成器件击穿而失效，降低忆阻器可靠性，不仅带来较高的功耗，还增加了外围电路设计的复杂度。
发明内容
针对现有技术的缺陷，本申请的目的在于提供一种氮化硅电荷俘获型忆阻器及其制备方法，旨在解决传统导电丝型忆阻器的导电丝生长随机性带来的一致性差以及需要大电压Forming的问题。
为实现上述目的，第一方面，本申请提供了一种氮化硅电荷俘获型忆阻器，依次包括衬底、下电极、功能层及上电极，所述功能层设置为三层，其中上下两层为SiO2，中间层为SiNX；
所述忆阻器通过低温退火工艺处理，使得功能层中的SiNX形成硅悬挂键，所述硅悬挂键为俘获和释放电荷的陷阱；所述忆阻器利用电荷在SiNX陷阱中的俘获和释放机制实现电阻的变化，当在上电极和下电极之间施加 正向电压时，电荷在电场的作用下从下电极流向上电极，电荷流经功能层中SiNX时逐渐被SiNX中的陷阱俘获，忆阻器的阻值逐渐降低，当陷阱填满时忆阻器的阻值降到最低；当在上电极和下电极之间施负向电压时，电荷逐渐被SiNX中的陷阱释放，流向下电极，忆阻器的阻值逐渐升高，当陷阱中的电荷全部释放时忆阻器的阻值升到最高；
其中，所述SiO2用于增大功能层与上、下电极之间的势垒差，缓冲电荷被SiNX陷阱俘获和释放的过程。
作为进一步优选的，在所述功能层中，所述SiNX的厚度小于或等于20nm，所述SiO2的厚度小于或等于10nm。
作为进一步优选的，所述上电极和上电极的材料采用Pt、Ti、W、Au、Ru、Al、Hf、Ta或TiN。
作为进一步优选的，所述忆阻器通过对其上电极和下电极之间施加不同大小的直流或脉冲电压，可获得稳定的多值存储特性；所述忆阻器通过对其上电极和下电极之间连续施加脉冲电压，可实现长时程增强和长时程抑制的脉冲突触特性。
第二方面，本申请提供了一种如上述所述的氮化硅电荷俘获型忆阻器的制备方法，包括如下步骤：
S10，准备衬底；
S20，在所述衬底上沉积下电极；
S30，在所述下电极上沉积功能层，所述功能层设置为三层，其中上下两层为SiO2，中间层为SiNX；
S40，在所述功能层上沉积并图形化上电极；
S50，将步骤S40制备的器件放入退火炉中进行低温退火工艺处理，使得功能层中的SiNX形成硅悬挂键，所述硅悬挂键为俘获和释放电荷的陷阱。
作为进一步优选的，步骤S50中，低温退火工艺中的退火温度控制在200～500℃，退火时间为500～2500秒。
作为进一步优选的，所述功能层采用化学气相沉积法或物理气相沉积法制备而成。
作为进一步优选的，所述上电极和下电极均采用物理气相沉积法或化学气相沉积法制备而成。
作为进一步优选的，采用光刻技术在所述功能层上图形化上电极。
本申请提供的氮化硅电荷俘获型忆阻器及其制备方法，具有如下效果：
(1)功能层采用SiO2/SiNX/SiO2三层结构，通过低温退火工艺使SiNX形成的硅悬挂键俘获和释放电荷来实现忆阻器的电阻变化，该阻变过程无导电丝生长随机性问题，因此无大电压Forming过程，有利于降低忆阻器工作的功耗和外围电路设计复杂度，提高器件可靠性，具有高的一致性；
(2)利用硅悬挂键俘获和释放电荷来完成阻变，可使得本申请提供的忆阻器通过对电极施加大小不同的直流或脉冲电压，能使忆阻器有多个电导态，实现稳定的多阻值保持性；另外，对电极连续施加脉冲电压，可实现长时程增强和长时程抑制等脉冲突触特性，具有存算融合应用的潜力；
(3)使用SiNX作为核心阻变材料，与传统离子迁移型忆阻器阻变材料相比，具有成本低、易获取、与CMOS工艺更加兼容的优点；而且本申请提供的制备方法适用于CVD、PVD等量产设备及工艺，具有更好的大规模量产前景。
附图说明
图1是本申请提供的氮化硅电荷俘获型忆阻器的结构示意图；
图2是本申请提供的氮化硅电荷俘获型忆阻器的制备方法的流程图；
图3是本申请具体实施例提供的氮化硅电荷俘获型忆阻器的能带示意图；
图4是本申请具体实施例提供的氮化硅电荷俘获型忆阻器经过第1～100次连续直流电压扫描下的I-V曲线图；
图5是本申请具体实施例提供的氮化硅电荷俘获型忆阻器的多阻值保持性能图；
图6是本申请具体实施例提供的氮化硅电荷俘获型忆阻器施加104个脉冲电压的电导值变化图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需要理解的是，在本申请的描述中，术语“若干”的含义是至少一个，例如一个，两个等，除非另有明确具体的限定；术语“多个”的含义是两个或两个以上，除非另有明确具体的限定；术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序；术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
另外，贯穿本说明书对“一个实施例”的引用；“一个实施例”、“一个示例”或类似的语言表示结合该实施例描述的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，短语“在一个实施例中；”的出现贯穿本说明书的“在一个实施例中”和类似的语言可能但不一定都指代相同的实施例。
为解决传统导电丝型忆阻器的导电丝生长随机性带来的一致性差和需要大电压Forming的问题，本申请提供了一种氮化硅电荷俘获型忆阻器，图1是本申请提供的氮化硅电荷俘获型忆阻器的结构示意图，如图1所示，该忆阻器依次包括衬底100、下电极101、功能层及上电极105。
其中，衬底100可采用本领域常用的材料制成，比如Si或SiO2材料等材料制成，本申请不作限制。上电极101和下电极105可采用Pt、Ti、W、Au、Ru、Al、Hf、Ta或TiN等导电材料制成，本申请不作限制。
功能层的结构为三层：上层104和下层102均为SiO2，中间层103为SiNX，SiNX为功能层核心阻变材料。
上述忆阻器结构在使用前，需对其通过低温退火工艺处理，使得功能层中的SiNX形成硅悬挂键，该硅悬挂键为俘获和释放电荷的陷阱。
本申请提供的忆阻器利用电荷在SiNX陷阱中的俘获和释放机制实现电阻的变化，即当在上电极和下电极之间施加正向电压(即在下电极施加负偏压，上电极接地)时，电荷在电场的作用下从下电极流向上电极，电荷流经功能层中SiNX时逐渐被SiNX中的陷阱俘获，使得忆阻器的阻值逐渐降低，当SiNX中的陷阱填满时忆阻器的阻值降到最低；当在上电极和下电极之间施负向电压(即在下电极施加正偏压，上电极接地)时，电荷逐渐被SiNX中的陷阱释放，流向上电极，忆阻器的阻值逐渐升高，当陷阱中的电荷全部释放时忆阻器的阻值升到最高。
在功能层中，两层SiO2的加入用于增大功能层与上、下电极之间的势垒差，缓冲电荷被SiNX陷阱俘获和释放的过程，这种缓冲作用可使得忆阻器进行模拟型阻变，进而实现脉冲突触功能。
具体地，本申请提供的忆阻器可通过调节对电极施加的电压改变功能层俘获的电荷数量，数量不同导致器件的电阻值不同，对电极施加不同大小或不同数量的直流或脉冲电压可实现稳定的多阻值保持性；通过对电极连续施加脉冲电压，可以实现长时程增强和长时程抑制等脉冲突触特性，该特性是重要的生物学习机制。
优选地，本申请提供的功能层中的SiNX层厚度小于或等于20nm，SiO2层厚度小于或等于10nm，在此厚度范围内的功能层能达到后续稳定俘获电荷的效果，超出此范围表现出绝缘性且无法阻变。
此外，本申请还提供了一种面向上述氮化硅电荷俘获型忆阻器的制备方法，如图2所示，包括步骤S10～S50，详述如下：
S10，准备衬底。
在步骤S10中，衬底可采用Si/SiO2材料。
S20，在衬底上沉积下电极。
在步骤S20中，下电极可采用物理气相沉积法(PVD)或化学气相沉积法(CVD)制备而成。
S30，在下电极上沉积功能层，功能层设置为三层，其中上下两层为SiO2，中间层为SiNX。
在步骤S30中，功能层可采用化学气相沉积法或物理气相沉积法制备而成。
S40，在功能层上沉积并图形化上电极。
在步骤S40中，上电极可采用物理气相沉积法或化学气相沉积法制备而成。在功能层上可采用光刻技术图形化上电极。
S50，将步骤S40制备的器件放入退火炉中进行低温退火工艺处理，使得功能层中的SiNX形成硅悬挂键，硅悬挂键为俘获和释放电荷的陷阱。
具体地，步骤S40制备的器件可在退火炉中N2氛围下或真空环境下进行退火，本申请不作限制。为更好地使得功能层中的SiNX形成硅悬挂键，低温退火工艺中的退火温度可控制在200℃～500℃，退火时间为500秒～2500秒。
本申请提供的氮化硅电荷俘获型忆阻器及其制备方法，具有如下效果：
(1)功能层采用SiO2/SiNX/SiO2三层结构，通过低温退火工艺使SiNX形成的硅悬挂键俘获和释放电荷来实现忆阻器的电阻变化，该阻变过程无导电丝生长随机性问题，因此无大电压Forming过程，有利于降低忆阻器工作的功耗和外围电路设计复杂度，提高器件可靠性，具有高的一致性；
(2)利用硅悬挂键俘获和释放电荷来完成阻变，可使得本申请提供的忆阻器通过对电极施加大小不同的直流或脉冲电压，能使忆阻器有多个电导态，实现稳定的多阻值保持性；另外，对电极连续施加脉冲电压，可实现长时程增强和长时程抑制等脉冲突触特性，具有存算融合应用的潜力；
(3)使用SiNX作为核心阻变材料，与传统离子迁移型忆阻器阻变材料相比，具有成本低、易获取、与CMOS工艺更加兼容的优点；而且本申请提供的制备方法适用于CVD、PVD等量产设备及工艺，具有更好的大规模量产前景。
下面结合具体实施例对本申请提供的氮化硅电荷俘获型忆阻器及其制备方法进行详细说明。
本具体实施例提供的氮化硅电荷俘获型忆阻器及其制备方法，器件结构为Ti/SiO2/SiNX/SiO2/Pt，其中下电极为Pt，功能层为SiO2/SiNX/SiO2的三层叠加结构，上电极为Ti，具体制备工艺流程如下(未描述衬底清洗过程)：
(1)提前准备好Si/SiO2衬底；
(2)在衬底上直流磁控溅射，功率100W，氩气流量60sccm，气压维持在0.5Pa，靶材为金属Ti，沉积5～10nm厚度的Ti电极作为黏附层；随后功率设为40～60W，气压0.5Pa，氩气流量60sccm，靶材为Pt，沉积50～120nm厚度的Pt电极；
(3)使用等离子体增强化学气相沉积法(PECVD)在Pt电极上面沉积2nm SiO2薄膜，沉积温度为300℃，反应压力为850mTorr，反应气源为5％SiH4/N2、N2、N2O；随后使用PECVD法在SiO2薄膜上沉积6nm SiNX薄膜，沉积温度为300℃，反应压力为1000mTorr，反应气源为5％ SiH4/N2、NH3、N2；随后使用PECVD法在SiNX上面沉积3nm SiO2薄膜，沉积温度为300℃，反应压力为850mTorr，反应气源为5％ SiH4/N2、N2、N2O。
(4)采用紫外光刻技术在功能层上光刻出上电极图形，通过匀胶、前烘、前曝、后烘、后爆、显影等六个过程制备；
(5)直流磁控溅射，功率100W，氩气流量60sccm，气压维持在0.5Pa，靶材为金属Ti，沉积50～120nm厚度的Ti电极，上电极为方块状，尺寸分别为50μm×50μm、100μm×100μm、200μm×200μm、300μm×300μm；
(6)将步骤(5)所制备出的样品放在丙酮中浸泡15～30分钟，再用 无水乙醇和去离子水清洗，用氮气吹干；
(7)将步骤(6)制备出的器件放入退火炉中，在氮气的气氛下退火，温度设置为350℃，保持时间1200秒。
完成上述步骤后即制备出了Ti/3nm SiO2/6nm SiNX/2nm SiO2/Pt忆阻器。当对Pt下电极施加负偏压，上电极接地时，电荷在电场作用从Pt电极穿过SiO2层进入SiNX中，随后被SiNX中的陷阱俘获，此时忆阻器逐渐转换为低阻态；当对Pt下电极施加正偏压，上电极接地时，电荷在电场作用下从陷阱中释放，从SiNX穿过SiO2层流向Pt电极，此时忆阻器逐渐转换为高阻态。
图3是本具体实施例提供的Ti/SiO2/SiNX/SiO2/Pt忆阻器能带示意图，Ti和Pt电极与SiNX的势垒差分别为2.5eV和3.8eV，Ti和Pt电极与SiO2的势垒差为3.35eV和4.65eV，两层SiO2的加入增大了功能层与上、下电极之间的势垒差，阻碍了电荷被SiNx陷阱俘获和释放的过程，这种缓冲作用使器件电阻逐渐转变。
图4是本具体实施例提供的Ti/SiO2/SiNX/SiO2/Pt忆阻器经过第1～100次连续直流电压扫描下的I-V曲线图，电压扫描范围控制在-2～3V之间，可以看出该忆阻器无Forming过程，且操作电压较低，经统计，SET电压的变异系数为4.8％，RESET电压的变异系数为2.1％，低的变异系数证明了该忆阻器的一致性高。
图5是本具体实施例提供的Ti/SiO2/SiNX/SiO2/Pt忆阻器在85℃的高温下的多值保持性能图，该忆阻器能稳定保持的12个阻态，这对提升忆阻器的存储容量具有重要意义。
图6是本具体实施例提供的Ti/SiO2/SiNX/SiO2/Pt忆阻器施加104个脉冲电压的电导值变化图，连续的长时程增强和抑制特性与初始相比几乎没有变化，展现了十分稳定可靠的神经突触功能，表明该忆阻器具有存算一体应用的潜力。
本领域的技术人员容易理解，以上所述仅为本申请的较佳实施例，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (9)

  1. 一种氮化硅电荷俘获型忆阻器，其特征在于，依次包括衬底、下电极、功能层及上电极，所述功能层设置为三层，其中上下两层为SiO2，中间层为SiNX；
    所述忆阻器通过低温退火工艺处理，使得功能层中的SiNX形成硅悬挂键，所述硅悬挂键为俘获和释放电荷的陷阱；所述忆阻器利用电荷在SiNX陷阱中的俘获和释放机制实现电阻的变化，当在上电极和下电极之间施加正向电压时，电荷在电场的作用下从下电极流向上电极，电荷流经功能层中SiNX时逐渐被SiNX中的陷阱俘获，忆阻器的阻值逐渐降低，当陷阱填满时忆阻器的阻值降到最低；当在上电极和下电极之间施负向电压时，电荷逐渐被SiNX中的陷阱释放，流向下电极，忆阻器的阻值逐渐升高，当陷阱中的电荷全部释放时忆阻器的阻值升到最高；
    其中，所述SiO2用于增大功能层与上、下电极之间的势垒差，缓冲电荷被SiNX陷阱俘获和释放的过程。
  2. 如权利要求1所述的氮化硅电荷俘获型忆阻器，其特征在于，在所述功能层中，所述SiNX的厚度小于或等于20nm，所述SiO2的厚度小于或等于10nm。
  3. 如权利要求1或2所述的氮化硅电荷俘获型忆阻器，其特征在于，所述上电极和上电极的材料采用Pt、Ti、W、Au、Ru、Al、Hf、Ta或TiN。
  4. 如权利要求1或2所述的氮化硅电荷俘获型忆阻器，其特征在于，所述忆阻器通过对其上电极和下电极之间施加不同大小的直流或脉冲电压，可获得稳定的多值存储特性；所述忆阻器通过对其上电极和下电极之间连续施加脉冲电压，可实现长时程增强和长时程抑制的脉冲突触特性。
  5. 一种如权利要求1所述的氮化硅电荷俘获型忆阻器的制备方法，其特征在于，包括如下步骤：
    S10，准备衬底；
    S20，在所述衬底上沉积下电极；
    S30，在所述下电极上沉积功能层，所述功能层设置为三层，其中上下两层为SiO2，中间层为SiNX；
    S40，在所述功能层上沉积并图形化上电极；
    S50，将步骤S40制备的器件放入退火炉中进行低温退火工艺处理，使得功能层中的SiNX形成硅悬挂键，所述硅悬挂键为俘获和释放电荷的陷阱。
  6. 如权利要求5所述的氮化硅电荷俘获型忆阻器的制备方法，其特征在于，步骤S50中，低温退火工艺中的退火温度控制在200～500℃，退火时间为500～2500秒。
  7. 如权利要求5所述的氮化硅电荷俘获型忆阻器的制备方法，其特征在于，所述功能层采用化学气相沉积法或物理气相沉积法制备而成。
  8. 如权利要求5所述的氮化硅电荷俘获型忆阻器的制备方法，其特征在于，所述上电极和下电极均采用物理气相沉积法或化学气相沉积法制备而成。
  9. 如权利要求5所述的氮化硅电荷俘获型忆阻器的制备方法，其特征在于，采用光刻技术在所述功能层上图形化上电极。
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Citations (3)

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Publication number Priority date Publication date Assignee Title
CN107634140A (zh) * 2017-09-12 2018-01-26 电子科技大学 基于SiNx的光读取神经突触器件结构及其制备方法
KR20220010800A (ko) * 2020-07-20 2022-01-27 한국과학기술연구원 아날로그 시냅스 동작을 제공하는 비정질 실리콘 층 및 유전체 층을 포함하는 다층 멤리스터 장치
CN117457481A (zh) * 2023-11-09 2024-01-26 上海积塔半导体有限公司 Ono堆叠层的制造方法及非易失性存储器的制造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107634140A (zh) * 2017-09-12 2018-01-26 电子科技大学 基于SiNx的光读取神经突触器件结构及其制备方法
KR20220010800A (ko) * 2020-07-20 2022-01-27 한국과학기술연구원 아날로그 시냅스 동작을 제공하는 비정질 실리콘 층 및 유전체 층을 포함하는 다층 멤리스터 장치
CN117457481A (zh) * 2023-11-09 2024-01-26 上海积塔半导体有限公司 Ono堆叠层的制造方法及非易失性存储器的制造方法

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