WO2025251503A1 - 叠接型转换器 - Google Patents

叠接型转换器

Info

Publication number
WO2025251503A1
WO2025251503A1 PCT/CN2024/127231 CN2024127231W WO2025251503A1 WO 2025251503 A1 WO2025251503 A1 WO 2025251503A1 CN 2024127231 W CN2024127231 W CN 2024127231W WO 2025251503 A1 WO2025251503 A1 WO 2025251503A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch
capacitor
turned
inductor
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/127231
Other languages
English (en)
French (fr)
Inventor
林鸿杰
谢奕平
黄进忠
黄弘宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Delta Electronics Inc
Original Assignee
Delta Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delta Electronics Inc filed Critical Delta Electronics Inc
Publication of WO2025251503A1 publication Critical patent/WO2025251503A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels

Definitions

  • This invention relates to a stacked converter, and more particularly to a stacked converter with component-saving and structurally simple features.
  • Figure 1 is a circuit block diagram of a first embodiment of a conventional dual-capacitor stacked converter.
  • the circuit requires at least one inductor L1 and two switches S1 and S2 .
  • Figure 2 is a circuit block diagram of a second embodiment of a conventional dual-capacitor stacked converter.
  • the circuit requires at least three inductors L1 , L2 , and L3 and six switches S1 , S2 , S3 , S4 , S5 , and S6 to maintain the required voltage.
  • conventional dual-capacitor stacked converters contain a large number of components, they suffer from disadvantages such as excessive circuit size, high cost, and difficulty in improving power density.
  • the stacked converter includes four capacitors, four switches, a fifth switch and a first inductor, a sixth switch and a second inductor, and a seventh switch.
  • the four capacitors include a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor connected in series.
  • the first and second capacitors are connected together at a first node
  • the second and third capacitors are connected together at a second node
  • the third and fourth capacitors are connected together at a third node.
  • the first capacitor is also connected to a first voltage node
  • the fourth capacitor is also connected to a second voltage node.
  • the four switches include a first switch, a second switch, a third switch, and a fourth switch connected in series.
  • the first and second switches are connected together at a fourth node, the second and third switches are connected together at a second node, and the third and fourth switches are connected together at a fifth node.
  • the first switch is also connected to a first voltage node, and the fourth switch is also connected to a second voltage node.
  • the fifth switch and the first inductor are connected together at a sixth node, and the fifth switch is also connected to a first node, while the first inductor is also connected to a fourth node.
  • the sixth switch and the second inductor are connected together at a seventh node, and the sixth switch is also connected to a third node, while the second inductor is also connected to a fifth node.
  • the seventh switch is connected between the sixth and seventh nodes.
  • the stacked converter includes four capacitors, four switches, a fifth switch and a first inductor, a sixth switch and a second inductor, and a diode.
  • the four capacitors include a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor connected in series, wherein the first and second capacitors are connected together at a first node, the second and third capacitors are connected together at a second node, and the third and fourth capacitors are connected together at a third node.
  • the first capacitor is also connected to a first voltage node
  • the fourth capacitor is also connected to a second voltage node.
  • the four switches include a first switch, a second switch, a third switch, and a fourth switch connected in series.
  • the system includes a fourth switch, where the first and second switches are shared at the fourth node, the second and third switches are shared at the second node, and the third and fourth switches are shared at the fifth node.
  • the first switch is also connected to the first voltage node, and the fourth switch is also connected to the second voltage node.
  • the fifth switch and the first inductor are shared at the sixth node, and the fifth switch is also connected to the first node, while the first inductor is also connected to the fourth node.
  • the sixth switch and the second inductor are shared at the seventh node, and the sixth switch is also connected to the third node, while the second inductor is also connected to the fifth node.
  • the cathode of the diode is connected to the sixth node, and the anode of the diode is connected to the seventh node.
  • the stacked converter provided by this invention requires only seven switches and two inductors to control the voltage of four capacitors. Furthermore, the capacitor voltage can be controlled by using two inductors in parallel, achieving advantages such as reduced component costs, simplified structure, and space saving. Thus, compared to existing technologies, the stacked converter proposed in this invention possesses higher power density characteristics.
  • Figure 1 A circuit block diagram of a first embodiment of a conventional dual-capacitor stacked converter
  • Figure 2 A circuit block diagram of a second embodiment of a conventional dual-capacitor stacked converter
  • Figure 3 A circuit block diagram of the first embodiment of the stacked converter of the present invention
  • FIG 4A Timing diagram of energy transfer from the first capacitor to the second capacitor in the cascaded converter shown in Figure 3;
  • Figure 4B Timing diagram of the second capacitor transferring energy to the first capacitor in the cascaded converter shown in Figure 3;
  • Figure 4C Timing diagram of the third capacitor transferring energy to the fourth capacitor in the cascaded converter shown in Figure 3;
  • Figure 4D Timing diagram of the fourth capacitor transferring energy to the third capacitor in the cascaded converter shown in Figure 3;
  • Figure 4E Timing diagram showing the transfer of energy from the second capacitor to the third capacitor in the cascaded converter shown in Figure 3;
  • Figure 4F Timing diagram of the third capacitor transferring energy to the second capacitor in the cascaded converter shown in Figure 3;
  • Figure 4G Timing diagram showing the transfer of energy from the second capacitor to the third capacitor in the stacked converter shown in Figure 7;
  • Figure 4H Timing diagram of the third capacitor transferring energy to the second capacitor in the cascaded converter shown in Figure 7;
  • Figure 5A A schematic diagram of the first energy storage operation of the cascaded converter shown in Figure 3;
  • Figure 5B A schematic diagram of the first energy release operation of the cascaded converter shown in Figure 3;
  • Figure 5C A schematic diagram of the second energy storage operation of the cascaded converter shown in Figure 3;
  • Figure 5D A schematic diagram of the second energy release operation of the cascaded converter shown in Figure 3;
  • Figure 5E A schematic diagram of the third energy storage operation of the cascaded converter shown in Figure 3;
  • Figure 5F A schematic diagram of the third energy release operation of the cascaded converter shown in Figure 3;
  • Figure 5G A schematic diagram of the fourth energy storage operation of the cascaded converter shown in Figure 3;
  • Figure 5H A schematic diagram of the fourth energy release operation of the cascaded converter shown in Figure 3;
  • Figure 6A A schematic diagram of the fifth energy storage operation of the cascaded converter shown in Figure 3;
  • Figure 6B A schematic diagram of the fifth energy release operation of the cascaded converter shown in Figure 3;
  • Figure 6C A schematic diagram of the sixth energy storage operation of the cascaded converter shown in Figure 3;
  • Figure 6D A schematic diagram of the sixth energy release operation of the cascaded converter shown in Figure 3;
  • Figure 7 A circuit block diagram of a second embodiment of the stacked converter of the present invention.
  • Figure 8A A schematic diagram of the seventh energy storage operation of the cascaded converter shown in Figure 7;
  • Figure 8B A schematic diagram of the seventh energy release operation of the cascaded converter shown in Figure 7;
  • Figure 8C A schematic diagram of the eighth energy storage operation of the cascaded converter shown in Figure 7;
  • Figure 8D A schematic diagram of the eighth energy release operation of the cascaded converter shown in Figure 7.
  • FIG. 3 is a circuit block diagram of a first embodiment of the stacked converter of the present invention.
  • the stacked converter includes four capacitors C1 , C2 , C3 , C4 , four switches S1 , S2 , S3 , S4 , a fifth switch S5 and a first inductor L1 , a sixth switch S6 and a second inductor L2 , and a seventh switch S7 .
  • the four capacitors C1 , C2 , C3 , and C4 consist of a first capacitor C1 , a second capacitor C2 , a third capacitor C3 , and a fourth capacitor C4 connected in series.
  • the first capacitor C1 and the second capacitor C2 are connected together at the first node N1 ; the second capacitor C2 and the third capacitor C3 are connected together at the second node N2 ; and the third capacitor C3 and the fourth capacitor C4 are connected together at the third node N3 .
  • the first capacitor C1 is also connected to the first voltage node NA
  • the fourth capacitor C4 is also connected to the second voltage node NB .
  • the four switches S1 , S2 , S3 , and S4 consist of a first switch S1 , a second switch S2 , a third switch S3 , and a fourth switch S4 connected in series.
  • the first switch S1 and the second switch S2 are connected together to the fourth node N4 ;
  • the second switch S2 and the third switch S3 are connected together to the second node N2 ;
  • the third switch S3 and the fourth switch S4 are connected together to the fifth node N5 .
  • the first switch S1 is also connected to the first voltage node NA
  • the fourth switch S4 is also connected to the second voltage node NB .
  • the fifth switch S5 and the first inductor L1 are connected together to the sixth node N6 , and the fifth switch S5 is also connected to the first node N1 , while the first inductor L1 is also connected to the fourth node N4 .
  • the sixth switch S6 and the second inductor L2 are connected together to the seventh node N7 , and the sixth switch S6 is also connected to the third node N3 , while the second inductor L2 is also connected to the fifth node N5 .
  • the seventh switch S7 is connected between the sixth node N6 and the seventh node N7 .
  • Figure 4A is a timing diagram showing the energy transfer from the first capacitor to the second capacitor in the cascaded converter shown in Figure 3;
  • Figure 5A is a schematic diagram of the first energy storage operation of the cascaded converter shown in Figure 3;
  • Figure 5B is a schematic diagram of the first energy release operation of the cascaded converter shown in Figure 3.
  • the first time period i.e., time t1 to time t2
  • the fifth switch S5 is on
  • the seventh switch S7 is off
  • the first voltage V1 established on the first capacitor C1 stores energy in the first inductor L1 .
  • the first voltage V1 established on the first capacitor C1 stores energy in the first inductor L1 via a first energy storage path PS1 , where the first energy storage path PS1 is the path formed through the first capacitor C1 , the first switch S1 , the first inductor L1 , and the fifth switch S5 .
  • the first switch S1 is turned off, the second switch S2 is turned on, the fifth switch S5 is turned on, and the seventh switch S7 is turned off.
  • the energy of the first inductor L1 is released to the second capacitor C2 to establish the second voltage V2 .
  • the energy stored in the first inductor L1 is released to the second capacitor C2 through the first energy release path PR1 to establish the second voltage V2 .
  • the first energy release path PR1 is the path formed through the first inductor L1 , the fifth switch S5 , the second capacitor C2, and the second switch S2 .
  • Figure 4B is a timing diagram showing the energy transfer from the second capacitor to the first capacitor in the stacked converter shown in Figure 3;
  • Figure 5C is a schematic diagram of the second energy storage operation of the stacked converter shown in Figure 3;
  • Figure 5D is a schematic diagram of the second energy release operation of the stacked converter shown in Figure 3.
  • the second voltage V2 established on the second capacitor C2 stores energy in the first inductor L1 via the second energy storage path PS2 , where the second energy storage path PS2 is the path formed through the second capacitor C2 , the fifth switch S5 , the first inductor L1 , and the second switch S2 .
  • the first switch S1 is turned on, the second switch S2 is turned off, the fifth switch S5 is turned on, and the seventh switch S7 is turned off.
  • the energy of the first inductor L1 is released to the first capacitor C1 to establish the first voltage V1 .
  • the energy stored in the first inductor L1 is released to the first capacitor C1 through the second energy release path PR2 to establish the first voltage V1 .
  • the second energy release path PR2 is the path formed through the first inductor L1 , the first switch S1 , the first capacitor C1 , and the fifth switch S5 .
  • Figure 4C is a timing diagram showing the energy transfer from the third capacitor to the fourth capacitor in the stacked converter shown in Figure 3;
  • Figure 5E is a schematic diagram of the third energy storage operation of the stacked converter shown in Figure 3;
  • Figure 5F is a schematic diagram of the third energy release operation of the stacked converter shown in Figure 3.
  • the third switch S3 based on the first time period (i.e., time t1 to time t2), when the third switch S3 is turned on, the fourth switch S4 is turned off, the sixth switch S6 is turned on, and the seventh switch S7 is turned off, the third voltage V3 established on the third capacitor C3 stores energy in the second inductor L2 .
  • the third voltage V3 established on the third capacitor C3 stores energy in the second inductor L2 through the third energy storage path PS3 , where the third energy storage path PS3 is the path formed through the third capacitor C3 , the third switch S3 , the second inductor L2 and the sixth switch S6 .
  • the third switch S3 is turned off, the fourth switch S4 is turned on, the sixth switch S6 is turned on, and the seventh switch S7 is turned off.
  • the energy stored in the second inductor L2 is released to the fourth capacitor C4 to establish the fourth voltage V4 .
  • the energy stored in the second inductor L2 is released to the fourth capacitor C4 through the third energy release path PR3 to establish the fourth voltage V4 .
  • the third energy release path PR3 is the path formed through the second inductor L2 , the sixth switch S6 , the fourth capacitor C4 , and the fourth switch S4 .
  • Figure 4D is a timing diagram showing the energy transfer from the fourth capacitor to the third capacitor in the cascaded converter shown in Figure 3;
  • Figure 5G is a schematic diagram of the fourth energy storage operation of the cascaded converter shown in Figure 3;
  • Figure 5H is a schematic diagram of the fourth energy release operation of the cascaded converter shown in Figure 3.
  • the fourth voltage V4 established on the fourth capacitor C4 stores energy in the second inductor L2 .
  • the fourth voltage V4 established on the fourth capacitor C4 stores energy in the second inductor L2 via a fourth energy storage path PS4 , where PS4 is the path formed through the fourth capacitor C4 , the sixth switch S6 , the second inductor L2 , and the fourth switch S4 .
  • the third switch S3 is turned on, the fourth switch S4 is turned off, the sixth switch S6 is turned on, and the seventh switch S7 is turned off.
  • the energy stored in the second inductor L2 is released to the third capacitor C3 to establish the third voltage V3 .
  • the energy stored in the second inductor L2 is released to the third capacitor C3 through the fourth energy release path PR4 to establish the third voltage V3 .
  • the fourth energy release path PR4 is the path formed through the second inductor L2 , the third switch S3 , the third capacitor C3, and the sixth switch S6 .
  • Figure 4E is a timing diagram showing the energy transfer from the second capacitor to the third capacitor in the stacked converter shown in Figure 3;
  • Figure 6A is a schematic diagram of the fifth energy storage operation of the stacked converter shown in Figure 3;
  • Figure 6B is a schematic diagram of the fifth energy release operation of the stacked converter shown in Figure 3.
  • the second switch S2 is turned on, the third switch S3 is turned on, the fifth switch S5 is turned on, the sixth switch S6 is turned off, and the seventh switch S7 is turned on.
  • the second voltage V2 established on the second capacitor C2 stores energy in the first inductor L1 and the second inductor L2 .
  • the second voltage V2 established on the second capacitor C2 stores energy in the first inductor L1 and the second inductor L2 through the fifth energy storage path PS5 .
  • the fifth energy storage path PS5 is the path formed by the second capacitor C2 , the fifth switch S5 , the first inductor L1 and the second switch S2 , and the path formed by the second capacitor C2 , the fifth switch S5 , the seventh switch S7 , the second inductor L2 and the third switch S3 .
  • the second switch S2 is turned on, the third switch S3 is turned on, the fifth switch S5 is turned off, the sixth switch S6 is turned on, and the seventh switch S7 is turned on.
  • the energy of the first inductor L1 and the second inductor L2 is released to the third capacitor C3 to establish the third voltage V3 .
  • the energy stored in the first inductor L1 and the second inductor L2 releases energy to the third capacitor C3 through the fifth energy release path PR5 to establish the third voltage V3 .
  • the fifth energy release path PR5 is the path formed by the first inductor L1 , the second switch S2 , the third capacitor C3 , the sixth switch S6 , and the seventh switch S7 , as well as the path formed by the second inductor L2 , the third switch S3 , the third capacitor C3, and the sixth switch S6 .
  • Figure 4F is a timing diagram showing the energy transfer from the third capacitor to the second capacitor in the stacked converter shown in Figure 3;
  • Figure 6C is a schematic diagram of the sixth energy storage operation of the stacked converter shown in Figure 3;
  • Figure 6D is a schematic diagram of the sixth energy release operation of the stacked converter shown in Figure 3.
  • the second switch S2 is turned on, the third switch S3 is turned on, the fifth switch S5 is turned off, the sixth switch S6 is turned on, and the seventh switch S7 is turned on, the third voltage V3 established on the third capacitor C3 stores energy in the first inductor L1 and the second inductor L2 .
  • the third voltage V3 established on the third capacitor C3 stores energy in the first inductor L1 and the second inductor L2 through the sixth energy storage path PS6 .
  • the sixth energy storage path PS6 is the path formed by the third capacitor C3 , the second switch S2 , the first inductor L1 , the seventh switch S7 , and the sixth switch S6 , as well as the path formed by the third capacitor C3 , the third switch S3 , the second inductor L2 , and the sixth switch S6 .
  • the second switch S2 is turned on, the third switch S3 is turned on, the fifth switch S5 is turned on, the sixth switch S6 is turned off, and the seventh switch S7 is turned on.
  • the energy from the first inductor L1 and the second inductor L2 is released to the second capacitor C2 to establish the second voltage V2 . See Figure 6D for further details.
  • the third switch S3 , the fifth switch S5 , and the seventh switch S7 i.e., the fifth switch S5 changes from off to on, and the sixth switch S6 changes from on to off
  • the sixth energy release path PR6 is the path formed by the first inductor L1 , the fifth switch S5 , the second capacitor C2 and the second switch S2 , and the path formed by the second inductor L2 , the seventh switch S7 , the fifth switch S5 , the second capacitor C2 and the third switch S3 .
  • FIG. 7 is a circuit block diagram of a second embodiment of the stacked converter of the present invention.
  • This stacked converter includes four capacitors C1 , C2 , C3 , and C4 ; four switches S1 , S2 , S3 , and S4 ; a fifth switch S5 and a first inductor L1 ; a sixth switch S6 and a second inductor L2 ; and a diode D1 .
  • the diode D1 replaces the seventh switch S7 .
  • the four capacitors C1 , C2 , C3 , and C4 consist of a first capacitor C1 , a second capacitor C2 , a third capacitor C3 , and a fourth capacitor C4 connected in series.
  • the first capacitor C1 and the second capacitor C2 are connected together at the first node N1 ; the second capacitor C2 and the third capacitor C3 are connected together at the second node N2 ; and the third capacitor C3 and the fourth capacitor C4 are connected together at the third node N3 .
  • the first capacitor C1 is also connected to the first voltage node NA
  • the fourth capacitor C4 is also connected to the second voltage node NB .
  • the four switches S1 , S2 , S3 , and S4 consist of a first switch S1 , a second switch S2 , a third switch S3 , and a fourth switch S4 connected in series.
  • the first switch S1 and the second switch S2 are connected together to the fourth node N4 ;
  • the second switch S2 and the third switch S3 are connected together to the second node N2 ;
  • the third switch S3 and the fourth switch S4 are connected together to the fifth node N5 .
  • the first switch S1 is also connected to the first voltage node NA
  • the fourth switch S4 is also connected to the second voltage node NB .
  • the fifth switch S5 and the first inductor L1 are connected together to the sixth node N6 , and the fifth switch S5 is also connected to the first node N1 .
  • the first inductor L1 is also connected to the fourth node N4 .
  • the sixth switch S6 and the second inductor L2 are connected together to the seventh node N7 , and the sixth switch S6 is also connected to the third node N3 .
  • the second inductor L2 is also connected to the fifth node N5 .
  • the cathode of diode D1 is connected to the sixth node N6 , and the anode of diode D1 is connected to the seventh node N7 .
  • Figure 4A is a timing diagram of the energy transfer from the first capacitor to the second capacitor in the stacked converter shown in Figure 3
  • Figure 5A is a schematic diagram of the first energy storage operation of the stacked converter shown in Figure 3
  • Figure 5B is a schematic diagram of the first energy release operation of the stacked converter shown in Figure 3.
  • diode D1 replaces the seventh switch S7 . Therefore, the control signal SS7 controlling the seventh switch S7 in Figure 4A is deleted, and the seventh switch S7 in Figures 5A and 5B is replaced with diode D1 to correspond to the description of this embodiment.
  • the first voltage V1 established on the first capacitor C1 stores energy in the first inductor L1 .
  • the seventh switch S7 is replaced by diode D1 ), based on the conduction of the first switch S1 and the conduction of the fifth switch S5 , the first voltage V1 established on the first capacitor C1 stores energy in the first inductor L1 through the first energy storage path PS1 , wherein the first energy storage path PS1 is the path formed through the first capacitor C1 , the first switch S1 , the first inductor L1 and the fifth switch S5 .
  • the first switch S1 is turned off, the second switch S2 is turned on, and the fifth switch S5 is turned on.
  • the energy of the first inductor L1 is released to the second capacitor C2 to establish the second voltage V2 .
  • the seventh switch S7 is replaced by a diode D1
  • the energy stored in the first inductor L1 is released to the second capacitor C2 through the first energy release path PR1 to establish the second voltage V2 .
  • the first energy release path PR1 is the path formed through the first inductor L1 , the fifth switch S5 , the second capacitor C2 , and the second switch S2 .
  • Figure 4B is a timing diagram showing the transfer of energy from the second capacitor to the first capacitor in the stacked converter shown in Figure 3
  • Figure 5C is a schematic diagram of the second energy storage operation of the stacked converter shown in Figure 3
  • Figure 5D is a schematic diagram of the second energy release operation of the stacked converter shown in Figure 3.
  • the first voltage V1 established on the first capacitor C1 stores energy in the first inductor L1 .
  • the seventh switch S7 is replaced by a diode D1
  • the second voltage V2 established on the second capacitor C2 stores energy in the first inductor L1 through the second energy storage path PS2 , where the second energy storage path PS2 is the path formed through the second capacitor C2 , the fifth switch S5 , the first inductor L1 , and the second switch S2 .
  • the first switch S1 is turned on, the second switch S2 is turned off, and the fifth switch S5 is turned on.
  • the energy of the first inductor L1 is released to the first capacitor C1 to establish the first voltage V1 .
  • the seventh switch S7 is replaced by a diode D1
  • the energy stored in the first inductor L1 is released to the first capacitor C1 through the second energy release path PR2 to establish the first voltage V1 .
  • the second energy release path PR2 is the path formed through the first inductor L1 , the first switch S1 , the first capacitor C1 , and the fifth switch S5 .
  • Figure 4C is a timing diagram of the energy transfer from the third capacitor to the fourth capacitor in the stacked converter shown in Figure 3
  • Figure 5E is a schematic diagram of the third energy storage operation of the stacked converter shown in Figure 3
  • Figure 5F is a schematic diagram of the third energy release operation of the stacked converter shown in Figure 3.
  • the third switch S3 is turned on, the fourth switch S4 is turned off, and the sixth switch S6 is turned on, the third voltage V3 established on the third capacitor C3 stores energy in the second inductor L2 .
  • the seventh switch S7 is replaced by diode D1 ), based on the conduction of the third switch S3 and the sixth switch S6 , the third voltage V3 established on the third capacitor C3 stores energy in the second inductor L2 through the third energy storage path PS3 , where the third energy storage path PS3 is the path formed through the third capacitor C3 , the third switch S3 , the second inductor L2 and the sixth switch S6 .
  • the third switch S3 is turned off, the fourth switch S4 is turned on, and the sixth switch S6 is turned on.
  • the energy of the second inductor L2 is released to the fourth capacitor C4 to establish the fourth voltage V4 .
  • the seventh switch S7 is replaced by a diode D1
  • the energy stored in the second inductor L2 is released to the fourth capacitor C4 through the third energy release path PR3 to establish the fourth voltage V4 .
  • the third energy release path PR3 is the path formed through the second inductor L2 , the sixth switch S6 , the fourth capacitor C4 , and the fourth switch S4 .
  • Figure 4D is a timing diagram of the fourth capacitor transferring energy to the third capacitor in the stacked converter shown in Figure 3
  • Figure 5G is a schematic diagram of the third energy release operation of the stacked converter shown in Figure 3
  • Figure 5H is a schematic diagram of the fourth energy release operation of the stacked converter shown in Figure 3.
  • the third switch S3 is turned off, the fourth switch S4 is turned on, and the sixth switch S6 is turned on, the fourth voltage V4 established on the fourth capacitor C4 stores energy in the second inductor L2 .
  • the seventh switch S7 is replaced by diode D1
  • the fourth voltage V4 established on the fourth capacitor C4 stores energy in the second inductor L2 through the fourth energy storage path PS4 , where the fourth energy storage path PS4 is the path formed through the fourth capacitor C4 , the sixth switch S6 , the second inductor L2 and the fourth switch S4 .
  • the third switch S3 is turned on, the fourth switch S4 is turned off, and the sixth switch S6 is turned on.
  • the energy stored in the second inductor L2 is released to the third capacitor C3 to establish the third voltage V3 .
  • the seventh switch S7 is replaced by a diode D1
  • the energy stored in the second inductor L2 is released via the fourth energy release path PR4.
  • the third capacitor C3 releases energy to establish the third voltage V3 , wherein the fourth energy release path PR4 is the path formed through the second inductor L2 , the third switch S3 , the third capacitor C3 and the sixth switch S6 .
  • Figure 4G is a timing diagram showing the energy transfer from the second capacitor to the third capacitor in the stacked converter shown in Figure 7;
  • Figure 8A is a schematic diagram of the seventh energy storage operation of the stacked converter shown in Figure 7;
  • Figure 8B is a schematic diagram of the seventh energy release operation of the stacked converter shown in Figure 7.
  • the second switch S2 is turned on, the third switch S3 is turned off, the fifth switch S5 is turned on, and the sixth switch S6 is turned off, the second voltage V2 established on the second capacitor C2 stores energy in the first inductor L1 .
  • the second voltage V2 established on the second capacitor C2 stores energy in the first inductor L1 via the seventh energy storage path PS7 , where the seventh energy storage path PS7 is the path formed through the second capacitor C2 , the fifth switch S5 , the first inductor L1 , and the second switch S2 .
  • the second switch S2 is turned on, the third switch S3 is turned off, the fifth switch S5 is turned off, and the sixth switch S6 is turned on.
  • the energy stored in the first inductor L1 is released to the third capacitor C3 to establish the third voltage V3 .
  • the sixth switch S6 changes from off to on
  • the energy stored in the first inductor L1 is released to the third capacitor C3 through the seventh energy release path PR7 to establish the third voltage V3 .
  • the seventh energy release path PR7 is the path formed by the first inductor L1 , the second switch S2 , the third capacitor C3 , the sixth switch S6 , and the diode D1 .
  • Figure 4F is a timing diagram of the energy transfer from the third capacitor to the second capacitor in the stacked converter shown in Figure 3
  • Figure 6C is a schematic diagram of the sixth energy storage operation of the stacked converter shown in Figure 3
  • Figure 6D is a schematic diagram of the sixth energy release operation of the stacked converter shown in Figure 3.
  • the third voltage V3 established on the third capacitor C3 stores energy in the second inductor L2 through the eighth energy storage path PS8 , where the eighth energy storage path PS8 is the path formed through the third capacitor C3 , the third switch S3 , the second inductor L2 and the sixth switch S6 .
  • the second switch S2 is turned off, the third switch S3 is turned on, the fifth switch S5 is turned on, and the sixth switch S6 is turned off.
  • the energy stored in the second inductor L2 is released to the second capacitor C2 to establish the second voltage V2 .
  • the eighth energy release path PR8 is the path formed by the second inductor L2 , diode D1 , the fifth switch S5 , the second capacitor C2 , and the third switch S3 .
  • the present invention has the following features and advantages:
  • the stacked converter proposed in this invention requires only seven switches S1 to S7 and two inductors L1 and L2 to control the voltages V1 to V4 of four capacitors.
  • the capacitor voltages V2 and V3 can be controlled by using two inductors L1 and L2 in parallel, achieving advantages such as saving component costs, simple structure, and space saving. Therefore, compared with the prior art, the stacked converter proposed in this invention has higher power density characteristics.

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Abstract

一种叠接型转换器包括四个电容、四个开关、第五开关与第一电感、第六开关与第二电感以及第七开关。四个电容包括串联的第一电容、第二电容、第三电容以及第四电容；四个开关包括串联的第一开关、第二开关、第三开关以及第四开关。第五开关的一端与第一电感的一端共接于第六节点，且第五开关的另一端连接于第一节点，第一电感的另一端连接于第四节点。第六开关的一端与第二电感的一端共接于第七节点，且第六开关的另一端连接于第三节点，第二电感的另一端连接于第五节点。第七开关连接于第六节点与第七节点之间。该转换器具有结构简单、元件成本低、功率密度高的优点。

Description

叠接型转换器 技术领域
本发明涉及一种叠接型转换器，尤指一种具节省元件与结构简单的叠接型转换器。
背景技术
请参见图1所示，其为现有双电容叠接转换器的第一实施例的电路方块图。当有两个电容C1,C2时，电路至少需要有一个电感L1与两个开关S1,S2组成。请参见图2所示，其为现有双电容叠接转换器的第二实施例的电路方块图。当增加到四个电容C1,C2,C3,C4时，由于电压提供能量不相同，电路上至少需要三个电感L1,L2,L3跟六个开关S1,S2,S3,S4,S5,S6来维持所需的电压大小。因现有双电容叠接转换器包含较多的元件数量，会造成电路体积过大、成本过高，以及功率密度难提高等缺点。
例如，在数据中心快速发展的情形下，随者数据快速膨胀，需要安装的伺服器数量也随者增加。在有限的空间下，势必要缩小电力装置的体积(例如但不限制：叠接转换器等)，其中最有效的缩小体积的方式为减少元件数量。为此，如何设计出一种较少元件数量的叠接型转换器，解决现有技术所存在电路体积过大、成本过高，以及功率密度难提高的问题与技术瓶颈，乃为本案发明人所研究的重要课题。
发明内容
本发明的一目的在于提供一种叠接型转换器。叠接型转换器包括四电容、四开关、第五开关与第一电感、第六开关与第二电感以及第七开关。四电容包括串联的第一电容、第二电容、第三电容以及第四电容，其中第一电容与第二电容共接于第一节点，第二电容与第三电容共接于第二节点，第三电容与第四电容共接于第三节点，且第一电容另连接于第一电压节点，第四电容另连接于第二电压节点。四开关包括串联的第一开关、第二开关、第三开关以及第四开关，其中第一开关与第二开关共接于第四节点，第二开关与第三开关共接于第二节点，第三开关与第四开关共接于第五节点，且第一开关另连接于第一电压节点，第四开关另连接于第二电压节点。第五开关与第一电感共接于第六节点，且第五开关另连接于第一节点，第一电感另连接于第四节点。第六开关与第二电感共接于第七节点，且第六开关另连接于第三节点，第二电感另连接于第五节点。第七开关连接于第六节点与第七节点之间。
本发明的另一目的在于提供一种叠接型转换器。叠接型转换器包括四电容、四开关、第五开关与第一电感、第六开关与第二电感以及二极管。四电容包括串联的第一电容、第二电容、第三电容以及第四电容，其中第一电容与第二电容共接于第一节点，第二电容与第三电容共接于第二节点，第三电容与第四电容共接于第三节点，且第一电容另连接于第一电压节点，第四电容另连接于第二电压节点。四开关包括串联的第一开关、第二开关、第三开关以 及第四开关，其中第一开关与第二开关共接于第四节点，第二开关与第三开关共接于第二节点，第三开关与第四开关共接于第五节点，且第一开关另连接于第一电压节点，第四开关另连接于第二电压节点。第五开关与第一电感共接于第六节点，且第五开关另连接于第一节点，第一电感另连接于第四节点。第六开关与第二电感共接于第七节点，且第六开关另连接于第三节点，第二电感另连接于第五节点。二极管的阴极连接于第六节点，二极管的阳极连接于第七节点。
由此，本发明所提供的叠接型转换器，只需要七个开关以及两个电感，即可做到四电容电压的控制，并且可通过两电感并联使用，以控制电容电压，达到节省元件成本、结构简单以及节省空间的优点。因此，相较于现有技术，本发明所提出的叠接型转换器更具备高功率密度的特性。
为了能更进一步了解本发明为达成预定目的所采取的技术、手段及功效，请参阅以下有关本发明的详细说明与附图，相信本发明的目的、特征与特点，当可由此得一深入且具体的了解，然而所附附图仅提供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1：为现有双电容叠接转换器的第一实施例的电路方块图；
图2：为现有双电容叠接转换器的第二实施例的电路方块图；
图3：为本发明叠接型转换器的第一实施例的电路方块图；
图4A：为图3所示叠接型转换器的第一电容传递能量至第二电容的时序图；
图4B：为图3所示叠接型转换器的第二电容传递能量至第一电容的时序图；
图4C：为图3所示叠接型转换器的第三电容传递能量至第四电容的时序图；
图4D：为图3所示叠接型转换器的第四电容传递能量至第三电容的时序图；
图4E：为图3所示叠接型转换器的第二电容传递能量至第三电容的时序图；
图4F：为图3所示叠接型转换器的第三电容传递能量至第二电容的时序图；
图4G：为图7所示叠接型转换器的第二电容传递能量至第三电容的时序图；
图4H：为图7所示叠接型转换器的第三电容传递能量至第二电容的时序图；
图5A：为图3所示叠接型转换器的第一储能操作的示意图；
图5B：为图3所示叠接型转换器的第一释能操作的示意图；
图5C：为图3所示叠接型转换器的第二储能操作的示意图；
图5D：为图3所示叠接型转换器的第二释能操作的示意图；
图5E：为图3所示叠接型转换器的第三储能操作的示意图；
图5F：为图3所示叠接型转换器的第三释能操作的示意图；
图5G：为图3所示叠接型转换器的第四储能操作的示意图；
图5H：为图3所示叠接型转换器的第四释能操作的示意图；
图6A：为图3所示叠接型转换器的第五储能操作的示意图；
图6B：为图3所示叠接型转换器的第五释能操作的示意图；
图6C：为图3所示叠接型转换器的第六储能操作的示意图；
图6D：为图3所示叠接型转换器的第六释能操作的示意图；
图7：为本发明叠接型转换器的第二实施例的电路方块图；
图8A：为图7所示叠接型转换器的第七储能操作的示意图；
图8B：为图7所示叠接型转换器的第七释能操作的示意图；
图8C：为图7所示叠接型转换器的第八储能操作的示意图；
图8D：为图7所示叠接型转换器的第八释能操作的示意图。
附图标号说明
C1～C4:第一电容～第四电容
S1～S7:第一开关～第七开关
L1,L2:第一电感～第二电感
D1:二极管
N1～N7:第一节点～第七节点
NA,NB:第一电压节点～第二电压节点
PS1～PS8:第一储能路径～第八储能路径
PR1～PR8:第一释能路径～第八释能路径
V1～V4:第一电压～第四电压
SS1～SS7:第一控制信号～第七控制信号
t1～t3:时间
具体实施方式
有关本发明的技术内容及详细说明，配合附图说明如下。
请参见图3，为本发明叠接型转换器的第一实施例的电路方块图。该叠接型转换器包括四电容C1,C2,C3,C4、四开关S1,S2,S3,S4、第五开关S5与第一电感L1、第六开关S6与第二电感L2以及第七开关S7。
四电容C1,C2,C3,C4包括串联的第一电容C1、第二电容C2、第三电容C3以及第四电容C4。其中第一电容C1与第二电容C2共接于第一节点N1，第二电容C2与第三电容C3共接于第二节点N2，第三电容C3与第四电容C4共接于第三节点N3。第一电容C1另连接于第一电压节点NA，第四电容C4另连接于第二电压节点NB。
四开关S1,S2,S3,S4包括串联的第一开关S1、第二开关S2、第三开关S3以及第四开关S4。其中第一开关S1与第二开关S2共接于第四节点N4，第二开关S2与第三开关S3共接于第二节点N2，第三开关S3与第四开关S4共接于第五节点N5。且第一开关S1另连接于第一电压节点NA，第四开关S4另连接于第二电压节点NB。
第五开关S5与第一电感L1共接于第六节点N6，且第五开关S5另连接于第一节点N1，第一电感L1另连接于第四节点N4。第六开关S6与第二电感L2共接于第七节点N7，且第六开关S6另连接于第三节点N3，第二电感L2另连接于第五节点N5。第七开关S7连接于第六节点N6与第七节点N7之间。
请参见图4A、图5A以及图5B，其中图4A为图3所示叠接型转换器的第一电容传递能量至第二电容的时序图；图5A为图3所示叠接型转换器的第一储能操作的示意图；图5B为图3所示叠接型转换器的第一释能操作的示意图。如图4A所示，基于在第一时间段(即时间t1至时间t2)， 第一开关S1导通，第二开关S2关断，第五开关S5导通以及第七开关S7关断，在第一电容C1上建立的第一电压V1对第一电感L1储能。可配合参见图5A，基于第一开关S1导通与第五开关S5导通，在第一电容C1上建立的第一电压V1以第一储能路径PS1对第一电感L1储能，其中第一储能路径PS1为通过第一电容C1、第一开关S1、第一电感L1以及第五开关S5所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第一开关S1关断，第二开关S2导通，第五开关S5导通以及第七开关S7关断，第一电感L1的能量释能至第二电容C2以建立第二电压V2。可配合参见图5B，基于第二开关S2导通与第五开关S5导通(即第一开关S1由导通转为关断，第二开关S2由关断转为导通)，第一电感L1的储能以第一释能路径PR1对第二电容C2释能以建立第二电压V2，其中第一释能路径PR1为通过第一电感L1、第五开关S5、第二电容C2以及第二开关S2所形成的路径。
请参见图4B、图5C以及图5D，其中图4B为图3所示叠接型转换器的第二电容传递能量至第一电容的时序图；图5C为图3所示叠接型转换器的第二储能操作的示意图；图5D为图3所示叠接型转换器的第二释能操作的示意图。如图4B所示，基于在第一时间段(即时间t1至时间t2)，第一开关S1关断，第二开关S2导通，第五开关S5导通以及第七开关S7关断，在第一电容C1上建立的第一电压V1对第一电感L1储能。可配合参见图5C，基于第二开关S2导通与第五开关S5导通，在第二电容C2上建立的第二电压V2以第二储能路径PS2对第一电感L1储能，其中第二储能路径PS2为通过第二电容C2、第五开关S5、第一电感L1以及第二开关S2所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第一开关S1导通，第二开关S2关断，第五开关S5导通以及第七开关S7关断，第一电感L1的能量释能至第一电容C1以建立第一电压V1。可配合参见图5D，基于第一开关S1导通与第五开关S5导通(即第一开关S1由关断转为导通，第二开关S2由导通转为关断)，第一电感L1的储能以第二释能路径PR2对第一电容C1释能以建立第一电压V1，其中第二释能路径PR2为通过第一电感L1、第一开关S1、第一电容C1以及第五开关S5所形成的路径。
请参见图4C、图5E以及图5F，其中图4C为图3所示叠接型转换器的第三电容传递能量至第四电容的时序图；图5E为图3所示叠接型转换器的第三储能操作的示意图；图5F为图3所示叠接型转换器的第三释能操作的示意图。如图4C所示，基于在第一时间段(即时间t1至时间t2)，第三开关S3导通，第四开关S4关断，第六开关S6导通以及第七开关S7关断，在第三电容C3上建立的第三电压V3对第二电感L2储能。可配合参见图5E，基于第三开关S3导通与第六开关S6导通，在第三电容C3上建立的第三电压V3以第三储能路径PS3对第二电感L2储能，其中第三储能路径PS3为通过第三电容C3、第三开关S3、第二电感L2以及第六开关S6所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第三开关S3关断，第四开关S4导通，第六开关S6导通以及第七开关S7关断，第二电感L2的能量释能至第四电容C4以建立第四电压V4。可配合参见图5F，基于第四开关S4导通与第六开关S6导通(即第三开关S3由导通转为关断，第四开关S4由关断转为导通)，第二电感L2的储能以第三释能路径PR3对第四电容C4释能以建立第四电压V4，其中第三释能路径PR3为通过第二电感L2、第六开关S6、第四电容C4以及第四开关S4所形成的路径。
请参见图4D、图5G以及图5H，其中图4D为图3所示叠接型转换器的第四电容传递能量至第三电容的时序图；图5G为图3所示叠接型转换器的第四储能操作的示意图；图5H为图3所示叠接型转换器的第四释能操作的示意图。如图4D所示，基于在第一时间段(即时间t1至时间t2)， 第三开关S3关断，第四开关S4导通，第六开关S6导通以及第七开关S7关断，在第四电容C4上建立的第四电压V4对第二电感L2储能。可配合参见图5G，基于第四开关S4导通与第六开关S6导通，在第四电容C4上建立的第四电压V4以第四储能路径PS4对第二电感L2储能，其中第四储能路径PS4为通过第四电容C4、第六开关S6、第二电感L2以及第四开关S4所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第三开关S3导通，第四开关S4关断，第六开关S6导通以及第七开关S7关断，第二电感L2的能量释能至第三电容C3以建立第三电压V3。可配合参见图5H，基于第三开关S3导通与第六开关S6导通(即第三开关S3由关断转为导通，第四开关S4由导通转为关断)，第二电感L2的储能以第四释能路径PR4对第三电容C3释能以建立第三电压V3，其中第四释能路径PR4为通过第二电感L2、第三开关S3、第三电容C3以及第六开关S6所形成的路径。
请参见图4E、图6A以及图6B，其中图4E为图3所示叠接型转换器的第二电容传递能量至第三电容的时序图；图6A为图3所示叠接型转换器的第五储能操作的示意图；图6B为图3所示叠接型转换器的第五释能操作的示意图。如图4E所示，基于在第一时间段(即时间t1至时间t2)，第二开关S2导通，第三开关S3导通，第五开关S5导通，第六开关S6关断以及第七开关S7导通，在第二电容C2上建立的第二电压V2对第一电感L1与第二电感L2储能。可配合参见图6A，基于第二开关S2导通、第三开关S3导通、第五开关S5导通与第七开关S7导通，在第二电容C2上建立的第二电压V2以第五储能路径PS5对第一电感L1与第二电感L2储能，其中第五储能路径PS5为通过第二电容C2、第五开关S5、第一电感L1与第二开关S2，以及通过第二电容C2、第五开关S5、第七开关S7、第二电感L2与第三开关S3所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第二开关S2导通，第三开关S3导通，第五开关S5关断，第六开关S6导通以及第七开关S7导通，第一电感L1与第二电感L2的能量释能至第三电容C3以建立第三电压V3。可配合参见图6B，基于第二开关S2导通、第三开关S3导通、第六开关S6导通与第七开关S7导通(即第五开关S5由导通转为关断，第六开关S6由关断转为导通)，第一电感L1与第二电感L2的储能以第五释能路径PR5对第三电容C3释能以建立第三电压V3，其中第五释能路径PR5为通过第一电感L1、第二开关S2、第三电容C3、第六开关S6与第七开关S7，以及通过第二电感L2、第三开关S3、第三电容C3与第六开关S6所形成的路径。
请参见图4F、图6C以及图6D，其中图4F为图3所示叠接型转换器的第三电容传递能量至第二电容的时序图；图6C为图3所示叠接型转换器的第六储能操作的示意图；图6D为图3所示叠接型转换器的第六释能操作的示意图。如图4F所示，基于在第一时间段(即时间t1至时间t2)，第二开关S2导通，第三开关S3导通，第五开关S5关断，第六开关S6导通以及第七开关S7导通，在第三电容C3上建立的第三电压V3对第一电感L1与第二电感L2储能。可配合参见图6C，基于第二开关S2导通、第三开关S3导通、第六开关S6导通与第七开关S7导通，在第三电容C3上建立的第三电压V3以第六储能路径PS6对第一电感L1与第二电感L2储能，其中第六储能路径PS6为通过第三电容C3、第二开关S2、第一电感L1、第七开关S7与第六开关S6，以及通过第三电容C3、第三开关S3、第二电感L2与第六开关S6所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第二开关S2导通，第三开关S3导通，第五开关S5导通，第六开关S6关断以及第七开关S7导通，第一电感L1与第二电感L2的能量释能至第二电容C2以建立第二电压V2。可配合参见图6D，基于第二开关S2导通、第三开关S3导通、第五开关S5导通与第七开关S7导通(即第五开关S5由关断转为导通，第六开关S6由导通转 为关断)，第一电感L1与第二电感L2的储能以第六释能路径PR6对第二电容C2释能以建立第二电压V2，其中第六释能路径PR6为通过第一电感L1、第五开关S5、第二电容C2与第二开关S2，以及通过第二电感L2、第七开关S7、第五开关S5、第二电容C2与第三开关S3所形成的路径。
请参见图7，为本发明叠接型转换器的第二实施例的电路方块图。该叠接型转换器包括四电容C1,C2,C3,C4、四开关S1,S2,S3,S4、第五开关S5与第一电感L1、第六开关S6与第二电感L2以及二极管D1。附带一提，图7所示的第二实施例与图3所示的第一实施例最大的差异在于将二极管D1取代第七开关S7。
四电容C1,C2,C3,C4包括串联的第一电容C1、第二电容C2、第三电容C3以及第四电容C4。其中第一电容C1与第二电容C2共接于第一节点N1，第二电容C2与第三电容C3共接于第二节点N2，第三电容C3与第四电容C4共接于第三节点N3。第一电容C1另连接于第一电压节点NA，第四电容C4另连接于第二电压节点NB。
四开关S1,S2,S3,S4包括串联的第一开关S1、第二开关S2、第三开关S3以及第四开关S4。其中第一开关S1与第二开关S2共接于第四节点N4，第二开关S2与第三开关S3共接于第二节点N2，第三开关S3与第四开关S4共接于第五节点N5。且第一开关S1另连接于第一电压节点NA，第四开关S4另连接于第二电压节点NB。
第五开关S5与第一电感L1共接于第六节点N6，且第五开关S5另连接于第一节点N1，第一电感L1另连接于第四节点N4。第六开关S6与第二电感L2共接于第七节点N7，且第六开关S6另连接于第三节点N3，第二电感L2另连接于第五节点N5。二极管D1的阴极连接于第六节点N6，二极管D1的阳极连接于第七节点N7。
请参见图4A、图5A以及图5B，其中图4A为图3所示叠接型转换器的第一电容传递能量至第二电容的时序图；图5A为图3所示叠接型转换器的第一储能操作的示意图；图5B为图3所示叠接型转换器的第一释能操作的示意图。然，附带一提，承前所述，在第二实施例以二极管D1取代第七开关S7，因此将图4A中控制第七开关S7的控制信号SS7删去，并且将图5A与图5B的第七开关S7改为二极管D1即可对应本实施方式的记载。如图4A所示，基于在第一时间段(即时间t1至时间t2)，第一开关S1导通，第二开关S2关断以及第五开关S5导通，在第一电容C1上建立的第一电压V1对第一电感L1储能。可配合参见图5A(承前所述，第七开关S7改为二极管D1)，基于第一开关S1导通与第五开关S5导通，在第一电容C1上建立的第一电压V1以第一储能路径PS1对第一电感L1储能，其中第一储能路径PS1为通过第一电容C1、第一开关S1、第一电感L1以及第五开关S5所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第一开关S1关断，第二开关S2导通以及第五开关S5导通，第一电感L1的能量释能至第二电容C2以建立第二电压V2。可配合参见图5B(承前所述，第七开关S7改为二极管D1)，基于第二开关S2导通与第五开关S5导通(即第一开关S1由导通转为关断，第二开关S2由关断转为导通)，第一电感L1的储能以第一释能路径PR1对第二电容C2释能以建立第二电压V2，其中第一释能路径PR1为通过第一电感L1、第五开关S5、第二电容C2以及第二开关S2所形成的路径。
请参见图4B、图5C以及图5D，其中图4B为图3所示叠接型转换器的第二电容传递能量至第一电容的时序图；图5C为图3所示叠接型转换器的第二储能操作的示意图；图5D为图3所示叠接型转换器的第二释能操作的示意图。同样地，将图4B中控制第七开关S7的控制信号SS7删去，并且将图5C与图5D的第七开关S7改为二极管D1即可对应本实施方式的记载。如图4B所示， 基于在第一时间段(即时间t1至时间t2)，第一开关S1关断，第二开关S2导通以及第五开关S5导通，在第一电容C1上建立的第一电压V1对第一电感L1储能。可配合参见图5C(承前所述，第七开关S7改为二极管D1)，基于第二开关S2导通与第五开关S5导通，在第二电容C2上建立的第二电压V2以第二储能路径PS2对第一电感L1储能，其中第二储能路径PS2为通过第二电容C2、第五开关S5、第一电感L1以及第二开关S2所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第一开关S1导通，第二开关S2关断以及第五开关S5导通，第一电感L1的能量释能至第一电容C1以建立第一电压V1。可配合参见图5D(承前所述，第七开关S7改为二极管D1)，基于第一开关S1导通与第五开关S5导通(即第一开关S1由关断转为导通，第二开关S2由导通转为关断)，第一电感L1的储能以第二释能路径PR2对第一电容C1释能以建立第一电压V1，其中第二释能路径PR2为通过第一电感L1、第一开关S1、第一电容C1以及第五开关S5所形成的路径。
请参见图4C、图5E以及图5F，其中图4C为图3所示叠接型转换器的第三电容传递能量至第四电容的时序图；图5E为图3所示叠接型转换器的第三储能操作的示意图；图5F为图3所示叠接型转换器的第三释能操作的示意图。同样地，将图4C中控制第七开关S7的控制信号SS7删去，并且将图5E与图5F的第七开关S7改为二极管D1即可对应本实施方式的记载。如图4C所示，基于在第一时间段(即时间t1至时间t2)，第三开关S3导通，第四开关S4关断以及第六开关S6导通，在第三电容C3上建立的第三电压V3对第二电感L2储能。可配合参见图5E(承前所述，第七开关S7改为二极管D1)，基于第三开关S3导通与第六开关S6导通，在第三电容C3上建立的第三电压V3以第三储能路径PS3对第二电感L2储能，其中第三储能路径PS3为通过第三电容C3、第三开关S3、第二电感L2以及第六开关S6所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第三开关S3关断，第四开关S4导通以及第六开关S6导通，第二电感L2的能量释能至第四电容C4以建立第四电压V4。可配合参见图5F(承前所述，第七开关S7改为二极管D1)，基于第四开关S4导通与第六开关S6导通(即第三开关S3由导通转为关断，第四开关S4由关断转为导通)，第二电感L2的储能以第三释能路径PR3对第四电容C4释能以建立第四电压V4，其中第三释能路径PR3为通过第二电感L2、第六开关S6、第四电容C4以及第四开关S4所形成的路径。
请参见图4D、图5G以及图5H，其中图4D为图3所示叠接型转换器的第四电容传递能量至第三电容的时序图；图5G为图3所示叠接型转换器的第三释能操作的示意图；图5H为图3所示叠接型转换器的第四释能操作的示意图。同样地，将图4D中控制第七开关S7的控制信号SS7删去，并且将图5G与图5H的第七开关S7改为二极管D1即可对应本实施方式的记载。如图4D所示，基于在第一时间段(即时间t1至时间t2)，第三开关S3关断，第四开关S4导通以及第六开关S6导通，在第四电容C4上建立的第四电压V4对第二电感L2储能。可配合参见图5G(承前所述，第七开关S7改为二极管D1)，基于第四开关S4导通与第六开关S6导通，在第四电容C4上建立的第四电压V4以第四储能路径PS4对第二电感L2储能，其中第四储能路径PS4为通过第四电容C4、第六开关S6、第二电感L2以及第四开关S4所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第三开关S3导通，第四开关S4关断以及第六开关S6导通，第二电感L2的能量释能至第三电容C3以建立第三电压V3。可配合参见图5H(承前所述，第七开关S7改为二极管D1)，基于第三开关S3导通与第六开关S6导通(即第三开关S3由关断转为导通，第四开关S4由导通转为关断)，第二电感L2的储能以第四释能路径PR4对 第三电容C3释能以建立第三电压V3，其中第四释能路径PR4为通过第二电感L2、第三开关S3、第三电容C3以及第六开关S6所形成的路径。
请参见图4G、图8A以及图8B，其中图4G为图7所示叠接型转换器的第二电容传递能量至第三电容的时序图；图8A为图7所示叠接型转换器的第七储能操作的示意图；图8B为图7所示叠接型转换器的第七释能操作的示意图。如图4G所示，基于在第一时间段(即时间t1至时间t2)，第二开关S2导通，第三开关S3关断，第五开关S5导通以及第六开关S6关断，在第二电容C2上建立的第二电压V2对第一电感L1储能。可配合参见图8A，基于第二开关S2导通与第五开关S5导通，在第二电容C2上建立的第二电压V2以第七储能路径PS7对第一电感L1储能，其中第七储能路径PS7为通过第二电容C2、第五开关S5、第一电感L1与第二开关S2所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第二开关S2导通，第三开关S3关断，第五开关S5关断以及第六开关S6导通，第一电感L1的能量释能至第三电容C3以建立第三电压V3。可配合参见图8B，基于第二开关S2导通与第六开关S6导通(即第五开关S5由导通转为关断，第六开关S6由关断转为导通)，第一电感L1的储能以第七释能路径PR7对第三电容C3释能以建立第三电压V3，其中第七释能路径PR7为通过第一电感L1、第二开关S2、第三电容C3、第六开关S6与二极管D1所形成的路径。
请参见图4H、图8C以及图8D，其中图4F为图3所示叠接型转换器的第三电容传递能量至第二电容的时序图；图6C为图3所示叠接型转换器的第六储能操作的示意图；图6D为图3所示叠接型转换器的第六释能操作的示意图。如图4H所示，基于在第一时间段(即时间t1至时间t2)，第二开关S2关断，第三开关S3导通，第五开关S5关断以及第六开关S6导通，在第三电容C3上建立的第三电压V3对第二电感L2储能。可配合参见图8C，基于第三开关S3导通与第六开关S6导通，在第三电容C3上建立的第三电压V3以第八储能路径PS8对第二电感L2储能，其中第八储能路径PS8为通过第三电容C3、第三开关S3、第二电感L2与第六开关S6所形成的路径。
在接续第一时间段后的第二时间段(即时间t2至时间t3)，第二开关S2关断，第三开关S3导通，第五开关S5导通以及第六开关S6关断，第二电感L2的能量释能至第二电容C2以建立第二电压V2。可配合参见图8D，基于第三开关S3导通与第五开关S5导通(即第五开关S5由关断转为导通，第六开关S6由导通转为关断)，第二电感L2的储能以第八释能路径PR8对第二电容C2释能以建立第二电压V2，其中第八释能路径PR8为通过第二电感L2、二极管D1、第五开关S5、第二电容C2与第三开关S3所形成的路径。
综上所述，本发明具有以下的特征与优点：本发明所提出的叠接型转换器，只需要7个开关S1～S7以及两个电感L1,L2，即可做到四电容电压V1～V4的控制，并且可通过两电感L1,L2并联使用，以控制电容电压V2,V3，达到节省元件成本、结构简单以及节省空间的优点。因此，相较于现有技术，本发明所提出的叠接型转换器更具备高功率密度的特性。
以上所述，仅为本发明较佳具体实施例的详细说明与附图，惟本发明的特征并不局限于此，并非用以限制本发明，本发明的所有范围应以下述的权利要求范围为准，凡合于本发明权利要求范围的精神与其类似变化的实施例，皆应包括于本发明的范畴中，任何本领域技术人员在本发明的领域内，可轻易思及的变化或修饰皆可涵盖在以下本案的权利要求范围。

Claims (14)

  1. 一种叠接型转换器，包括：
    四电容，包括串联的第一电容、第二电容、第三电容以及第四电容，其中所述第一电容与所述第二电容共接于第一节点，所述第二电容与所述第三电容共接于第二节点，所述第三电容与所述第四电容共接于第三节点，且所述第一电容另连接于第一电压节点，所述第四电容另连接于第二电压节点；
    四开关，包括串联的第一开关、第二开关、第三开关以及第四开关，其中所述第一开关与所述第二开关共接于第四节点，所述第二开关与所述第三开关共接于所述第二节点，所述第三开关与所述第四开关共接于第五节点，且所述第一开关另连接于所述第一电压节点，所述第四开关另连接于所述第二电压节点；
    第五开关与第一电感，共接于第六节点，且所述第五开关另连接于所述第一节点，所述第一电感另连接于所述第四节点；
    第六开关与第二电感，共接于第七节点，且所述第六开关另连接于所述第三节点，所述第二电感另连接于所述第五节点；以及
    第七开关，连接于所述第六节点与所述第七节点之间。
  2. 根据权利要求1所述的叠接型转换器，其中基于在第一时间段，所述第一开关导通，所述第二开关关断，所述第五开关导通以及所述第七开关关断，在所述第一电容上建立的第一电压对所述第一电感储能；
    在接续所述第一时间段后的第二时间段，所述第一开关关断，所述第二开关导通，所述第五开关导通以及所述第七开关关断，所述第一电感的能量释能至所述第二电容以建立第二电压。
  3. 根据权利要求1所述的叠接型转换器，其中基于在第一时间段，所述第一开关关断，所述第二开关导通，所述第五开关导通以及所述第七开关关断，在所述第二电容上建立的第二电压对所述第一电感储能；
    在接续所述第一时间段后的第二时间段，所述第一开关导通，所述第二开关关断，所述第五开关导通以及所述第七开关关断，所述第一电感的能量释能至所述第一电容以建立第一电压。
  4. 根据权利要求1所述的叠接型转换器，其中基于在第一时间段，所述第三开关导通，所述第四开关关断，所述第六开关导通以及所述第七开关关断，在所述第三电容上建立的第三电压对所述第二电感储能；
    在接续所述第一时间段后的第二时间段，所述第三开关关断，所述第四开关导通，所述第六开关导通以及所述第七开关关断，所述第二电感的能量释能至所述第四电容以建立第四电压。
  5. 根据权利要求1所述的叠接型转换器，其中基于在第一时间段，所述第三开关关断，所述第四开关导通，所述第六开关导通以及所述第七开关关断，在所述第四电容上建立的第四电压对所述第二电感储能；
    在接续所述第一时间段后的第二时间段，所述第三开关导通，所述第四开关关断，所述第六开关导通以及所述第七开关关断，所述第二电感的能量释能至所述第三电容以建立第三电压。
  6. 根据权利要求1所述的叠接型转换器，其中基于在第一时间段，所述第二开关导通，第三开关导通，第五开关导通，所述第六开关关断以及所述第七开关导通，在所述第二电容上建立的第二电压对所述第一电感与所述第二电感储能；
    在接续所述第一时间段后的第二时间段，所述第二开关导通，第三开关导通，所述第五开关关断，所述第六开关导通以及所述第七开关导通，所述第一电感与所述第二电感的能量释能至所述第三电容以建立第三电压。
  7. 根据权利要求1所述的叠接型转换器，其中基于在第一时间段，所述第二开关导通，第三开关导通，第五开关关断，所述第六开关导通以及所述第七开关导通，在所述第三电容上建立的第三电压对所述第一电感与所述第二电感储能；
    在接续所述第一时间段后的第二时间段，所述第二开关导通，第三开关导通，所述第五开关导通，所述第六开关关断以及所述第七开关导通，所述第一电感与所述第二电感的能量释能至所述第二电容以建立第二电压。
  8. 一种叠接型转换器，包括：
    四电容，包括串联的第一电容、第二电容、第三电容以及第四电容，其中所述第一电容与所述第二电容共接于第一节点，所述第二电容与所述第三电容共接于第二节点，所述第三电容与所述第四电容共接于第三节点，且所述第一电容另连接于第一电压节点，所述第四电容另连接于第二电压节点；
    四开关，包括串联的第一开关、第二开关、第三开关以及第四开关，其中所述第一开关与所述第二开关共接于第四节点，所述第二开关与所述第三开关共接于所述第二节点，所述第三开关与所述第四开关共接于第五节点，且所述第一开关另连接于所述第一电压节点，所述第四开关另连接于所述第二电压节点；
    第五开关与第一电感，共接于第六节点，且所述第五开关另连接于所述第一节点，所述第一电感另连接于所述第四节点；
    第六开关与第二电感，共接于第七节点，且所述第六开关另连接于所述第三节点，所述第二电感另连接于所述第五节点；以及
    二极管，所述二极管的阴极连接于所述第六节点，所述二极管的阳极连接于所述第七节点。
  9. 根据权利要求8所述的叠接型转换器，其中基于在第一时间段，所述第一开关导通，所述第二开关关断以及所述第五开关导通，在所述第一电容上建立的第一电压对所述第一电感储能；
    在接续所述第一时间段后的第二时间段，所述第一开关关断，所述第二开关导通以及所述第五开关导通，所述第一电感的能量释能至所述第二电容以建立第二电压。
  10. 根据权利要求8所述的叠接型转换器，其中基于在第一时间段，所述第一开关关断，所述第二开关导通以及所述第五开关，在所述第二电容上建立的第二电压对所述第一电感储能；
    在接续所述第一时间段后的第二时间段，所述第一开关导通，所述第二开关关断以及所述第五开关导通，所述第一电感的能量释能至所述第一电容以建立第一电压。
  11. 根据权利要求8所述的叠接型转换器，其中基于在第一时间段，所述第三开关导通，所述第四开关关断以及所述第六开关导通，在所述第三电容上建立的第三电压对所述第二电感储能；
    在接续所述第一时间段后的第二时间段，所述第三开关关断，所述第四开关导通以及所述第六开关导通，所述第二电感的能量释能至所述第四电容以建立第四电压。
  12. 根据权利要求8所述的叠接型转换器，其中基于在第一时间段，所述第三开关关断，所述第四开关导通以及所述第六开关导通，在所述第四电容上建立的第四电压对所述第二电感储能；
    在接续所述第一时间段后的第二时间段，所述第三开关导通，所述第四开关关断以及所述第六开关导通，所述第二电感的能量释能至所述第三电容以建立第三电压。
  13. 根据权利要求8所述的叠接型转换器，其中基于在第一时间段，所述第二开关导通，第三开关关断，第五开关导通以及所述第六开关关断，在所述第二电容上建立的第二电压对所述第一电感储能；
    在接续所述第一时间段后的第二时间段，所述第二开关导通，第三开关关断，所述第五开关关断以及所述第六开关导通，所述第一电感的能量释能至所述第三电容以建立第三电压。
  14. 根据权利要求8所述的叠接型转换器，其中基于在第一时间段，所述第二开关关断，第三开关导通，第五开关关断以及所述第六开关导通，在所述第三电容上建立的第三电压对所述第二电感储能；
    在接续所述第一时间段后的第二时间段，所述第二开关关断，第三开关导通，所述第五开关导通以及所述第六开关关断，所述第二电感的能量释能至所述第二电容以建立第二电压。
PCT/CN2024/127231 2024-06-05 2024-10-25 叠接型转换器 Pending WO2025251503A1 (zh)

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TWI822432B (zh) 2022-04-13 2023-11-11 立錡科技股份有限公司 功率轉換器及其控制方法
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US20180269803A1 (en) * 2015-11-24 2018-09-20 Abb Schweiz Ag Four-level power converter
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